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pseries: Consolidate construction of /vdevice device tree node
[mirror_qemu.git] / hw / ppc / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/kvm.h"
40 #include "sysemu/device_tree.h"
41 #include "kvm_ppc.h"
42 #include "migration/migration.h"
43 #include "mmu-hash64.h"
44 #include "qom/cpu.h"
45
46 #include "hw/boards.h"
47 #include "hw/ppc/ppc.h"
48 #include "hw/loader.h"
49
50 #include "hw/ppc/fdt.h"
51 #include "hw/ppc/spapr.h"
52 #include "hw/ppc/spapr_vio.h"
53 #include "hw/pci-host/spapr.h"
54 #include "hw/ppc/xics.h"
55 #include "hw/pci/msi.h"
56
57 #include "hw/pci/pci.h"
58 #include "hw/scsi/scsi.h"
59 #include "hw/virtio/virtio-scsi.h"
60
61 #include "exec/address-spaces.h"
62 #include "hw/usb.h"
63 #include "qemu/config-file.h"
64 #include "qemu/error-report.h"
65 #include "trace.h"
66 #include "hw/nmi.h"
67
68 #include "hw/compat.h"
69 #include "qemu/cutils.h"
70 #include "hw/ppc/spapr_cpu_core.h"
71 #include "qmp-commands.h"
72
73 #include <libfdt.h>
74
75 /* SLOF memory layout:
76 *
77 * SLOF raw image loaded at 0, copies its romfs right below the flat
78 * device-tree, then position SLOF itself 31M below that
79 *
80 * So we set FW_OVERHEAD to 40MB which should account for all of that
81 * and more
82 *
83 * We load our kernel at 4M, leaving space for SLOF initial image
84 */
85 #define FDT_MAX_SIZE 0x100000
86 #define RTAS_MAX_SIZE 0x10000
87 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
88 #define FW_MAX_SIZE 0x400000
89 #define FW_FILE_NAME "slof.bin"
90 #define FW_OVERHEAD 0x2800000
91 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
92
93 #define MIN_RMA_SLOF 128UL
94
95 #define PHANDLE_XICP 0x00001111
96
97 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
98
99 static XICSState *try_create_xics(const char *type, int nr_servers,
100 int nr_irqs, Error **errp)
101 {
102 Error *err = NULL;
103 DeviceState *dev;
104
105 dev = qdev_create(NULL, type);
106 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
107 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
108 object_property_set_bool(OBJECT(dev), true, "realized", &err);
109 if (err) {
110 error_propagate(errp, err);
111 object_unparent(OBJECT(dev));
112 return NULL;
113 }
114 return XICS_COMMON(dev);
115 }
116
117 static XICSState *xics_system_init(MachineState *machine,
118 int nr_servers, int nr_irqs, Error **errp)
119 {
120 XICSState *xics = NULL;
121
122 if (kvm_enabled()) {
123 Error *err = NULL;
124
125 if (machine_kernel_irqchip_allowed(machine)) {
126 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
127 &err);
128 }
129 if (machine_kernel_irqchip_required(machine) && !xics) {
130 error_reportf_err(err,
131 "kernel_irqchip requested but unavailable: ");
132 } else {
133 error_free(err);
134 }
135 }
136
137 if (!xics) {
138 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
139 }
140
141 return xics;
142 }
143
144 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
145 int smt_threads)
146 {
147 int i, ret = 0;
148 uint32_t servers_prop[smt_threads];
149 uint32_t gservers_prop[smt_threads * 2];
150 int index = ppc_get_vcpu_dt_id(cpu);
151
152 if (cpu->cpu_version) {
153 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
154 if (ret < 0) {
155 return ret;
156 }
157 }
158
159 /* Build interrupt servers and gservers properties */
160 for (i = 0; i < smt_threads; i++) {
161 servers_prop[i] = cpu_to_be32(index + i);
162 /* Hack, direct the group queues back to cpu 0 */
163 gservers_prop[i*2] = cpu_to_be32(index + i);
164 gservers_prop[i*2 + 1] = 0;
165 }
166 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
167 servers_prop, sizeof(servers_prop));
168 if (ret < 0) {
169 return ret;
170 }
171 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
172 gservers_prop, sizeof(gservers_prop));
173
174 return ret;
175 }
176
177 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
178 {
179 int ret = 0;
180 PowerPCCPU *cpu = POWERPC_CPU(cs);
181 int index = ppc_get_vcpu_dt_id(cpu);
182 uint32_t associativity[] = {cpu_to_be32(0x5),
183 cpu_to_be32(0x0),
184 cpu_to_be32(0x0),
185 cpu_to_be32(0x0),
186 cpu_to_be32(cs->numa_node),
187 cpu_to_be32(index)};
188
189 /* Advertise NUMA via ibm,associativity */
190 if (nb_numa_nodes > 1) {
191 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
192 sizeof(associativity));
193 }
194
195 return ret;
196 }
197
198 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
199 {
200 int ret = 0, offset, cpus_offset;
201 CPUState *cs;
202 char cpu_model[32];
203 int smt = kvmppc_smt_threads();
204 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
205
206 CPU_FOREACH(cs) {
207 PowerPCCPU *cpu = POWERPC_CPU(cs);
208 DeviceClass *dc = DEVICE_GET_CLASS(cs);
209 int index = ppc_get_vcpu_dt_id(cpu);
210
211 if ((index % smt) != 0) {
212 continue;
213 }
214
215 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
216
217 cpus_offset = fdt_path_offset(fdt, "/cpus");
218 if (cpus_offset < 0) {
219 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
220 "cpus");
221 if (cpus_offset < 0) {
222 return cpus_offset;
223 }
224 }
225 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
226 if (offset < 0) {
227 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
228 if (offset < 0) {
229 return offset;
230 }
231 }
232
233 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
234 pft_size_prop, sizeof(pft_size_prop));
235 if (ret < 0) {
236 return ret;
237 }
238
239 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
240 if (ret < 0) {
241 return ret;
242 }
243
244 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
245 ppc_get_compat_smt_threads(cpu));
246 if (ret < 0) {
247 return ret;
248 }
249 }
250 return ret;
251 }
252
253 static hwaddr spapr_node0_size(void)
254 {
255 MachineState *machine = MACHINE(qdev_get_machine());
256
257 if (nb_numa_nodes) {
258 int i;
259 for (i = 0; i < nb_numa_nodes; ++i) {
260 if (numa_info[i].node_mem) {
261 return MIN(pow2floor(numa_info[i].node_mem),
262 machine->ram_size);
263 }
264 }
265 }
266 return machine->ram_size;
267 }
268
269 static void add_str(GString *s, const gchar *s1)
270 {
271 g_string_append_len(s, s1, strlen(s1) + 1);
272 }
273
274 static void *spapr_create_fdt_skel(sPAPRMachineState *spapr)
275 {
276 void *fdt;
277 char *buf;
278
279 fdt = g_malloc0(FDT_MAX_SIZE);
280 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
281
282 _FDT((fdt_finish_reservemap(fdt)));
283
284 /* Root node */
285 _FDT((fdt_begin_node(fdt, "")));
286 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
287 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
288 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
289
290 /*
291 * Add info to guest to indentify which host is it being run on
292 * and what is the uuid of the guest
293 */
294 if (kvmppc_get_host_model(&buf)) {
295 _FDT((fdt_property_string(fdt, "host-model", buf)));
296 g_free(buf);
297 }
298 if (kvmppc_get_host_serial(&buf)) {
299 _FDT((fdt_property_string(fdt, "host-serial", buf)));
300 g_free(buf);
301 }
302
303 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
304
305 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
306 if (qemu_uuid_set) {
307 _FDT((fdt_property_string(fdt, "system-id", buf)));
308 }
309 g_free(buf);
310
311 if (qemu_get_vm_name()) {
312 _FDT((fdt_property_string(fdt, "ibm,partition-name",
313 qemu_get_vm_name())));
314 }
315
316 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
317 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
318
319 _FDT((fdt_end_node(fdt))); /* close root node */
320 _FDT((fdt_finish(fdt)));
321
322 return fdt;
323 }
324
325 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
326 hwaddr size)
327 {
328 uint32_t associativity[] = {
329 cpu_to_be32(0x4), /* length */
330 cpu_to_be32(0x0), cpu_to_be32(0x0),
331 cpu_to_be32(0x0), cpu_to_be32(nodeid)
332 };
333 char mem_name[32];
334 uint64_t mem_reg_property[2];
335 int off;
336
337 mem_reg_property[0] = cpu_to_be64(start);
338 mem_reg_property[1] = cpu_to_be64(size);
339
340 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
341 off = fdt_add_subnode(fdt, 0, mem_name);
342 _FDT(off);
343 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
344 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
345 sizeof(mem_reg_property))));
346 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
347 sizeof(associativity))));
348 return off;
349 }
350
351 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
352 {
353 MachineState *machine = MACHINE(spapr);
354 hwaddr mem_start, node_size;
355 int i, nb_nodes = nb_numa_nodes;
356 NodeInfo *nodes = numa_info;
357 NodeInfo ramnode;
358
359 /* No NUMA nodes, assume there is just one node with whole RAM */
360 if (!nb_numa_nodes) {
361 nb_nodes = 1;
362 ramnode.node_mem = machine->ram_size;
363 nodes = &ramnode;
364 }
365
366 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
367 if (!nodes[i].node_mem) {
368 continue;
369 }
370 if (mem_start >= machine->ram_size) {
371 node_size = 0;
372 } else {
373 node_size = nodes[i].node_mem;
374 if (node_size > machine->ram_size - mem_start) {
375 node_size = machine->ram_size - mem_start;
376 }
377 }
378 if (!mem_start) {
379 /* ppc_spapr_init() checks for rma_size <= node0_size already */
380 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
381 mem_start += spapr->rma_size;
382 node_size -= spapr->rma_size;
383 }
384 for ( ; node_size; ) {
385 hwaddr sizetmp = pow2floor(node_size);
386
387 /* mem_start != 0 here */
388 if (ctzl(mem_start) < ctzl(sizetmp)) {
389 sizetmp = 1ULL << ctzl(mem_start);
390 }
391
392 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
393 node_size -= sizetmp;
394 mem_start += sizetmp;
395 }
396 }
397
398 return 0;
399 }
400
401 /* Populate the "ibm,pa-features" property */
402 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
403 {
404 uint8_t pa_features_206[] = { 6, 0,
405 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
406 uint8_t pa_features_207[] = { 24, 0,
407 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
408 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
409 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
410 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
411 uint8_t *pa_features;
412 size_t pa_size;
413
414 switch (env->mmu_model) {
415 case POWERPC_MMU_2_06:
416 case POWERPC_MMU_2_06a:
417 pa_features = pa_features_206;
418 pa_size = sizeof(pa_features_206);
419 break;
420 case POWERPC_MMU_2_07:
421 case POWERPC_MMU_2_07a:
422 pa_features = pa_features_207;
423 pa_size = sizeof(pa_features_207);
424 break;
425 default:
426 return;
427 }
428
429 if (env->ci_large_pages) {
430 /*
431 * Note: we keep CI large pages off by default because a 64K capable
432 * guest provisioned with large pages might otherwise try to map a qemu
433 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
434 * even if that qemu runs on a 4k host.
435 * We dd this bit back here if we are confident this is not an issue
436 */
437 pa_features[3] |= 0x20;
438 }
439 if (kvmppc_has_cap_htm() && pa_size > 24) {
440 pa_features[24] |= 0x80; /* Transactional memory support */
441 }
442
443 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
444 }
445
446 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
447 sPAPRMachineState *spapr)
448 {
449 PowerPCCPU *cpu = POWERPC_CPU(cs);
450 CPUPPCState *env = &cpu->env;
451 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
452 int index = ppc_get_vcpu_dt_id(cpu);
453 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
454 0xffffffff, 0xffffffff};
455 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
456 : SPAPR_TIMEBASE_FREQ;
457 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
458 uint32_t page_sizes_prop[64];
459 size_t page_sizes_prop_size;
460 uint32_t vcpus_per_socket = smp_threads * smp_cores;
461 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
462 sPAPRDRConnector *drc;
463 sPAPRDRConnectorClass *drck;
464 int drc_index;
465
466 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
467 if (drc) {
468 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
469 drc_index = drck->get_index(drc);
470 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
471 }
472
473 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
474 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
475
476 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
477 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
478 env->dcache_line_size)));
479 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
480 env->dcache_line_size)));
481 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
482 env->icache_line_size)));
483 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
484 env->icache_line_size)));
485
486 if (pcc->l1_dcache_size) {
487 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
488 pcc->l1_dcache_size)));
489 } else {
490 error_report("Warning: Unknown L1 dcache size for cpu");
491 }
492 if (pcc->l1_icache_size) {
493 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
494 pcc->l1_icache_size)));
495 } else {
496 error_report("Warning: Unknown L1 icache size for cpu");
497 }
498
499 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
500 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
501 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
502 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
503 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
504 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
505
506 if (env->spr_cb[SPR_PURR].oea_read) {
507 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
508 }
509
510 if (env->mmu_model & POWERPC_MMU_1TSEG) {
511 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
512 segs, sizeof(segs))));
513 }
514
515 /* Advertise VMX/VSX (vector extensions) if available
516 * 0 / no property == no vector extensions
517 * 1 == VMX / Altivec available
518 * 2 == VSX available */
519 if (env->insns_flags & PPC_ALTIVEC) {
520 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
521
522 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
523 }
524
525 /* Advertise DFP (Decimal Floating Point) if available
526 * 0 / no property == no DFP
527 * 1 == DFP available */
528 if (env->insns_flags2 & PPC2_DFP) {
529 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
530 }
531
532 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
533 sizeof(page_sizes_prop));
534 if (page_sizes_prop_size) {
535 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
536 page_sizes_prop, page_sizes_prop_size)));
537 }
538
539 spapr_populate_pa_features(env, fdt, offset);
540
541 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
542 cs->cpu_index / vcpus_per_socket)));
543
544 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
545 pft_size_prop, sizeof(pft_size_prop))));
546
547 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
548
549 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
550 ppc_get_compat_smt_threads(cpu)));
551 }
552
553 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
554 {
555 CPUState *cs;
556 int cpus_offset;
557 char *nodename;
558 int smt = kvmppc_smt_threads();
559
560 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
561 _FDT(cpus_offset);
562 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
563 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
564
565 /*
566 * We walk the CPUs in reverse order to ensure that CPU DT nodes
567 * created by fdt_add_subnode() end up in the right order in FDT
568 * for the guest kernel the enumerate the CPUs correctly.
569 */
570 CPU_FOREACH_REVERSE(cs) {
571 PowerPCCPU *cpu = POWERPC_CPU(cs);
572 int index = ppc_get_vcpu_dt_id(cpu);
573 DeviceClass *dc = DEVICE_GET_CLASS(cs);
574 int offset;
575
576 if ((index % smt) != 0) {
577 continue;
578 }
579
580 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
581 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
582 g_free(nodename);
583 _FDT(offset);
584 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
585 }
586
587 }
588
589 /*
590 * Adds ibm,dynamic-reconfiguration-memory node.
591 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
592 * of this device tree node.
593 */
594 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
595 {
596 MachineState *machine = MACHINE(spapr);
597 int ret, i, offset;
598 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
599 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
600 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
601 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
602 memory_region_size(&spapr->hotplug_memory.mr)) /
603 lmb_size;
604 uint32_t *int_buf, *cur_index, buf_len;
605 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
606
607 /*
608 * Don't create the node if there is no hotpluggable memory
609 */
610 if (machine->ram_size == machine->maxram_size) {
611 return 0;
612 }
613
614 /*
615 * Allocate enough buffer size to fit in ibm,dynamic-memory
616 * or ibm,associativity-lookup-arrays
617 */
618 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
619 * sizeof(uint32_t);
620 cur_index = int_buf = g_malloc0(buf_len);
621
622 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
623
624 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
625 sizeof(prop_lmb_size));
626 if (ret < 0) {
627 goto out;
628 }
629
630 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
631 if (ret < 0) {
632 goto out;
633 }
634
635 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
636 if (ret < 0) {
637 goto out;
638 }
639
640 /* ibm,dynamic-memory */
641 int_buf[0] = cpu_to_be32(nr_lmbs);
642 cur_index++;
643 for (i = 0; i < nr_lmbs; i++) {
644 uint64_t addr = i * lmb_size;
645 uint32_t *dynamic_memory = cur_index;
646
647 if (i >= hotplug_lmb_start) {
648 sPAPRDRConnector *drc;
649 sPAPRDRConnectorClass *drck;
650
651 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
652 g_assert(drc);
653 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
654
655 dynamic_memory[0] = cpu_to_be32(addr >> 32);
656 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
657 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
658 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
659 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
660 if (memory_region_present(get_system_memory(), addr)) {
661 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
662 } else {
663 dynamic_memory[5] = cpu_to_be32(0);
664 }
665 } else {
666 /*
667 * LMB information for RMA, boot time RAM and gap b/n RAM and
668 * hotplug memory region -- all these are marked as reserved
669 * and as having no valid DRC.
670 */
671 dynamic_memory[0] = cpu_to_be32(addr >> 32);
672 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
673 dynamic_memory[2] = cpu_to_be32(0);
674 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
675 dynamic_memory[4] = cpu_to_be32(-1);
676 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
677 SPAPR_LMB_FLAGS_DRC_INVALID);
678 }
679
680 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
681 }
682 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
683 if (ret < 0) {
684 goto out;
685 }
686
687 /* ibm,associativity-lookup-arrays */
688 cur_index = int_buf;
689 int_buf[0] = cpu_to_be32(nr_nodes);
690 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
691 cur_index += 2;
692 for (i = 0; i < nr_nodes; i++) {
693 uint32_t associativity[] = {
694 cpu_to_be32(0x0),
695 cpu_to_be32(0x0),
696 cpu_to_be32(0x0),
697 cpu_to_be32(i)
698 };
699 memcpy(cur_index, associativity, sizeof(associativity));
700 cur_index += 4;
701 }
702 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
703 (cur_index - int_buf) * sizeof(uint32_t));
704 out:
705 g_free(int_buf);
706 return ret;
707 }
708
709 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
710 target_ulong addr, target_ulong size,
711 bool cpu_update, bool memory_update)
712 {
713 void *fdt, *fdt_skel;
714 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
715 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
716
717 size -= sizeof(hdr);
718
719 /* Create sceleton */
720 fdt_skel = g_malloc0(size);
721 _FDT((fdt_create(fdt_skel, size)));
722 _FDT((fdt_begin_node(fdt_skel, "")));
723 _FDT((fdt_end_node(fdt_skel)));
724 _FDT((fdt_finish(fdt_skel)));
725 fdt = g_malloc0(size);
726 _FDT((fdt_open_into(fdt_skel, fdt, size)));
727 g_free(fdt_skel);
728
729 /* Fixup cpu nodes */
730 if (cpu_update) {
731 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
732 }
733
734 /* Generate ibm,dynamic-reconfiguration-memory node if required */
735 if (memory_update && smc->dr_lmb_enabled) {
736 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
737 }
738
739 /* Pack resulting tree */
740 _FDT((fdt_pack(fdt)));
741
742 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
743 trace_spapr_cas_failed(size);
744 return -1;
745 }
746
747 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
748 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
749 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
750 g_free(fdt);
751
752 return 0;
753 }
754
755 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
756 {
757 int rtas;
758 GString *hypertas = g_string_sized_new(256);
759 GString *qemu_hypertas = g_string_sized_new(256);
760 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
761 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
762 memory_region_size(&spapr->hotplug_memory.mr);
763 uint32_t lrdr_capacity[] = {
764 cpu_to_be32(max_hotplug_addr >> 32),
765 cpu_to_be32(max_hotplug_addr & 0xffffffff),
766 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
767 cpu_to_be32(max_cpus / smp_threads),
768 };
769
770 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
771
772 /* hypertas */
773 add_str(hypertas, "hcall-pft");
774 add_str(hypertas, "hcall-term");
775 add_str(hypertas, "hcall-dabr");
776 add_str(hypertas, "hcall-interrupt");
777 add_str(hypertas, "hcall-tce");
778 add_str(hypertas, "hcall-vio");
779 add_str(hypertas, "hcall-splpar");
780 add_str(hypertas, "hcall-bulk");
781 add_str(hypertas, "hcall-set-mode");
782 add_str(hypertas, "hcall-sprg0");
783 add_str(hypertas, "hcall-copy");
784 add_str(hypertas, "hcall-debug");
785 add_str(qemu_hypertas, "hcall-memop1");
786
787 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
788 add_str(hypertas, "hcall-multi-tce");
789 }
790 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
791 hypertas->str, hypertas->len));
792 g_string_free(hypertas, TRUE);
793 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
794 qemu_hypertas->str, qemu_hypertas->len));
795 g_string_free(qemu_hypertas, TRUE);
796
797 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
798 refpoints, sizeof(refpoints)));
799
800 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
801 RTAS_ERROR_LOG_MAX));
802 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
803 RTAS_EVENT_SCAN_RATE));
804
805 if (msi_nonbroken) {
806 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
807 }
808
809 /*
810 * According to PAPR, rtas ibm,os-term does not guarantee a return
811 * back to the guest cpu.
812 *
813 * While an additional ibm,extended-os-term property indicates
814 * that rtas call return will always occur. Set this property.
815 */
816 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
817
818 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
819 lrdr_capacity, sizeof(lrdr_capacity)));
820
821 spapr_dt_rtas_tokens(fdt, rtas);
822 }
823
824 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
825 {
826 MachineState *machine = MACHINE(spapr);
827 int chosen;
828 const char *boot_device = machine->boot_order;
829 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
830 size_t cb = 0;
831 char *bootlist = get_boot_devices_list(&cb, true);
832 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
833
834 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
835
836 /* Set Form1_affinity */
837 _FDT(fdt_setprop(fdt, chosen, "ibm,architecture-vec-5",
838 vec5, sizeof(vec5)));
839
840 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
841 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
842 spapr->initrd_base));
843 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
844 spapr->initrd_base + spapr->initrd_size));
845
846 if (spapr->kernel_size) {
847 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
848 cpu_to_be64(spapr->kernel_size) };
849
850 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
851 &kprop, sizeof(kprop)));
852 if (spapr->kernel_le) {
853 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
854 }
855 }
856 if (boot_menu) {
857 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
858 }
859 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
860 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
861 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
862
863 if (cb && bootlist) {
864 int i;
865
866 for (i = 0; i < cb; i++) {
867 if (bootlist[i] == '\n') {
868 bootlist[i] = ' ';
869 }
870 }
871 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
872 }
873
874 if (boot_device && strlen(boot_device)) {
875 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
876 }
877
878 if (!spapr->has_graphics && stdout_path) {
879 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
880 }
881
882 g_free(stdout_path);
883 g_free(bootlist);
884 }
885
886 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
887 {
888 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
889 * KVM to work under pHyp with some guest co-operation */
890 int hypervisor;
891 uint8_t hypercall[16];
892
893 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
894 /* indicate KVM hypercall interface */
895 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
896 if (kvmppc_has_cap_fixup_hcalls()) {
897 /*
898 * Older KVM versions with older guest kernels were broken
899 * with the magic page, don't allow the guest to map it.
900 */
901 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
902 sizeof(hypercall))) {
903 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
904 hypercall, sizeof(hypercall)));
905 }
906 }
907 }
908
909 static void *spapr_build_fdt(sPAPRMachineState *spapr,
910 hwaddr rtas_addr,
911 hwaddr rtas_size)
912 {
913 MachineState *machine = MACHINE(qdev_get_machine());
914 MachineClass *mc = MACHINE_GET_CLASS(machine);
915 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
916 int ret;
917 void *fdt;
918 sPAPRPHBState *phb;
919
920 fdt = g_malloc(FDT_MAX_SIZE);
921
922 /* open out the base tree into a temp buffer for the final tweaks */
923 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
924
925 /* /interrupt controller */
926 spapr_dt_xics(spapr->xics, fdt, PHANDLE_XICP);
927
928 ret = spapr_populate_memory(spapr, fdt);
929 if (ret < 0) {
930 error_report("couldn't setup memory nodes in fdt");
931 exit(1);
932 }
933
934 /* /vdevice */
935 spapr_dt_vdevice(spapr->vio_bus, fdt);
936
937 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
938 ret = spapr_rng_populate_dt(fdt);
939 if (ret < 0) {
940 error_report("could not set up rng device in the fdt");
941 exit(1);
942 }
943 }
944
945 QLIST_FOREACH(phb, &spapr->phbs, list) {
946 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
947 if (ret < 0) {
948 error_report("couldn't setup PCI devices in fdt");
949 exit(1);
950 }
951 }
952
953 /* cpus */
954 spapr_populate_cpus_dt_node(fdt, spapr);
955
956 if (smc->dr_lmb_enabled) {
957 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
958 }
959
960 if (mc->query_hotpluggable_cpus) {
961 int offset = fdt_path_offset(fdt, "/cpus");
962 ret = spapr_drc_populate_dt(fdt, offset, NULL,
963 SPAPR_DR_CONNECTOR_TYPE_CPU);
964 if (ret < 0) {
965 error_report("Couldn't set up CPU DR device tree properties");
966 exit(1);
967 }
968 }
969
970 /* /event-sources */
971 spapr_dt_events(fdt, spapr->check_exception_irq);
972
973 /* /rtas */
974 spapr_dt_rtas(spapr, fdt);
975
976 /* /chosen */
977 spapr_dt_chosen(spapr, fdt);
978
979 /* /hypervisor */
980 if (kvm_enabled()) {
981 spapr_dt_hypervisor(spapr, fdt);
982 }
983
984 /* Build memory reserve map */
985 if (spapr->kernel_size) {
986 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
987 }
988 if (spapr->initrd_size) {
989 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
990 }
991
992 return fdt;
993 }
994
995 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
996 {
997 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
998 }
999
1000 static void emulate_spapr_hypercall(PowerPCCPU *cpu)
1001 {
1002 CPUPPCState *env = &cpu->env;
1003
1004 if (msr_pr) {
1005 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1006 env->gpr[3] = H_PRIVILEGE;
1007 } else {
1008 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1009 }
1010 }
1011
1012 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1013 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1014 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1015 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1016 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1017
1018 /*
1019 * Get the fd to access the kernel htab, re-opening it if necessary
1020 */
1021 static int get_htab_fd(sPAPRMachineState *spapr)
1022 {
1023 if (spapr->htab_fd >= 0) {
1024 return spapr->htab_fd;
1025 }
1026
1027 spapr->htab_fd = kvmppc_get_htab_fd(false);
1028 if (spapr->htab_fd < 0) {
1029 error_report("Unable to open fd for reading hash table from KVM: %s",
1030 strerror(errno));
1031 }
1032
1033 return spapr->htab_fd;
1034 }
1035
1036 static void close_htab_fd(sPAPRMachineState *spapr)
1037 {
1038 if (spapr->htab_fd >= 0) {
1039 close(spapr->htab_fd);
1040 }
1041 spapr->htab_fd = -1;
1042 }
1043
1044 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1045 {
1046 int shift;
1047
1048 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1049 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1050 * that's much more than is needed for Linux guests */
1051 shift = ctz64(pow2ceil(ramsize)) - 7;
1052 shift = MAX(shift, 18); /* Minimum architected size */
1053 shift = MIN(shift, 46); /* Maximum architected size */
1054 return shift;
1055 }
1056
1057 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1058 Error **errp)
1059 {
1060 long rc;
1061
1062 /* Clean up any HPT info from a previous boot */
1063 g_free(spapr->htab);
1064 spapr->htab = NULL;
1065 spapr->htab_shift = 0;
1066 close_htab_fd(spapr);
1067
1068 rc = kvmppc_reset_htab(shift);
1069 if (rc < 0) {
1070 /* kernel-side HPT needed, but couldn't allocate one */
1071 error_setg_errno(errp, errno,
1072 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1073 shift);
1074 /* This is almost certainly fatal, but if the caller really
1075 * wants to carry on with shift == 0, it's welcome to try */
1076 } else if (rc > 0) {
1077 /* kernel-side HPT allocated */
1078 if (rc != shift) {
1079 error_setg(errp,
1080 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1081 shift, rc);
1082 }
1083
1084 spapr->htab_shift = shift;
1085 spapr->htab = NULL;
1086 } else {
1087 /* kernel-side HPT not needed, allocate in userspace instead */
1088 size_t size = 1ULL << shift;
1089 int i;
1090
1091 spapr->htab = qemu_memalign(size, size);
1092 if (!spapr->htab) {
1093 error_setg_errno(errp, errno,
1094 "Could not allocate HPT of order %d", shift);
1095 return;
1096 }
1097
1098 memset(spapr->htab, 0, size);
1099 spapr->htab_shift = shift;
1100
1101 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1102 DIRTY_HPTE(HPTE(spapr->htab, i));
1103 }
1104 }
1105 }
1106
1107 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1108 {
1109 bool matched = false;
1110
1111 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1112 matched = true;
1113 }
1114
1115 if (!matched) {
1116 error_report("Device %s is not supported by this machine yet.",
1117 qdev_fw_name(DEVICE(sbdev)));
1118 exit(1);
1119 }
1120 }
1121
1122 static void ppc_spapr_reset(void)
1123 {
1124 MachineState *machine = MACHINE(qdev_get_machine());
1125 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1126 PowerPCCPU *first_ppc_cpu;
1127 uint32_t rtas_limit;
1128 hwaddr rtas_addr, fdt_addr;
1129 void *fdt;
1130 int rc;
1131
1132 /* Check for unknown sysbus devices */
1133 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1134
1135 /* Allocate and/or reset the hash page table */
1136 spapr_reallocate_hpt(spapr,
1137 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1138 &error_fatal);
1139
1140 /* Update the RMA size if necessary */
1141 if (spapr->vrma_adjust) {
1142 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1143 spapr->htab_shift);
1144 }
1145
1146 qemu_devices_reset();
1147
1148 /*
1149 * We place the device tree and RTAS just below either the top of the RMA,
1150 * or just below 2GB, whichever is lowere, so that it can be
1151 * processed with 32-bit real mode code if necessary
1152 */
1153 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1154 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1155 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1156
1157 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1158
1159 spapr_load_rtas(spapr, fdt, rtas_addr);
1160
1161 rc = fdt_pack(fdt);
1162
1163 /* Should only fail if we've built a corrupted tree */
1164 assert(rc == 0);
1165
1166 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1167 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1168 fdt_totalsize(fdt), FDT_MAX_SIZE);
1169 exit(1);
1170 }
1171
1172 /* Load the fdt */
1173 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1174 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1175 g_free(fdt);
1176
1177 /* Set up the entry state */
1178 first_ppc_cpu = POWERPC_CPU(first_cpu);
1179 first_ppc_cpu->env.gpr[3] = fdt_addr;
1180 first_ppc_cpu->env.gpr[5] = 0;
1181 first_cpu->halted = 0;
1182 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1183
1184 }
1185
1186 static void spapr_create_nvram(sPAPRMachineState *spapr)
1187 {
1188 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1189 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1190
1191 if (dinfo) {
1192 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1193 &error_fatal);
1194 }
1195
1196 qdev_init_nofail(dev);
1197
1198 spapr->nvram = (struct sPAPRNVRAM *)dev;
1199 }
1200
1201 static void spapr_rtc_create(sPAPRMachineState *spapr)
1202 {
1203 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1204
1205 qdev_init_nofail(dev);
1206 spapr->rtc = dev;
1207
1208 object_property_add_alias(qdev_get_machine(), "rtc-time",
1209 OBJECT(spapr->rtc), "date", NULL);
1210 }
1211
1212 /* Returns whether we want to use VGA or not */
1213 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1214 {
1215 switch (vga_interface_type) {
1216 case VGA_NONE:
1217 return false;
1218 case VGA_DEVICE:
1219 return true;
1220 case VGA_STD:
1221 case VGA_VIRTIO:
1222 return pci_vga_init(pci_bus) != NULL;
1223 default:
1224 error_setg(errp,
1225 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1226 return false;
1227 }
1228 }
1229
1230 static int spapr_post_load(void *opaque, int version_id)
1231 {
1232 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1233 int err = 0;
1234
1235 /* In earlier versions, there was no separate qdev for the PAPR
1236 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1237 * So when migrating from those versions, poke the incoming offset
1238 * value into the RTC device */
1239 if (version_id < 3) {
1240 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1241 }
1242
1243 return err;
1244 }
1245
1246 static bool version_before_3(void *opaque, int version_id)
1247 {
1248 return version_id < 3;
1249 }
1250
1251 static const VMStateDescription vmstate_spapr = {
1252 .name = "spapr",
1253 .version_id = 3,
1254 .minimum_version_id = 1,
1255 .post_load = spapr_post_load,
1256 .fields = (VMStateField[]) {
1257 /* used to be @next_irq */
1258 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1259
1260 /* RTC offset */
1261 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1262
1263 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1264 VMSTATE_END_OF_LIST()
1265 },
1266 };
1267
1268 static int htab_save_setup(QEMUFile *f, void *opaque)
1269 {
1270 sPAPRMachineState *spapr = opaque;
1271
1272 /* "Iteration" header */
1273 qemu_put_be32(f, spapr->htab_shift);
1274
1275 if (spapr->htab) {
1276 spapr->htab_save_index = 0;
1277 spapr->htab_first_pass = true;
1278 } else {
1279 assert(kvm_enabled());
1280 }
1281
1282
1283 return 0;
1284 }
1285
1286 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1287 int64_t max_ns)
1288 {
1289 bool has_timeout = max_ns != -1;
1290 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1291 int index = spapr->htab_save_index;
1292 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1293
1294 assert(spapr->htab_first_pass);
1295
1296 do {
1297 int chunkstart;
1298
1299 /* Consume invalid HPTEs */
1300 while ((index < htabslots)
1301 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1302 index++;
1303 CLEAN_HPTE(HPTE(spapr->htab, index));
1304 }
1305
1306 /* Consume valid HPTEs */
1307 chunkstart = index;
1308 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1309 && HPTE_VALID(HPTE(spapr->htab, index))) {
1310 index++;
1311 CLEAN_HPTE(HPTE(spapr->htab, index));
1312 }
1313
1314 if (index > chunkstart) {
1315 int n_valid = index - chunkstart;
1316
1317 qemu_put_be32(f, chunkstart);
1318 qemu_put_be16(f, n_valid);
1319 qemu_put_be16(f, 0);
1320 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1321 HASH_PTE_SIZE_64 * n_valid);
1322
1323 if (has_timeout &&
1324 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1325 break;
1326 }
1327 }
1328 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1329
1330 if (index >= htabslots) {
1331 assert(index == htabslots);
1332 index = 0;
1333 spapr->htab_first_pass = false;
1334 }
1335 spapr->htab_save_index = index;
1336 }
1337
1338 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1339 int64_t max_ns)
1340 {
1341 bool final = max_ns < 0;
1342 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1343 int examined = 0, sent = 0;
1344 int index = spapr->htab_save_index;
1345 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1346
1347 assert(!spapr->htab_first_pass);
1348
1349 do {
1350 int chunkstart, invalidstart;
1351
1352 /* Consume non-dirty HPTEs */
1353 while ((index < htabslots)
1354 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1355 index++;
1356 examined++;
1357 }
1358
1359 chunkstart = index;
1360 /* Consume valid dirty HPTEs */
1361 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1362 && HPTE_DIRTY(HPTE(spapr->htab, index))
1363 && HPTE_VALID(HPTE(spapr->htab, index))) {
1364 CLEAN_HPTE(HPTE(spapr->htab, index));
1365 index++;
1366 examined++;
1367 }
1368
1369 invalidstart = index;
1370 /* Consume invalid dirty HPTEs */
1371 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1372 && HPTE_DIRTY(HPTE(spapr->htab, index))
1373 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1374 CLEAN_HPTE(HPTE(spapr->htab, index));
1375 index++;
1376 examined++;
1377 }
1378
1379 if (index > chunkstart) {
1380 int n_valid = invalidstart - chunkstart;
1381 int n_invalid = index - invalidstart;
1382
1383 qemu_put_be32(f, chunkstart);
1384 qemu_put_be16(f, n_valid);
1385 qemu_put_be16(f, n_invalid);
1386 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1387 HASH_PTE_SIZE_64 * n_valid);
1388 sent += index - chunkstart;
1389
1390 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1391 break;
1392 }
1393 }
1394
1395 if (examined >= htabslots) {
1396 break;
1397 }
1398
1399 if (index >= htabslots) {
1400 assert(index == htabslots);
1401 index = 0;
1402 }
1403 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1404
1405 if (index >= htabslots) {
1406 assert(index == htabslots);
1407 index = 0;
1408 }
1409
1410 spapr->htab_save_index = index;
1411
1412 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1413 }
1414
1415 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1416 #define MAX_KVM_BUF_SIZE 2048
1417
1418 static int htab_save_iterate(QEMUFile *f, void *opaque)
1419 {
1420 sPAPRMachineState *spapr = opaque;
1421 int fd;
1422 int rc = 0;
1423
1424 /* Iteration header */
1425 qemu_put_be32(f, 0);
1426
1427 if (!spapr->htab) {
1428 assert(kvm_enabled());
1429
1430 fd = get_htab_fd(spapr);
1431 if (fd < 0) {
1432 return fd;
1433 }
1434
1435 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1436 if (rc < 0) {
1437 return rc;
1438 }
1439 } else if (spapr->htab_first_pass) {
1440 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1441 } else {
1442 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1443 }
1444
1445 /* End marker */
1446 qemu_put_be32(f, 0);
1447 qemu_put_be16(f, 0);
1448 qemu_put_be16(f, 0);
1449
1450 return rc;
1451 }
1452
1453 static int htab_save_complete(QEMUFile *f, void *opaque)
1454 {
1455 sPAPRMachineState *spapr = opaque;
1456 int fd;
1457
1458 /* Iteration header */
1459 qemu_put_be32(f, 0);
1460
1461 if (!spapr->htab) {
1462 int rc;
1463
1464 assert(kvm_enabled());
1465
1466 fd = get_htab_fd(spapr);
1467 if (fd < 0) {
1468 return fd;
1469 }
1470
1471 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1472 if (rc < 0) {
1473 return rc;
1474 }
1475 } else {
1476 if (spapr->htab_first_pass) {
1477 htab_save_first_pass(f, spapr, -1);
1478 }
1479 htab_save_later_pass(f, spapr, -1);
1480 }
1481
1482 /* End marker */
1483 qemu_put_be32(f, 0);
1484 qemu_put_be16(f, 0);
1485 qemu_put_be16(f, 0);
1486
1487 return 0;
1488 }
1489
1490 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1491 {
1492 sPAPRMachineState *spapr = opaque;
1493 uint32_t section_hdr;
1494 int fd = -1;
1495
1496 if (version_id < 1 || version_id > 1) {
1497 error_report("htab_load() bad version");
1498 return -EINVAL;
1499 }
1500
1501 section_hdr = qemu_get_be32(f);
1502
1503 if (section_hdr) {
1504 Error *local_err = NULL;
1505
1506 /* First section gives the htab size */
1507 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1508 if (local_err) {
1509 error_report_err(local_err);
1510 return -EINVAL;
1511 }
1512 return 0;
1513 }
1514
1515 if (!spapr->htab) {
1516 assert(kvm_enabled());
1517
1518 fd = kvmppc_get_htab_fd(true);
1519 if (fd < 0) {
1520 error_report("Unable to open fd to restore KVM hash table: %s",
1521 strerror(errno));
1522 }
1523 }
1524
1525 while (true) {
1526 uint32_t index;
1527 uint16_t n_valid, n_invalid;
1528
1529 index = qemu_get_be32(f);
1530 n_valid = qemu_get_be16(f);
1531 n_invalid = qemu_get_be16(f);
1532
1533 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1534 /* End of Stream */
1535 break;
1536 }
1537
1538 if ((index + n_valid + n_invalid) >
1539 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1540 /* Bad index in stream */
1541 error_report(
1542 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1543 index, n_valid, n_invalid, spapr->htab_shift);
1544 return -EINVAL;
1545 }
1546
1547 if (spapr->htab) {
1548 if (n_valid) {
1549 qemu_get_buffer(f, HPTE(spapr->htab, index),
1550 HASH_PTE_SIZE_64 * n_valid);
1551 }
1552 if (n_invalid) {
1553 memset(HPTE(spapr->htab, index + n_valid), 0,
1554 HASH_PTE_SIZE_64 * n_invalid);
1555 }
1556 } else {
1557 int rc;
1558
1559 assert(fd >= 0);
1560
1561 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1562 if (rc < 0) {
1563 return rc;
1564 }
1565 }
1566 }
1567
1568 if (!spapr->htab) {
1569 assert(fd >= 0);
1570 close(fd);
1571 }
1572
1573 return 0;
1574 }
1575
1576 static void htab_cleanup(void *opaque)
1577 {
1578 sPAPRMachineState *spapr = opaque;
1579
1580 close_htab_fd(spapr);
1581 }
1582
1583 static SaveVMHandlers savevm_htab_handlers = {
1584 .save_live_setup = htab_save_setup,
1585 .save_live_iterate = htab_save_iterate,
1586 .save_live_complete_precopy = htab_save_complete,
1587 .cleanup = htab_cleanup,
1588 .load_state = htab_load,
1589 };
1590
1591 static void spapr_boot_set(void *opaque, const char *boot_device,
1592 Error **errp)
1593 {
1594 MachineState *machine = MACHINE(qdev_get_machine());
1595 machine->boot_order = g_strdup(boot_device);
1596 }
1597
1598 /*
1599 * Reset routine for LMB DR devices.
1600 *
1601 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1602 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1603 * when it walks all its children devices. LMB devices reset occurs
1604 * as part of spapr_ppc_reset().
1605 */
1606 static void spapr_drc_reset(void *opaque)
1607 {
1608 sPAPRDRConnector *drc = opaque;
1609 DeviceState *d = DEVICE(drc);
1610
1611 if (d) {
1612 device_reset(d);
1613 }
1614 }
1615
1616 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1617 {
1618 MachineState *machine = MACHINE(spapr);
1619 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1620 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1621 int i;
1622
1623 for (i = 0; i < nr_lmbs; i++) {
1624 sPAPRDRConnector *drc;
1625 uint64_t addr;
1626
1627 addr = i * lmb_size + spapr->hotplug_memory.base;
1628 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1629 addr/lmb_size);
1630 qemu_register_reset(spapr_drc_reset, drc);
1631 }
1632 }
1633
1634 /*
1635 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1636 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1637 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1638 */
1639 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1640 {
1641 int i;
1642
1643 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1644 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1645 " is not aligned to %llu MiB",
1646 machine->ram_size,
1647 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1648 return;
1649 }
1650
1651 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1652 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1653 " is not aligned to %llu MiB",
1654 machine->ram_size,
1655 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1656 return;
1657 }
1658
1659 for (i = 0; i < nb_numa_nodes; i++) {
1660 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1661 error_setg(errp,
1662 "Node %d memory size 0x%" PRIx64
1663 " is not aligned to %llu MiB",
1664 i, numa_info[i].node_mem,
1665 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1666 return;
1667 }
1668 }
1669 }
1670
1671 /* pSeries LPAR / sPAPR hardware init */
1672 static void ppc_spapr_init(MachineState *machine)
1673 {
1674 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1675 MachineClass *mc = MACHINE_GET_CLASS(machine);
1676 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1677 const char *kernel_filename = machine->kernel_filename;
1678 const char *initrd_filename = machine->initrd_filename;
1679 PCIHostState *phb;
1680 int i;
1681 MemoryRegion *sysmem = get_system_memory();
1682 MemoryRegion *ram = g_new(MemoryRegion, 1);
1683 MemoryRegion *rma_region;
1684 void *rma = NULL;
1685 hwaddr rma_alloc_size;
1686 hwaddr node0_size = spapr_node0_size();
1687 long load_limit, fw_size;
1688 char *filename;
1689 int smt = kvmppc_smt_threads();
1690 int spapr_cores = smp_cpus / smp_threads;
1691 int spapr_max_cores = max_cpus / smp_threads;
1692
1693 if (mc->query_hotpluggable_cpus) {
1694 if (smp_cpus % smp_threads) {
1695 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1696 smp_cpus, smp_threads);
1697 exit(1);
1698 }
1699 if (max_cpus % smp_threads) {
1700 error_report("max_cpus (%u) must be multiple of threads (%u)",
1701 max_cpus, smp_threads);
1702 exit(1);
1703 }
1704 }
1705
1706 msi_nonbroken = true;
1707
1708 QLIST_INIT(&spapr->phbs);
1709
1710 cpu_ppc_hypercall = emulate_spapr_hypercall;
1711
1712 /* Allocate RMA if necessary */
1713 rma_alloc_size = kvmppc_alloc_rma(&rma);
1714
1715 if (rma_alloc_size == -1) {
1716 error_report("Unable to create RMA");
1717 exit(1);
1718 }
1719
1720 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1721 spapr->rma_size = rma_alloc_size;
1722 } else {
1723 spapr->rma_size = node0_size;
1724
1725 /* With KVM, we don't actually know whether KVM supports an
1726 * unbounded RMA (PR KVM) or is limited by the hash table size
1727 * (HV KVM using VRMA), so we always assume the latter
1728 *
1729 * In that case, we also limit the initial allocations for RTAS
1730 * etc... to 256M since we have no way to know what the VRMA size
1731 * is going to be as it depends on the size of the hash table
1732 * isn't determined yet.
1733 */
1734 if (kvm_enabled()) {
1735 spapr->vrma_adjust = 1;
1736 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1737 }
1738
1739 /* Actually we don't support unbounded RMA anymore since we
1740 * added proper emulation of HV mode. The max we can get is
1741 * 16G which also happens to be what we configure for PAPR
1742 * mode so make sure we don't do anything bigger than that
1743 */
1744 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
1745 }
1746
1747 if (spapr->rma_size > node0_size) {
1748 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1749 spapr->rma_size);
1750 exit(1);
1751 }
1752
1753 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1754 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1755
1756 /* Set up Interrupt Controller before we create the VCPUs */
1757 spapr->xics = xics_system_init(machine,
1758 DIV_ROUND_UP(max_cpus * smt, smp_threads),
1759 XICS_IRQS_SPAPR, &error_fatal);
1760
1761 if (smc->dr_lmb_enabled) {
1762 spapr_validate_node_memory(machine, &error_fatal);
1763 }
1764
1765 /* init CPUs */
1766 if (machine->cpu_model == NULL) {
1767 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
1768 }
1769
1770 ppc_cpu_parse_features(machine->cpu_model);
1771
1772 if (mc->query_hotpluggable_cpus) {
1773 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1774
1775 if (type == NULL) {
1776 error_report("Unable to find sPAPR CPU Core definition");
1777 exit(1);
1778 }
1779
1780 spapr->cores = g_new0(Object *, spapr_max_cores);
1781 for (i = 0; i < spapr_max_cores; i++) {
1782 int core_id = i * smp_threads;
1783 sPAPRDRConnector *drc =
1784 spapr_dr_connector_new(OBJECT(spapr),
1785 SPAPR_DR_CONNECTOR_TYPE_CPU,
1786 (core_id / smp_threads) * smt);
1787
1788 qemu_register_reset(spapr_drc_reset, drc);
1789
1790 if (i < spapr_cores) {
1791 Object *core = object_new(type);
1792 object_property_set_int(core, smp_threads, "nr-threads",
1793 &error_fatal);
1794 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
1795 &error_fatal);
1796 object_property_set_bool(core, true, "realized", &error_fatal);
1797 }
1798 }
1799 g_free(type);
1800 } else {
1801 for (i = 0; i < smp_cpus; i++) {
1802 PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model);
1803 if (cpu == NULL) {
1804 error_report("Unable to find PowerPC CPU definition");
1805 exit(1);
1806 }
1807 spapr_cpu_init(spapr, cpu, &error_fatal);
1808 }
1809 }
1810
1811 if (kvm_enabled()) {
1812 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1813 kvmppc_enable_logical_ci_hcalls();
1814 kvmppc_enable_set_mode_hcall();
1815
1816 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
1817 kvmppc_enable_clear_ref_mod_hcalls();
1818 }
1819
1820 /* allocate RAM */
1821 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
1822 machine->ram_size);
1823 memory_region_add_subregion(sysmem, 0, ram);
1824
1825 if (rma_alloc_size && rma) {
1826 rma_region = g_new(MemoryRegion, 1);
1827 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1828 rma_alloc_size, rma);
1829 vmstate_register_ram_global(rma_region);
1830 memory_region_add_subregion(sysmem, 0, rma_region);
1831 }
1832
1833 /* initialize hotplug memory address space */
1834 if (machine->ram_size < machine->maxram_size) {
1835 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1836 /*
1837 * Limit the number of hotpluggable memory slots to half the number
1838 * slots that KVM supports, leaving the other half for PCI and other
1839 * devices. However ensure that number of slots doesn't drop below 32.
1840 */
1841 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
1842 SPAPR_MAX_RAM_SLOTS;
1843
1844 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
1845 max_memslots = SPAPR_MAX_RAM_SLOTS;
1846 }
1847 if (machine->ram_slots > max_memslots) {
1848 error_report("Specified number of memory slots %"
1849 PRIu64" exceeds max supported %d",
1850 machine->ram_slots, max_memslots);
1851 exit(1);
1852 }
1853
1854 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1855 SPAPR_HOTPLUG_MEM_ALIGN);
1856 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1857 "hotplug-memory", hotplug_mem_size);
1858 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1859 &spapr->hotplug_memory.mr);
1860 }
1861
1862 if (smc->dr_lmb_enabled) {
1863 spapr_create_lmb_dr_connectors(spapr);
1864 }
1865
1866 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1867 if (!filename) {
1868 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1869 exit(1);
1870 }
1871 spapr->rtas_size = get_image_size(filename);
1872 if (spapr->rtas_size < 0) {
1873 error_report("Could not get size of LPAR rtas '%s'", filename);
1874 exit(1);
1875 }
1876 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1877 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
1878 error_report("Could not load LPAR rtas '%s'", filename);
1879 exit(1);
1880 }
1881 if (spapr->rtas_size > RTAS_MAX_SIZE) {
1882 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1883 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
1884 exit(1);
1885 }
1886 g_free(filename);
1887
1888 /* Set up EPOW events infrastructure */
1889 spapr_events_init(spapr);
1890
1891 /* Set up the RTC RTAS interfaces */
1892 spapr_rtc_create(spapr);
1893
1894 /* Set up VIO bus */
1895 spapr->vio_bus = spapr_vio_bus_init();
1896
1897 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1898 if (serial_hds[i]) {
1899 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1900 }
1901 }
1902
1903 /* We always have at least the nvram device on VIO */
1904 spapr_create_nvram(spapr);
1905
1906 /* Set up PCI */
1907 spapr_pci_rtas_init();
1908
1909 phb = spapr_create_phb(spapr, 0);
1910
1911 for (i = 0; i < nb_nics; i++) {
1912 NICInfo *nd = &nd_table[i];
1913
1914 if (!nd->model) {
1915 nd->model = g_strdup("ibmveth");
1916 }
1917
1918 if (strcmp(nd->model, "ibmveth") == 0) {
1919 spapr_vlan_create(spapr->vio_bus, nd);
1920 } else {
1921 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1922 }
1923 }
1924
1925 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1926 spapr_vscsi_create(spapr->vio_bus);
1927 }
1928
1929 /* Graphics */
1930 if (spapr_vga_init(phb->bus, &error_fatal)) {
1931 spapr->has_graphics = true;
1932 machine->usb |= defaults_enabled() && !machine->usb_disabled;
1933 }
1934
1935 if (machine->usb) {
1936 if (smc->use_ohci_by_default) {
1937 pci_create_simple(phb->bus, -1, "pci-ohci");
1938 } else {
1939 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1940 }
1941
1942 if (spapr->has_graphics) {
1943 USBBus *usb_bus = usb_bus_find(-1);
1944
1945 usb_create_simple(usb_bus, "usb-kbd");
1946 usb_create_simple(usb_bus, "usb-mouse");
1947 }
1948 }
1949
1950 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
1951 error_report(
1952 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
1953 MIN_RMA_SLOF);
1954 exit(1);
1955 }
1956
1957 if (kernel_filename) {
1958 uint64_t lowaddr = 0;
1959
1960 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
1961 NULL, NULL, &lowaddr, NULL, 1,
1962 PPC_ELF_MACHINE, 0, 0);
1963 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
1964 spapr->kernel_size = load_elf(kernel_filename,
1965 translate_kernel_address, NULL, NULL,
1966 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
1967 0, 0);
1968 spapr->kernel_le = spapr->kernel_size > 0;
1969 }
1970 if (spapr->kernel_size < 0) {
1971 error_report("error loading %s: %s", kernel_filename,
1972 load_elf_strerror(spapr->kernel_size));
1973 exit(1);
1974 }
1975
1976 /* load initrd */
1977 if (initrd_filename) {
1978 /* Try to locate the initrd in the gap between the kernel
1979 * and the firmware. Add a bit of space just in case
1980 */
1981 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
1982 + 0x1ffff) & ~0xffff;
1983 spapr->initrd_size = load_image_targphys(initrd_filename,
1984 spapr->initrd_base,
1985 load_limit
1986 - spapr->initrd_base);
1987 if (spapr->initrd_size < 0) {
1988 error_report("could not load initial ram disk '%s'",
1989 initrd_filename);
1990 exit(1);
1991 }
1992 }
1993 }
1994
1995 if (bios_name == NULL) {
1996 bios_name = FW_FILE_NAME;
1997 }
1998 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1999 if (!filename) {
2000 error_report("Could not find LPAR firmware '%s'", bios_name);
2001 exit(1);
2002 }
2003 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2004 if (fw_size <= 0) {
2005 error_report("Could not load LPAR firmware '%s'", filename);
2006 exit(1);
2007 }
2008 g_free(filename);
2009
2010 /* FIXME: Should register things through the MachineState's qdev
2011 * interface, this is a legacy from the sPAPREnvironment structure
2012 * which predated MachineState but had a similar function */
2013 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2014 register_savevm_live(NULL, "spapr/htab", -1, 1,
2015 &savevm_htab_handlers, spapr);
2016
2017 /* Prepare the device tree */
2018 spapr->fdt_skel = spapr_create_fdt_skel(spapr);
2019 assert(spapr->fdt_skel != NULL);
2020
2021 /* used by RTAS */
2022 QTAILQ_INIT(&spapr->ccs_list);
2023 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2024
2025 qemu_register_boot_set(spapr_boot_set, spapr);
2026 }
2027
2028 static int spapr_kvm_type(const char *vm_type)
2029 {
2030 if (!vm_type) {
2031 return 0;
2032 }
2033
2034 if (!strcmp(vm_type, "HV")) {
2035 return 1;
2036 }
2037
2038 if (!strcmp(vm_type, "PR")) {
2039 return 2;
2040 }
2041
2042 error_report("Unknown kvm-type specified '%s'", vm_type);
2043 exit(1);
2044 }
2045
2046 /*
2047 * Implementation of an interface to adjust firmware path
2048 * for the bootindex property handling.
2049 */
2050 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2051 DeviceState *dev)
2052 {
2053 #define CAST(type, obj, name) \
2054 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2055 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2056 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2057
2058 if (d) {
2059 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2060 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2061 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2062
2063 if (spapr) {
2064 /*
2065 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2066 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2067 * in the top 16 bits of the 64-bit LUN
2068 */
2069 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2070 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2071 (uint64_t)id << 48);
2072 } else if (virtio) {
2073 /*
2074 * We use SRP luns of the form 01000000 | (target << 8) | lun
2075 * in the top 32 bits of the 64-bit LUN
2076 * Note: the quote above is from SLOF and it is wrong,
2077 * the actual binding is:
2078 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2079 */
2080 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2081 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2082 (uint64_t)id << 32);
2083 } else if (usb) {
2084 /*
2085 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2086 * in the top 32 bits of the 64-bit LUN
2087 */
2088 unsigned usb_port = atoi(usb->port->path);
2089 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2090 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2091 (uint64_t)id << 32);
2092 }
2093 }
2094
2095 if (phb) {
2096 /* Replace "pci" with "pci@800000020000000" */
2097 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2098 }
2099
2100 return NULL;
2101 }
2102
2103 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2104 {
2105 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2106
2107 return g_strdup(spapr->kvm_type);
2108 }
2109
2110 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2111 {
2112 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2113
2114 g_free(spapr->kvm_type);
2115 spapr->kvm_type = g_strdup(value);
2116 }
2117
2118 static void spapr_machine_initfn(Object *obj)
2119 {
2120 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2121
2122 spapr->htab_fd = -1;
2123 object_property_add_str(obj, "kvm-type",
2124 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2125 object_property_set_description(obj, "kvm-type",
2126 "Specifies the KVM virtualization mode (HV, PR)",
2127 NULL);
2128 }
2129
2130 static void spapr_machine_finalizefn(Object *obj)
2131 {
2132 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2133
2134 g_free(spapr->kvm_type);
2135 }
2136
2137 static void ppc_cpu_do_nmi_on_cpu(CPUState *cs, void *arg)
2138 {
2139 cpu_synchronize_state(cs);
2140 ppc_cpu_do_system_reset(cs);
2141 }
2142
2143 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2144 {
2145 CPUState *cs;
2146
2147 CPU_FOREACH(cs) {
2148 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, NULL);
2149 }
2150 }
2151
2152 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2153 uint32_t node, Error **errp)
2154 {
2155 sPAPRDRConnector *drc;
2156 sPAPRDRConnectorClass *drck;
2157 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2158 int i, fdt_offset, fdt_size;
2159 void *fdt;
2160
2161 for (i = 0; i < nr_lmbs; i++) {
2162 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2163 addr/SPAPR_MEMORY_BLOCK_SIZE);
2164 g_assert(drc);
2165
2166 fdt = create_device_tree(&fdt_size);
2167 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2168 SPAPR_MEMORY_BLOCK_SIZE);
2169
2170 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2171 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2172 addr += SPAPR_MEMORY_BLOCK_SIZE;
2173 }
2174 /* send hotplug notification to the
2175 * guest only in case of hotplugged memory
2176 */
2177 if (dev->hotplugged) {
2178 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2179 }
2180 }
2181
2182 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2183 uint32_t node, Error **errp)
2184 {
2185 Error *local_err = NULL;
2186 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2187 PCDIMMDevice *dimm = PC_DIMM(dev);
2188 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2189 MemoryRegion *mr = ddc->get_memory_region(dimm);
2190 uint64_t align = memory_region_get_alignment(mr);
2191 uint64_t size = memory_region_size(mr);
2192 uint64_t addr;
2193
2194 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2195 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2196 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2197 goto out;
2198 }
2199
2200 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2201 if (local_err) {
2202 goto out;
2203 }
2204
2205 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2206 if (local_err) {
2207 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2208 goto out;
2209 }
2210
2211 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2212
2213 out:
2214 error_propagate(errp, local_err);
2215 }
2216
2217 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2218 sPAPRMachineState *spapr)
2219 {
2220 PowerPCCPU *cpu = POWERPC_CPU(cs);
2221 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2222 int id = ppc_get_vcpu_dt_id(cpu);
2223 void *fdt;
2224 int offset, fdt_size;
2225 char *nodename;
2226
2227 fdt = create_device_tree(&fdt_size);
2228 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2229 offset = fdt_add_subnode(fdt, 0, nodename);
2230
2231 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2232 g_free(nodename);
2233
2234 *fdt_offset = offset;
2235 return fdt;
2236 }
2237
2238 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2239 DeviceState *dev, Error **errp)
2240 {
2241 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2242
2243 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2244 int node;
2245
2246 if (!smc->dr_lmb_enabled) {
2247 error_setg(errp, "Memory hotplug not supported for this machine");
2248 return;
2249 }
2250 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2251 if (*errp) {
2252 return;
2253 }
2254 if (node < 0 || node >= MAX_NODES) {
2255 error_setg(errp, "Invaild node %d", node);
2256 return;
2257 }
2258
2259 /*
2260 * Currently PowerPC kernel doesn't allow hot-adding memory to
2261 * memory-less node, but instead will silently add the memory
2262 * to the first node that has some memory. This causes two
2263 * unexpected behaviours for the user.
2264 *
2265 * - Memory gets hotplugged to a different node than what the user
2266 * specified.
2267 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2268 * to memory-less node, a reboot will set things accordingly
2269 * and the previously hotplugged memory now ends in the right node.
2270 * This appears as if some memory moved from one node to another.
2271 *
2272 * So until kernel starts supporting memory hotplug to memory-less
2273 * nodes, just prevent such attempts upfront in QEMU.
2274 */
2275 if (nb_numa_nodes && !numa_info[node].node_mem) {
2276 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2277 node);
2278 return;
2279 }
2280
2281 spapr_memory_plug(hotplug_dev, dev, node, errp);
2282 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2283 spapr_core_plug(hotplug_dev, dev, errp);
2284 }
2285 }
2286
2287 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2288 DeviceState *dev, Error **errp)
2289 {
2290 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2291
2292 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2293 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2294 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2295 if (!mc->query_hotpluggable_cpus) {
2296 error_setg(errp, "CPU hot unplug not supported on this machine");
2297 return;
2298 }
2299 spapr_core_unplug(hotplug_dev, dev, errp);
2300 }
2301 }
2302
2303 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2304 DeviceState *dev, Error **errp)
2305 {
2306 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2307 spapr_core_pre_plug(hotplug_dev, dev, errp);
2308 }
2309 }
2310
2311 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
2312 DeviceState *dev)
2313 {
2314 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2315 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2316 return HOTPLUG_HANDLER(machine);
2317 }
2318 return NULL;
2319 }
2320
2321 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2322 {
2323 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2324 * socket means much for the paravirtualized PAPR platform) */
2325 return cpu_index / smp_threads / smp_cores;
2326 }
2327
2328 static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
2329 {
2330 int i;
2331 HotpluggableCPUList *head = NULL;
2332 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2333 int spapr_max_cores = max_cpus / smp_threads;
2334
2335 for (i = 0; i < spapr_max_cores; i++) {
2336 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
2337 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
2338 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
2339
2340 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
2341 cpu_item->vcpus_count = smp_threads;
2342 cpu_props->has_core_id = true;
2343 cpu_props->core_id = i * smp_threads;
2344 /* TODO: add 'has_node/node' here to describe
2345 to which node core belongs */
2346
2347 cpu_item->props = cpu_props;
2348 if (spapr->cores[i]) {
2349 cpu_item->has_qom_path = true;
2350 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
2351 }
2352 list_item->value = cpu_item;
2353 list_item->next = head;
2354 head = list_item;
2355 }
2356 return head;
2357 }
2358
2359 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
2360 uint64_t *buid, hwaddr *pio,
2361 hwaddr *mmio32, hwaddr *mmio64,
2362 unsigned n_dma, uint32_t *liobns, Error **errp)
2363 {
2364 /*
2365 * New-style PHB window placement.
2366 *
2367 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
2368 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
2369 * windows.
2370 *
2371 * Some guest kernels can't work with MMIO windows above 1<<46
2372 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
2373 *
2374 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
2375 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
2376 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
2377 * 1TiB 64-bit MMIO windows for each PHB.
2378 */
2379 const uint64_t base_buid = 0x800000020000000ULL;
2380 const int max_phbs =
2381 (SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / SPAPR_PCI_MEM64_WIN_SIZE - 1;
2382 int i;
2383
2384 /* Sanity check natural alignments */
2385 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2386 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2387 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
2388 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
2389 /* Sanity check bounds */
2390 QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_IO_WIN_SIZE) > SPAPR_PCI_MEM32_WIN_SIZE);
2391 QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_MEM32_WIN_SIZE) > SPAPR_PCI_MEM64_WIN_SIZE);
2392
2393 if (index >= max_phbs) {
2394 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
2395 max_phbs - 1);
2396 return;
2397 }
2398
2399 *buid = base_buid + index;
2400 for (i = 0; i < n_dma; ++i) {
2401 liobns[i] = SPAPR_PCI_LIOBN(index, i);
2402 }
2403
2404 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
2405 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
2406 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
2407 }
2408
2409 static void spapr_machine_class_init(ObjectClass *oc, void *data)
2410 {
2411 MachineClass *mc = MACHINE_CLASS(oc);
2412 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2413 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2414 NMIClass *nc = NMI_CLASS(oc);
2415 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2416
2417 mc->desc = "pSeries Logical Partition (PAPR compliant)";
2418
2419 /*
2420 * We set up the default / latest behaviour here. The class_init
2421 * functions for the specific versioned machine types can override
2422 * these details for backwards compatibility
2423 */
2424 mc->init = ppc_spapr_init;
2425 mc->reset = ppc_spapr_reset;
2426 mc->block_default_type = IF_SCSI;
2427 mc->max_cpus = 255;
2428 mc->no_parallel = 1;
2429 mc->default_boot_order = "";
2430 mc->default_ram_size = 512 * M_BYTE;
2431 mc->kvm_type = spapr_kvm_type;
2432 mc->has_dynamic_sysbus = true;
2433 mc->pci_allow_0_address = true;
2434 mc->get_hotplug_handler = spapr_get_hotplug_handler;
2435 hc->pre_plug = spapr_machine_device_pre_plug;
2436 hc->plug = spapr_machine_device_plug;
2437 hc->unplug = spapr_machine_device_unplug;
2438 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2439
2440 smc->dr_lmb_enabled = true;
2441 smc->tcg_default_cpu = "POWER8";
2442 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus;
2443 fwc->get_dev_path = spapr_get_fw_dev_path;
2444 nc->nmi_monitor_handler = spapr_nmi;
2445 smc->phb_placement = spapr_phb_placement;
2446 }
2447
2448 static const TypeInfo spapr_machine_info = {
2449 .name = TYPE_SPAPR_MACHINE,
2450 .parent = TYPE_MACHINE,
2451 .abstract = true,
2452 .instance_size = sizeof(sPAPRMachineState),
2453 .instance_init = spapr_machine_initfn,
2454 .instance_finalize = spapr_machine_finalizefn,
2455 .class_size = sizeof(sPAPRMachineClass),
2456 .class_init = spapr_machine_class_init,
2457 .interfaces = (InterfaceInfo[]) {
2458 { TYPE_FW_PATH_PROVIDER },
2459 { TYPE_NMI },
2460 { TYPE_HOTPLUG_HANDLER },
2461 { }
2462 },
2463 };
2464
2465 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
2466 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2467 void *data) \
2468 { \
2469 MachineClass *mc = MACHINE_CLASS(oc); \
2470 spapr_machine_##suffix##_class_options(mc); \
2471 if (latest) { \
2472 mc->alias = "pseries"; \
2473 mc->is_default = 1; \
2474 } \
2475 } \
2476 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2477 { \
2478 MachineState *machine = MACHINE(obj); \
2479 spapr_machine_##suffix##_instance_options(machine); \
2480 } \
2481 static const TypeInfo spapr_machine_##suffix##_info = { \
2482 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2483 .parent = TYPE_SPAPR_MACHINE, \
2484 .class_init = spapr_machine_##suffix##_class_init, \
2485 .instance_init = spapr_machine_##suffix##_instance_init, \
2486 }; \
2487 static void spapr_machine_register_##suffix(void) \
2488 { \
2489 type_register(&spapr_machine_##suffix##_info); \
2490 } \
2491 type_init(spapr_machine_register_##suffix)
2492
2493 /*
2494 * pseries-2.8
2495 */
2496 static void spapr_machine_2_8_instance_options(MachineState *machine)
2497 {
2498 }
2499
2500 static void spapr_machine_2_8_class_options(MachineClass *mc)
2501 {
2502 /* Defaults for the latest behaviour inherited from the base class */
2503 }
2504
2505 DEFINE_SPAPR_MACHINE(2_8, "2.8", true);
2506
2507 /*
2508 * pseries-2.7
2509 */
2510 #define SPAPR_COMPAT_2_7 \
2511 HW_COMPAT_2_7 \
2512 { \
2513 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
2514 .property = "mem_win_size", \
2515 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
2516 }, \
2517 { \
2518 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
2519 .property = "mem64_win_size", \
2520 .value = "0", \
2521 },
2522
2523 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
2524 uint64_t *buid, hwaddr *pio,
2525 hwaddr *mmio32, hwaddr *mmio64,
2526 unsigned n_dma, uint32_t *liobns, Error **errp)
2527 {
2528 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
2529 const uint64_t base_buid = 0x800000020000000ULL;
2530 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
2531 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
2532 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
2533 const uint32_t max_index = 255;
2534 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
2535
2536 uint64_t ram_top = MACHINE(spapr)->ram_size;
2537 hwaddr phb0_base, phb_base;
2538 int i;
2539
2540 /* Do we have hotpluggable memory? */
2541 if (MACHINE(spapr)->maxram_size > ram_top) {
2542 /* Can't just use maxram_size, because there may be an
2543 * alignment gap between normal and hotpluggable memory
2544 * regions */
2545 ram_top = spapr->hotplug_memory.base +
2546 memory_region_size(&spapr->hotplug_memory.mr);
2547 }
2548
2549 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
2550
2551 if (index > max_index) {
2552 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
2553 max_index);
2554 return;
2555 }
2556
2557 *buid = base_buid + index;
2558 for (i = 0; i < n_dma; ++i) {
2559 liobns[i] = SPAPR_PCI_LIOBN(index, i);
2560 }
2561
2562 phb_base = phb0_base + index * phb_spacing;
2563 *pio = phb_base + pio_offset;
2564 *mmio32 = phb_base + mmio_offset;
2565 /*
2566 * We don't set the 64-bit MMIO window, relying on the PHB's
2567 * fallback behaviour of automatically splitting a large "32-bit"
2568 * window into contiguous 32-bit and 64-bit windows
2569 */
2570 }
2571
2572 static void spapr_machine_2_7_instance_options(MachineState *machine)
2573 {
2574 spapr_machine_2_8_instance_options(machine);
2575 }
2576
2577 static void spapr_machine_2_7_class_options(MachineClass *mc)
2578 {
2579 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2580
2581 spapr_machine_2_8_class_options(mc);
2582 smc->tcg_default_cpu = "POWER7";
2583 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
2584 smc->phb_placement = phb_placement_2_7;
2585 }
2586
2587 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
2588
2589 /*
2590 * pseries-2.6
2591 */
2592 #define SPAPR_COMPAT_2_6 \
2593 HW_COMPAT_2_6 \
2594 { \
2595 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2596 .property = "ddw",\
2597 .value = stringify(off),\
2598 },
2599
2600 static void spapr_machine_2_6_instance_options(MachineState *machine)
2601 {
2602 spapr_machine_2_7_instance_options(machine);
2603 }
2604
2605 static void spapr_machine_2_6_class_options(MachineClass *mc)
2606 {
2607 spapr_machine_2_7_class_options(mc);
2608 mc->query_hotpluggable_cpus = NULL;
2609 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
2610 }
2611
2612 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
2613
2614 /*
2615 * pseries-2.5
2616 */
2617 #define SPAPR_COMPAT_2_5 \
2618 HW_COMPAT_2_5 \
2619 { \
2620 .driver = "spapr-vlan", \
2621 .property = "use-rx-buffer-pools", \
2622 .value = "off", \
2623 },
2624
2625 static void spapr_machine_2_5_instance_options(MachineState *machine)
2626 {
2627 spapr_machine_2_6_instance_options(machine);
2628 }
2629
2630 static void spapr_machine_2_5_class_options(MachineClass *mc)
2631 {
2632 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2633
2634 spapr_machine_2_6_class_options(mc);
2635 smc->use_ohci_by_default = true;
2636 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
2637 }
2638
2639 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
2640
2641 /*
2642 * pseries-2.4
2643 */
2644 #define SPAPR_COMPAT_2_4 \
2645 HW_COMPAT_2_4
2646
2647 static void spapr_machine_2_4_instance_options(MachineState *machine)
2648 {
2649 spapr_machine_2_5_instance_options(machine);
2650 }
2651
2652 static void spapr_machine_2_4_class_options(MachineClass *mc)
2653 {
2654 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2655
2656 spapr_machine_2_5_class_options(mc);
2657 smc->dr_lmb_enabled = false;
2658 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
2659 }
2660
2661 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
2662
2663 /*
2664 * pseries-2.3
2665 */
2666 #define SPAPR_COMPAT_2_3 \
2667 HW_COMPAT_2_3 \
2668 {\
2669 .driver = "spapr-pci-host-bridge",\
2670 .property = "dynamic-reconfiguration",\
2671 .value = "off",\
2672 },
2673
2674 static void spapr_machine_2_3_instance_options(MachineState *machine)
2675 {
2676 spapr_machine_2_4_instance_options(machine);
2677 savevm_skip_section_footers();
2678 global_state_set_optional();
2679 savevm_skip_configuration();
2680 }
2681
2682 static void spapr_machine_2_3_class_options(MachineClass *mc)
2683 {
2684 spapr_machine_2_4_class_options(mc);
2685 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
2686 }
2687 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
2688
2689 /*
2690 * pseries-2.2
2691 */
2692
2693 #define SPAPR_COMPAT_2_2 \
2694 HW_COMPAT_2_2 \
2695 {\
2696 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2697 .property = "mem_win_size",\
2698 .value = "0x20000000",\
2699 },
2700
2701 static void spapr_machine_2_2_instance_options(MachineState *machine)
2702 {
2703 spapr_machine_2_3_instance_options(machine);
2704 machine->suppress_vmdesc = true;
2705 }
2706
2707 static void spapr_machine_2_2_class_options(MachineClass *mc)
2708 {
2709 spapr_machine_2_3_class_options(mc);
2710 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
2711 }
2712 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
2713
2714 /*
2715 * pseries-2.1
2716 */
2717 #define SPAPR_COMPAT_2_1 \
2718 HW_COMPAT_2_1
2719
2720 static void spapr_machine_2_1_instance_options(MachineState *machine)
2721 {
2722 spapr_machine_2_2_instance_options(machine);
2723 }
2724
2725 static void spapr_machine_2_1_class_options(MachineClass *mc)
2726 {
2727 spapr_machine_2_2_class_options(mc);
2728 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
2729 }
2730 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
2731
2732 static void spapr_machine_register_types(void)
2733 {
2734 type_register_static(&spapr_machine_info);
2735 }
2736
2737 type_init(spapr_machine_register_types)
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