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target/ppc: Manage external HPT via virtual hypervisor
[mirror_qemu.git] / hw / ppc / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/hw_accel.h"
40 #include "kvm_ppc.h"
41 #include "migration/migration.h"
42 #include "mmu-hash64.h"
43 #include "qom/cpu.h"
44
45 #include "hw/boards.h"
46 #include "hw/ppc/ppc.h"
47 #include "hw/loader.h"
48
49 #include "hw/ppc/fdt.h"
50 #include "hw/ppc/spapr.h"
51 #include "hw/ppc/spapr_vio.h"
52 #include "hw/pci-host/spapr.h"
53 #include "hw/ppc/xics.h"
54 #include "hw/pci/msi.h"
55
56 #include "hw/pci/pci.h"
57 #include "hw/scsi/scsi.h"
58 #include "hw/virtio/virtio-scsi.h"
59
60 #include "exec/address-spaces.h"
61 #include "hw/usb.h"
62 #include "qemu/config-file.h"
63 #include "qemu/error-report.h"
64 #include "trace.h"
65 #include "hw/nmi.h"
66
67 #include "hw/compat.h"
68 #include "qemu/cutils.h"
69 #include "hw/ppc/spapr_cpu_core.h"
70 #include "qmp-commands.h"
71
72 #include <libfdt.h>
73
74 /* SLOF memory layout:
75 *
76 * SLOF raw image loaded at 0, copies its romfs right below the flat
77 * device-tree, then position SLOF itself 31M below that
78 *
79 * So we set FW_OVERHEAD to 40MB which should account for all of that
80 * and more
81 *
82 * We load our kernel at 4M, leaving space for SLOF initial image
83 */
84 #define FDT_MAX_SIZE 0x100000
85 #define RTAS_MAX_SIZE 0x10000
86 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
87 #define FW_MAX_SIZE 0x400000
88 #define FW_FILE_NAME "slof.bin"
89 #define FW_OVERHEAD 0x2800000
90 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
91
92 #define MIN_RMA_SLOF 128UL
93
94 #define PHANDLE_XICP 0x00001111
95
96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
97
98 static XICSState *try_create_xics(const char *type, int nr_servers,
99 int nr_irqs, Error **errp)
100 {
101 Error *err = NULL;
102 DeviceState *dev;
103
104 dev = qdev_create(NULL, type);
105 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
106 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
107 object_property_set_bool(OBJECT(dev), true, "realized", &err);
108 if (err) {
109 error_propagate(errp, err);
110 object_unparent(OBJECT(dev));
111 return NULL;
112 }
113 return XICS_COMMON(dev);
114 }
115
116 static XICSState *xics_system_init(MachineState *machine,
117 int nr_servers, int nr_irqs, Error **errp)
118 {
119 XICSState *xics = NULL;
120
121 if (kvm_enabled()) {
122 Error *err = NULL;
123
124 if (machine_kernel_irqchip_allowed(machine)) {
125 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
126 &err);
127 }
128 if (machine_kernel_irqchip_required(machine) && !xics) {
129 error_reportf_err(err,
130 "kernel_irqchip requested but unavailable: ");
131 } else {
132 error_free(err);
133 }
134 }
135
136 if (!xics) {
137 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
138 }
139
140 return xics;
141 }
142
143 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
144 int smt_threads)
145 {
146 int i, ret = 0;
147 uint32_t servers_prop[smt_threads];
148 uint32_t gservers_prop[smt_threads * 2];
149 int index = ppc_get_vcpu_dt_id(cpu);
150
151 if (cpu->compat_pvr) {
152 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
153 if (ret < 0) {
154 return ret;
155 }
156 }
157
158 /* Build interrupt servers and gservers properties */
159 for (i = 0; i < smt_threads; i++) {
160 servers_prop[i] = cpu_to_be32(index + i);
161 /* Hack, direct the group queues back to cpu 0 */
162 gservers_prop[i*2] = cpu_to_be32(index + i);
163 gservers_prop[i*2 + 1] = 0;
164 }
165 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
166 servers_prop, sizeof(servers_prop));
167 if (ret < 0) {
168 return ret;
169 }
170 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
171 gservers_prop, sizeof(gservers_prop));
172
173 return ret;
174 }
175
176 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
177 {
178 int ret = 0;
179 PowerPCCPU *cpu = POWERPC_CPU(cs);
180 int index = ppc_get_vcpu_dt_id(cpu);
181 uint32_t associativity[] = {cpu_to_be32(0x5),
182 cpu_to_be32(0x0),
183 cpu_to_be32(0x0),
184 cpu_to_be32(0x0),
185 cpu_to_be32(cs->numa_node),
186 cpu_to_be32(index)};
187
188 /* Advertise NUMA via ibm,associativity */
189 if (nb_numa_nodes > 1) {
190 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
191 sizeof(associativity));
192 }
193
194 return ret;
195 }
196
197 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
198 {
199 int ret = 0, offset, cpus_offset;
200 CPUState *cs;
201 char cpu_model[32];
202 int smt = kvmppc_smt_threads();
203 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
204
205 CPU_FOREACH(cs) {
206 PowerPCCPU *cpu = POWERPC_CPU(cs);
207 DeviceClass *dc = DEVICE_GET_CLASS(cs);
208 int index = ppc_get_vcpu_dt_id(cpu);
209 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
210
211 if ((index % smt) != 0) {
212 continue;
213 }
214
215 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
216
217 cpus_offset = fdt_path_offset(fdt, "/cpus");
218 if (cpus_offset < 0) {
219 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
220 "cpus");
221 if (cpus_offset < 0) {
222 return cpus_offset;
223 }
224 }
225 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
226 if (offset < 0) {
227 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
228 if (offset < 0) {
229 return offset;
230 }
231 }
232
233 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
234 pft_size_prop, sizeof(pft_size_prop));
235 if (ret < 0) {
236 return ret;
237 }
238
239 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
240 if (ret < 0) {
241 return ret;
242 }
243
244 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
245 if (ret < 0) {
246 return ret;
247 }
248 }
249 return ret;
250 }
251
252 static hwaddr spapr_node0_size(void)
253 {
254 MachineState *machine = MACHINE(qdev_get_machine());
255
256 if (nb_numa_nodes) {
257 int i;
258 for (i = 0; i < nb_numa_nodes; ++i) {
259 if (numa_info[i].node_mem) {
260 return MIN(pow2floor(numa_info[i].node_mem),
261 machine->ram_size);
262 }
263 }
264 }
265 return machine->ram_size;
266 }
267
268 static void add_str(GString *s, const gchar *s1)
269 {
270 g_string_append_len(s, s1, strlen(s1) + 1);
271 }
272
273 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
274 hwaddr size)
275 {
276 uint32_t associativity[] = {
277 cpu_to_be32(0x4), /* length */
278 cpu_to_be32(0x0), cpu_to_be32(0x0),
279 cpu_to_be32(0x0), cpu_to_be32(nodeid)
280 };
281 char mem_name[32];
282 uint64_t mem_reg_property[2];
283 int off;
284
285 mem_reg_property[0] = cpu_to_be64(start);
286 mem_reg_property[1] = cpu_to_be64(size);
287
288 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
289 off = fdt_add_subnode(fdt, 0, mem_name);
290 _FDT(off);
291 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
292 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
293 sizeof(mem_reg_property))));
294 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
295 sizeof(associativity))));
296 return off;
297 }
298
299 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
300 {
301 MachineState *machine = MACHINE(spapr);
302 hwaddr mem_start, node_size;
303 int i, nb_nodes = nb_numa_nodes;
304 NodeInfo *nodes = numa_info;
305 NodeInfo ramnode;
306
307 /* No NUMA nodes, assume there is just one node with whole RAM */
308 if (!nb_numa_nodes) {
309 nb_nodes = 1;
310 ramnode.node_mem = machine->ram_size;
311 nodes = &ramnode;
312 }
313
314 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
315 if (!nodes[i].node_mem) {
316 continue;
317 }
318 if (mem_start >= machine->ram_size) {
319 node_size = 0;
320 } else {
321 node_size = nodes[i].node_mem;
322 if (node_size > machine->ram_size - mem_start) {
323 node_size = machine->ram_size - mem_start;
324 }
325 }
326 if (!mem_start) {
327 /* ppc_spapr_init() checks for rma_size <= node0_size already */
328 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
329 mem_start += spapr->rma_size;
330 node_size -= spapr->rma_size;
331 }
332 for ( ; node_size; ) {
333 hwaddr sizetmp = pow2floor(node_size);
334
335 /* mem_start != 0 here */
336 if (ctzl(mem_start) < ctzl(sizetmp)) {
337 sizetmp = 1ULL << ctzl(mem_start);
338 }
339
340 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
341 node_size -= sizetmp;
342 mem_start += sizetmp;
343 }
344 }
345
346 return 0;
347 }
348
349 /* Populate the "ibm,pa-features" property */
350 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
351 {
352 uint8_t pa_features_206[] = { 6, 0,
353 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
354 uint8_t pa_features_207[] = { 24, 0,
355 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
356 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
357 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
358 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
359 uint8_t *pa_features;
360 size_t pa_size;
361
362 switch (env->mmu_model) {
363 case POWERPC_MMU_2_06:
364 case POWERPC_MMU_2_06a:
365 pa_features = pa_features_206;
366 pa_size = sizeof(pa_features_206);
367 break;
368 case POWERPC_MMU_2_07:
369 case POWERPC_MMU_2_07a:
370 pa_features = pa_features_207;
371 pa_size = sizeof(pa_features_207);
372 break;
373 default:
374 return;
375 }
376
377 if (env->ci_large_pages) {
378 /*
379 * Note: we keep CI large pages off by default because a 64K capable
380 * guest provisioned with large pages might otherwise try to map a qemu
381 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
382 * even if that qemu runs on a 4k host.
383 * We dd this bit back here if we are confident this is not an issue
384 */
385 pa_features[3] |= 0x20;
386 }
387 if (kvmppc_has_cap_htm() && pa_size > 24) {
388 pa_features[24] |= 0x80; /* Transactional memory support */
389 }
390
391 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
392 }
393
394 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
395 sPAPRMachineState *spapr)
396 {
397 PowerPCCPU *cpu = POWERPC_CPU(cs);
398 CPUPPCState *env = &cpu->env;
399 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
400 int index = ppc_get_vcpu_dt_id(cpu);
401 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
402 0xffffffff, 0xffffffff};
403 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
404 : SPAPR_TIMEBASE_FREQ;
405 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
406 uint32_t page_sizes_prop[64];
407 size_t page_sizes_prop_size;
408 uint32_t vcpus_per_socket = smp_threads * smp_cores;
409 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
410 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
411 sPAPRDRConnector *drc;
412 sPAPRDRConnectorClass *drck;
413 int drc_index;
414
415 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
416 if (drc) {
417 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
418 drc_index = drck->get_index(drc);
419 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
420 }
421
422 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
423 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
424
425 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
426 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
427 env->dcache_line_size)));
428 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
429 env->dcache_line_size)));
430 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
431 env->icache_line_size)));
432 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
433 env->icache_line_size)));
434
435 if (pcc->l1_dcache_size) {
436 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
437 pcc->l1_dcache_size)));
438 } else {
439 error_report("Warning: Unknown L1 dcache size for cpu");
440 }
441 if (pcc->l1_icache_size) {
442 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
443 pcc->l1_icache_size)));
444 } else {
445 error_report("Warning: Unknown L1 icache size for cpu");
446 }
447
448 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
449 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
450 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
451 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
452 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
453 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
454
455 if (env->spr_cb[SPR_PURR].oea_read) {
456 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
457 }
458
459 if (env->mmu_model & POWERPC_MMU_1TSEG) {
460 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
461 segs, sizeof(segs))));
462 }
463
464 /* Advertise VMX/VSX (vector extensions) if available
465 * 0 / no property == no vector extensions
466 * 1 == VMX / Altivec available
467 * 2 == VSX available */
468 if (env->insns_flags & PPC_ALTIVEC) {
469 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
470
471 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
472 }
473
474 /* Advertise DFP (Decimal Floating Point) if available
475 * 0 / no property == no DFP
476 * 1 == DFP available */
477 if (env->insns_flags2 & PPC2_DFP) {
478 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
479 }
480
481 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
482 sizeof(page_sizes_prop));
483 if (page_sizes_prop_size) {
484 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
485 page_sizes_prop, page_sizes_prop_size)));
486 }
487
488 spapr_populate_pa_features(env, fdt, offset);
489
490 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
491 cs->cpu_index / vcpus_per_socket)));
492
493 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
494 pft_size_prop, sizeof(pft_size_prop))));
495
496 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
497
498 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
499 }
500
501 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
502 {
503 CPUState *cs;
504 int cpus_offset;
505 char *nodename;
506 int smt = kvmppc_smt_threads();
507
508 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
509 _FDT(cpus_offset);
510 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
511 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
512
513 /*
514 * We walk the CPUs in reverse order to ensure that CPU DT nodes
515 * created by fdt_add_subnode() end up in the right order in FDT
516 * for the guest kernel the enumerate the CPUs correctly.
517 */
518 CPU_FOREACH_REVERSE(cs) {
519 PowerPCCPU *cpu = POWERPC_CPU(cs);
520 int index = ppc_get_vcpu_dt_id(cpu);
521 DeviceClass *dc = DEVICE_GET_CLASS(cs);
522 int offset;
523
524 if ((index % smt) != 0) {
525 continue;
526 }
527
528 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
529 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
530 g_free(nodename);
531 _FDT(offset);
532 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
533 }
534
535 }
536
537 /*
538 * Adds ibm,dynamic-reconfiguration-memory node.
539 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
540 * of this device tree node.
541 */
542 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
543 {
544 MachineState *machine = MACHINE(spapr);
545 int ret, i, offset;
546 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
547 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
548 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
549 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
550 memory_region_size(&spapr->hotplug_memory.mr)) /
551 lmb_size;
552 uint32_t *int_buf, *cur_index, buf_len;
553 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
554
555 /*
556 * Don't create the node if there is no hotpluggable memory
557 */
558 if (machine->ram_size == machine->maxram_size) {
559 return 0;
560 }
561
562 /*
563 * Allocate enough buffer size to fit in ibm,dynamic-memory
564 * or ibm,associativity-lookup-arrays
565 */
566 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
567 * sizeof(uint32_t);
568 cur_index = int_buf = g_malloc0(buf_len);
569
570 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
571
572 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
573 sizeof(prop_lmb_size));
574 if (ret < 0) {
575 goto out;
576 }
577
578 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
579 if (ret < 0) {
580 goto out;
581 }
582
583 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
584 if (ret < 0) {
585 goto out;
586 }
587
588 /* ibm,dynamic-memory */
589 int_buf[0] = cpu_to_be32(nr_lmbs);
590 cur_index++;
591 for (i = 0; i < nr_lmbs; i++) {
592 uint64_t addr = i * lmb_size;
593 uint32_t *dynamic_memory = cur_index;
594
595 if (i >= hotplug_lmb_start) {
596 sPAPRDRConnector *drc;
597 sPAPRDRConnectorClass *drck;
598
599 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
600 g_assert(drc);
601 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
602
603 dynamic_memory[0] = cpu_to_be32(addr >> 32);
604 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
605 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
606 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
607 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
608 if (memory_region_present(get_system_memory(), addr)) {
609 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
610 } else {
611 dynamic_memory[5] = cpu_to_be32(0);
612 }
613 } else {
614 /*
615 * LMB information for RMA, boot time RAM and gap b/n RAM and
616 * hotplug memory region -- all these are marked as reserved
617 * and as having no valid DRC.
618 */
619 dynamic_memory[0] = cpu_to_be32(addr >> 32);
620 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
621 dynamic_memory[2] = cpu_to_be32(0);
622 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
623 dynamic_memory[4] = cpu_to_be32(-1);
624 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
625 SPAPR_LMB_FLAGS_DRC_INVALID);
626 }
627
628 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
629 }
630 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
631 if (ret < 0) {
632 goto out;
633 }
634
635 /* ibm,associativity-lookup-arrays */
636 cur_index = int_buf;
637 int_buf[0] = cpu_to_be32(nr_nodes);
638 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
639 cur_index += 2;
640 for (i = 0; i < nr_nodes; i++) {
641 uint32_t associativity[] = {
642 cpu_to_be32(0x0),
643 cpu_to_be32(0x0),
644 cpu_to_be32(0x0),
645 cpu_to_be32(i)
646 };
647 memcpy(cur_index, associativity, sizeof(associativity));
648 cur_index += 4;
649 }
650 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
651 (cur_index - int_buf) * sizeof(uint32_t));
652 out:
653 g_free(int_buf);
654 return ret;
655 }
656
657 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
658 sPAPROptionVector *ov5_updates)
659 {
660 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
661 int ret = 0, offset;
662
663 /* Generate ibm,dynamic-reconfiguration-memory node if required */
664 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
665 g_assert(smc->dr_lmb_enabled);
666 ret = spapr_populate_drconf_memory(spapr, fdt);
667 if (ret) {
668 goto out;
669 }
670 }
671
672 offset = fdt_path_offset(fdt, "/chosen");
673 if (offset < 0) {
674 offset = fdt_add_subnode(fdt, 0, "chosen");
675 if (offset < 0) {
676 return offset;
677 }
678 }
679 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
680 "ibm,architecture-vec-5");
681
682 out:
683 return ret;
684 }
685
686 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
687 target_ulong addr, target_ulong size,
688 sPAPROptionVector *ov5_updates)
689 {
690 void *fdt, *fdt_skel;
691 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
692
693 size -= sizeof(hdr);
694
695 /* Create sceleton */
696 fdt_skel = g_malloc0(size);
697 _FDT((fdt_create(fdt_skel, size)));
698 _FDT((fdt_begin_node(fdt_skel, "")));
699 _FDT((fdt_end_node(fdt_skel)));
700 _FDT((fdt_finish(fdt_skel)));
701 fdt = g_malloc0(size);
702 _FDT((fdt_open_into(fdt_skel, fdt, size)));
703 g_free(fdt_skel);
704
705 /* Fixup cpu nodes */
706 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
707
708 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
709 return -1;
710 }
711
712 /* Pack resulting tree */
713 _FDT((fdt_pack(fdt)));
714
715 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
716 trace_spapr_cas_failed(size);
717 return -1;
718 }
719
720 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
721 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
722 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
723 g_free(fdt);
724
725 return 0;
726 }
727
728 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
729 {
730 int rtas;
731 GString *hypertas = g_string_sized_new(256);
732 GString *qemu_hypertas = g_string_sized_new(256);
733 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
734 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
735 memory_region_size(&spapr->hotplug_memory.mr);
736 uint32_t lrdr_capacity[] = {
737 cpu_to_be32(max_hotplug_addr >> 32),
738 cpu_to_be32(max_hotplug_addr & 0xffffffff),
739 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
740 cpu_to_be32(max_cpus / smp_threads),
741 };
742
743 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
744
745 /* hypertas */
746 add_str(hypertas, "hcall-pft");
747 add_str(hypertas, "hcall-term");
748 add_str(hypertas, "hcall-dabr");
749 add_str(hypertas, "hcall-interrupt");
750 add_str(hypertas, "hcall-tce");
751 add_str(hypertas, "hcall-vio");
752 add_str(hypertas, "hcall-splpar");
753 add_str(hypertas, "hcall-bulk");
754 add_str(hypertas, "hcall-set-mode");
755 add_str(hypertas, "hcall-sprg0");
756 add_str(hypertas, "hcall-copy");
757 add_str(hypertas, "hcall-debug");
758 add_str(qemu_hypertas, "hcall-memop1");
759
760 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
761 add_str(hypertas, "hcall-multi-tce");
762 }
763 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
764 hypertas->str, hypertas->len));
765 g_string_free(hypertas, TRUE);
766 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
767 qemu_hypertas->str, qemu_hypertas->len));
768 g_string_free(qemu_hypertas, TRUE);
769
770 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
771 refpoints, sizeof(refpoints)));
772
773 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
774 RTAS_ERROR_LOG_MAX));
775 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
776 RTAS_EVENT_SCAN_RATE));
777
778 if (msi_nonbroken) {
779 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
780 }
781
782 /*
783 * According to PAPR, rtas ibm,os-term does not guarantee a return
784 * back to the guest cpu.
785 *
786 * While an additional ibm,extended-os-term property indicates
787 * that rtas call return will always occur. Set this property.
788 */
789 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
790
791 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
792 lrdr_capacity, sizeof(lrdr_capacity)));
793
794 spapr_dt_rtas_tokens(fdt, rtas);
795 }
796
797 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
798 {
799 MachineState *machine = MACHINE(spapr);
800 int chosen;
801 const char *boot_device = machine->boot_order;
802 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
803 size_t cb = 0;
804 char *bootlist = get_boot_devices_list(&cb, true);
805
806 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
807
808 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
809 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
810 spapr->initrd_base));
811 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
812 spapr->initrd_base + spapr->initrd_size));
813
814 if (spapr->kernel_size) {
815 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
816 cpu_to_be64(spapr->kernel_size) };
817
818 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
819 &kprop, sizeof(kprop)));
820 if (spapr->kernel_le) {
821 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
822 }
823 }
824 if (boot_menu) {
825 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
826 }
827 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
828 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
829 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
830
831 if (cb && bootlist) {
832 int i;
833
834 for (i = 0; i < cb; i++) {
835 if (bootlist[i] == '\n') {
836 bootlist[i] = ' ';
837 }
838 }
839 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
840 }
841
842 if (boot_device && strlen(boot_device)) {
843 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
844 }
845
846 if (!spapr->has_graphics && stdout_path) {
847 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
848 }
849
850 g_free(stdout_path);
851 g_free(bootlist);
852 }
853
854 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
855 {
856 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
857 * KVM to work under pHyp with some guest co-operation */
858 int hypervisor;
859 uint8_t hypercall[16];
860
861 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
862 /* indicate KVM hypercall interface */
863 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
864 if (kvmppc_has_cap_fixup_hcalls()) {
865 /*
866 * Older KVM versions with older guest kernels were broken
867 * with the magic page, don't allow the guest to map it.
868 */
869 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
870 sizeof(hypercall))) {
871 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
872 hypercall, sizeof(hypercall)));
873 }
874 }
875 }
876
877 static void *spapr_build_fdt(sPAPRMachineState *spapr,
878 hwaddr rtas_addr,
879 hwaddr rtas_size)
880 {
881 MachineState *machine = MACHINE(qdev_get_machine());
882 MachineClass *mc = MACHINE_GET_CLASS(machine);
883 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
884 int ret;
885 void *fdt;
886 sPAPRPHBState *phb;
887 char *buf;
888
889 fdt = g_malloc0(FDT_MAX_SIZE);
890 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
891
892 /* Root node */
893 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
894 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
895 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
896
897 /*
898 * Add info to guest to indentify which host is it being run on
899 * and what is the uuid of the guest
900 */
901 if (kvmppc_get_host_model(&buf)) {
902 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
903 g_free(buf);
904 }
905 if (kvmppc_get_host_serial(&buf)) {
906 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
907 g_free(buf);
908 }
909
910 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
911
912 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
913 if (qemu_uuid_set) {
914 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
915 }
916 g_free(buf);
917
918 if (qemu_get_vm_name()) {
919 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
920 qemu_get_vm_name()));
921 }
922
923 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
924 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
925
926 /* /interrupt controller */
927 spapr_dt_xics(spapr->xics, fdt, PHANDLE_XICP);
928
929 ret = spapr_populate_memory(spapr, fdt);
930 if (ret < 0) {
931 error_report("couldn't setup memory nodes in fdt");
932 exit(1);
933 }
934
935 /* /vdevice */
936 spapr_dt_vdevice(spapr->vio_bus, fdt);
937
938 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
939 ret = spapr_rng_populate_dt(fdt);
940 if (ret < 0) {
941 error_report("could not set up rng device in the fdt");
942 exit(1);
943 }
944 }
945
946 QLIST_FOREACH(phb, &spapr->phbs, list) {
947 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
948 if (ret < 0) {
949 error_report("couldn't setup PCI devices in fdt");
950 exit(1);
951 }
952 }
953
954 /* cpus */
955 spapr_populate_cpus_dt_node(fdt, spapr);
956
957 if (smc->dr_lmb_enabled) {
958 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
959 }
960
961 if (mc->has_hotpluggable_cpus) {
962 int offset = fdt_path_offset(fdt, "/cpus");
963 ret = spapr_drc_populate_dt(fdt, offset, NULL,
964 SPAPR_DR_CONNECTOR_TYPE_CPU);
965 if (ret < 0) {
966 error_report("Couldn't set up CPU DR device tree properties");
967 exit(1);
968 }
969 }
970
971 /* /event-sources */
972 spapr_dt_events(spapr, fdt);
973
974 /* /rtas */
975 spapr_dt_rtas(spapr, fdt);
976
977 /* /chosen */
978 spapr_dt_chosen(spapr, fdt);
979
980 /* /hypervisor */
981 if (kvm_enabled()) {
982 spapr_dt_hypervisor(spapr, fdt);
983 }
984
985 /* Build memory reserve map */
986 if (spapr->kernel_size) {
987 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
988 }
989 if (spapr->initrd_size) {
990 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
991 }
992
993 /* ibm,client-architecture-support updates */
994 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
995 if (ret < 0) {
996 error_report("couldn't setup CAS properties fdt");
997 exit(1);
998 }
999
1000 return fdt;
1001 }
1002
1003 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1004 {
1005 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1006 }
1007
1008 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1009 PowerPCCPU *cpu)
1010 {
1011 CPUPPCState *env = &cpu->env;
1012
1013 /* The TCG path should also be holding the BQL at this point */
1014 g_assert(qemu_mutex_iothread_locked());
1015
1016 if (msr_pr) {
1017 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1018 env->gpr[3] = H_PRIVILEGE;
1019 } else {
1020 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1021 }
1022 }
1023
1024 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1025 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1026 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1027 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1028 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1029
1030 /*
1031 * Get the fd to access the kernel htab, re-opening it if necessary
1032 */
1033 static int get_htab_fd(sPAPRMachineState *spapr)
1034 {
1035 if (spapr->htab_fd >= 0) {
1036 return spapr->htab_fd;
1037 }
1038
1039 spapr->htab_fd = kvmppc_get_htab_fd(false);
1040 if (spapr->htab_fd < 0) {
1041 error_report("Unable to open fd for reading hash table from KVM: %s",
1042 strerror(errno));
1043 }
1044
1045 return spapr->htab_fd;
1046 }
1047
1048 static void close_htab_fd(sPAPRMachineState *spapr)
1049 {
1050 if (spapr->htab_fd >= 0) {
1051 close(spapr->htab_fd);
1052 }
1053 spapr->htab_fd = -1;
1054 }
1055
1056 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1057 {
1058 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1059
1060 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1061 }
1062
1063 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1064 hwaddr ptex, int n)
1065 {
1066 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1067 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1068
1069 if (!spapr->htab) {
1070 /*
1071 * HTAB is controlled by KVM. Fetch into temporary buffer
1072 */
1073 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1074 kvmppc_read_hptes(hptes, ptex, n);
1075 return hptes;
1076 }
1077
1078 /*
1079 * HTAB is controlled by QEMU. Just point to the internally
1080 * accessible PTEG.
1081 */
1082 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1083 }
1084
1085 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1086 const ppc_hash_pte64_t *hptes,
1087 hwaddr ptex, int n)
1088 {
1089 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1090
1091 if (!spapr->htab) {
1092 g_free((void *)hptes);
1093 }
1094
1095 /* Nothing to do for qemu managed HPT */
1096 }
1097
1098 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1099 uint64_t pte0, uint64_t pte1)
1100 {
1101 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1102 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1103
1104 if (!spapr->htab) {
1105 kvmppc_write_hpte(ptex, pte0, pte1);
1106 } else {
1107 stq_p(spapr->htab + offset, pte0);
1108 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1109 }
1110 }
1111
1112 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1113 {
1114 int shift;
1115
1116 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1117 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1118 * that's much more than is needed for Linux guests */
1119 shift = ctz64(pow2ceil(ramsize)) - 7;
1120 shift = MAX(shift, 18); /* Minimum architected size */
1121 shift = MIN(shift, 46); /* Maximum architected size */
1122 return shift;
1123 }
1124
1125 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1126 Error **errp)
1127 {
1128 long rc;
1129
1130 /* Clean up any HPT info from a previous boot */
1131 g_free(spapr->htab);
1132 spapr->htab = NULL;
1133 spapr->htab_shift = 0;
1134 close_htab_fd(spapr);
1135
1136 rc = kvmppc_reset_htab(shift);
1137 if (rc < 0) {
1138 /* kernel-side HPT needed, but couldn't allocate one */
1139 error_setg_errno(errp, errno,
1140 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1141 shift);
1142 /* This is almost certainly fatal, but if the caller really
1143 * wants to carry on with shift == 0, it's welcome to try */
1144 } else if (rc > 0) {
1145 /* kernel-side HPT allocated */
1146 if (rc != shift) {
1147 error_setg(errp,
1148 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1149 shift, rc);
1150 }
1151
1152 spapr->htab_shift = shift;
1153 spapr->htab = NULL;
1154 } else {
1155 /* kernel-side HPT not needed, allocate in userspace instead */
1156 size_t size = 1ULL << shift;
1157 int i;
1158
1159 spapr->htab = qemu_memalign(size, size);
1160 if (!spapr->htab) {
1161 error_setg_errno(errp, errno,
1162 "Could not allocate HPT of order %d", shift);
1163 return;
1164 }
1165
1166 memset(spapr->htab, 0, size);
1167 spapr->htab_shift = shift;
1168
1169 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1170 DIRTY_HPTE(HPTE(spapr->htab, i));
1171 }
1172 }
1173 }
1174
1175 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1176 {
1177 bool matched = false;
1178
1179 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1180 matched = true;
1181 }
1182
1183 if (!matched) {
1184 error_report("Device %s is not supported by this machine yet.",
1185 qdev_fw_name(DEVICE(sbdev)));
1186 exit(1);
1187 }
1188 }
1189
1190 static void ppc_spapr_reset(void)
1191 {
1192 MachineState *machine = MACHINE(qdev_get_machine());
1193 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1194 PowerPCCPU *first_ppc_cpu;
1195 uint32_t rtas_limit;
1196 hwaddr rtas_addr, fdt_addr;
1197 void *fdt;
1198 int rc;
1199
1200 /* Check for unknown sysbus devices */
1201 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1202
1203 /* Allocate and/or reset the hash page table */
1204 spapr_reallocate_hpt(spapr,
1205 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1206 &error_fatal);
1207
1208 /* Update the RMA size if necessary */
1209 if (spapr->vrma_adjust) {
1210 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1211 spapr->htab_shift);
1212 }
1213
1214 qemu_devices_reset();
1215
1216 /*
1217 * We place the device tree and RTAS just below either the top of the RMA,
1218 * or just below 2GB, whichever is lowere, so that it can be
1219 * processed with 32-bit real mode code if necessary
1220 */
1221 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1222 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1223 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1224
1225 /* if this reset wasn't generated by CAS, we should reset our
1226 * negotiated options and start from scratch */
1227 if (!spapr->cas_reboot) {
1228 spapr_ovec_cleanup(spapr->ov5_cas);
1229 spapr->ov5_cas = spapr_ovec_new();
1230 }
1231
1232 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1233
1234 spapr_load_rtas(spapr, fdt, rtas_addr);
1235
1236 rc = fdt_pack(fdt);
1237
1238 /* Should only fail if we've built a corrupted tree */
1239 assert(rc == 0);
1240
1241 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1242 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1243 fdt_totalsize(fdt), FDT_MAX_SIZE);
1244 exit(1);
1245 }
1246
1247 /* Load the fdt */
1248 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1249 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1250 g_free(fdt);
1251
1252 /* Set up the entry state */
1253 first_ppc_cpu = POWERPC_CPU(first_cpu);
1254 first_ppc_cpu->env.gpr[3] = fdt_addr;
1255 first_ppc_cpu->env.gpr[5] = 0;
1256 first_cpu->halted = 0;
1257 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1258
1259 spapr->cas_reboot = false;
1260 }
1261
1262 static void spapr_create_nvram(sPAPRMachineState *spapr)
1263 {
1264 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1265 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1266
1267 if (dinfo) {
1268 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1269 &error_fatal);
1270 }
1271
1272 qdev_init_nofail(dev);
1273
1274 spapr->nvram = (struct sPAPRNVRAM *)dev;
1275 }
1276
1277 static void spapr_rtc_create(sPAPRMachineState *spapr)
1278 {
1279 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1280
1281 qdev_init_nofail(dev);
1282 spapr->rtc = dev;
1283
1284 object_property_add_alias(qdev_get_machine(), "rtc-time",
1285 OBJECT(spapr->rtc), "date", NULL);
1286 }
1287
1288 /* Returns whether we want to use VGA or not */
1289 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1290 {
1291 switch (vga_interface_type) {
1292 case VGA_NONE:
1293 return false;
1294 case VGA_DEVICE:
1295 return true;
1296 case VGA_STD:
1297 case VGA_VIRTIO:
1298 return pci_vga_init(pci_bus) != NULL;
1299 default:
1300 error_setg(errp,
1301 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1302 return false;
1303 }
1304 }
1305
1306 static int spapr_post_load(void *opaque, int version_id)
1307 {
1308 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1309 int err = 0;
1310
1311 /* In earlier versions, there was no separate qdev for the PAPR
1312 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1313 * So when migrating from those versions, poke the incoming offset
1314 * value into the RTC device */
1315 if (version_id < 3) {
1316 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1317 }
1318
1319 return err;
1320 }
1321
1322 static bool version_before_3(void *opaque, int version_id)
1323 {
1324 return version_id < 3;
1325 }
1326
1327 static bool spapr_ov5_cas_needed(void *opaque)
1328 {
1329 sPAPRMachineState *spapr = opaque;
1330 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1331 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1332 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1333 bool cas_needed;
1334
1335 /* Prior to the introduction of sPAPROptionVector, we had two option
1336 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1337 * Both of these options encode machine topology into the device-tree
1338 * in such a way that the now-booted OS should still be able to interact
1339 * appropriately with QEMU regardless of what options were actually
1340 * negotiatied on the source side.
1341 *
1342 * As such, we can avoid migrating the CAS-negotiated options if these
1343 * are the only options available on the current machine/platform.
1344 * Since these are the only options available for pseries-2.7 and
1345 * earlier, this allows us to maintain old->new/new->old migration
1346 * compatibility.
1347 *
1348 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1349 * via default pseries-2.8 machines and explicit command-line parameters.
1350 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1351 * of the actual CAS-negotiated values to continue working properly. For
1352 * example, availability of memory unplug depends on knowing whether
1353 * OV5_HP_EVT was negotiated via CAS.
1354 *
1355 * Thus, for any cases where the set of available CAS-negotiatable
1356 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1357 * include the CAS-negotiated options in the migration stream.
1358 */
1359 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1360 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1361
1362 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1363 * the mask itself since in the future it's possible "legacy" bits may be
1364 * removed via machine options, which could generate a false positive
1365 * that breaks migration.
1366 */
1367 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1368 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1369
1370 spapr_ovec_cleanup(ov5_mask);
1371 spapr_ovec_cleanup(ov5_legacy);
1372 spapr_ovec_cleanup(ov5_removed);
1373
1374 return cas_needed;
1375 }
1376
1377 static const VMStateDescription vmstate_spapr_ov5_cas = {
1378 .name = "spapr_option_vector_ov5_cas",
1379 .version_id = 1,
1380 .minimum_version_id = 1,
1381 .needed = spapr_ov5_cas_needed,
1382 .fields = (VMStateField[]) {
1383 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1384 vmstate_spapr_ovec, sPAPROptionVector),
1385 VMSTATE_END_OF_LIST()
1386 },
1387 };
1388
1389 static const VMStateDescription vmstate_spapr = {
1390 .name = "spapr",
1391 .version_id = 3,
1392 .minimum_version_id = 1,
1393 .post_load = spapr_post_load,
1394 .fields = (VMStateField[]) {
1395 /* used to be @next_irq */
1396 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1397
1398 /* RTC offset */
1399 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1400
1401 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1402 VMSTATE_END_OF_LIST()
1403 },
1404 .subsections = (const VMStateDescription*[]) {
1405 &vmstate_spapr_ov5_cas,
1406 NULL
1407 }
1408 };
1409
1410 static int htab_save_setup(QEMUFile *f, void *opaque)
1411 {
1412 sPAPRMachineState *spapr = opaque;
1413
1414 /* "Iteration" header */
1415 qemu_put_be32(f, spapr->htab_shift);
1416
1417 if (spapr->htab) {
1418 spapr->htab_save_index = 0;
1419 spapr->htab_first_pass = true;
1420 } else {
1421 assert(kvm_enabled());
1422 }
1423
1424
1425 return 0;
1426 }
1427
1428 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1429 int64_t max_ns)
1430 {
1431 bool has_timeout = max_ns != -1;
1432 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1433 int index = spapr->htab_save_index;
1434 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1435
1436 assert(spapr->htab_first_pass);
1437
1438 do {
1439 int chunkstart;
1440
1441 /* Consume invalid HPTEs */
1442 while ((index < htabslots)
1443 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1444 index++;
1445 CLEAN_HPTE(HPTE(spapr->htab, index));
1446 }
1447
1448 /* Consume valid HPTEs */
1449 chunkstart = index;
1450 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1451 && HPTE_VALID(HPTE(spapr->htab, index))) {
1452 index++;
1453 CLEAN_HPTE(HPTE(spapr->htab, index));
1454 }
1455
1456 if (index > chunkstart) {
1457 int n_valid = index - chunkstart;
1458
1459 qemu_put_be32(f, chunkstart);
1460 qemu_put_be16(f, n_valid);
1461 qemu_put_be16(f, 0);
1462 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1463 HASH_PTE_SIZE_64 * n_valid);
1464
1465 if (has_timeout &&
1466 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1467 break;
1468 }
1469 }
1470 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1471
1472 if (index >= htabslots) {
1473 assert(index == htabslots);
1474 index = 0;
1475 spapr->htab_first_pass = false;
1476 }
1477 spapr->htab_save_index = index;
1478 }
1479
1480 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1481 int64_t max_ns)
1482 {
1483 bool final = max_ns < 0;
1484 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1485 int examined = 0, sent = 0;
1486 int index = spapr->htab_save_index;
1487 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1488
1489 assert(!spapr->htab_first_pass);
1490
1491 do {
1492 int chunkstart, invalidstart;
1493
1494 /* Consume non-dirty HPTEs */
1495 while ((index < htabslots)
1496 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1497 index++;
1498 examined++;
1499 }
1500
1501 chunkstart = index;
1502 /* Consume valid dirty HPTEs */
1503 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1504 && HPTE_DIRTY(HPTE(spapr->htab, index))
1505 && HPTE_VALID(HPTE(spapr->htab, index))) {
1506 CLEAN_HPTE(HPTE(spapr->htab, index));
1507 index++;
1508 examined++;
1509 }
1510
1511 invalidstart = index;
1512 /* Consume invalid dirty HPTEs */
1513 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1514 && HPTE_DIRTY(HPTE(spapr->htab, index))
1515 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1516 CLEAN_HPTE(HPTE(spapr->htab, index));
1517 index++;
1518 examined++;
1519 }
1520
1521 if (index > chunkstart) {
1522 int n_valid = invalidstart - chunkstart;
1523 int n_invalid = index - invalidstart;
1524
1525 qemu_put_be32(f, chunkstart);
1526 qemu_put_be16(f, n_valid);
1527 qemu_put_be16(f, n_invalid);
1528 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1529 HASH_PTE_SIZE_64 * n_valid);
1530 sent += index - chunkstart;
1531
1532 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1533 break;
1534 }
1535 }
1536
1537 if (examined >= htabslots) {
1538 break;
1539 }
1540
1541 if (index >= htabslots) {
1542 assert(index == htabslots);
1543 index = 0;
1544 }
1545 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1546
1547 if (index >= htabslots) {
1548 assert(index == htabslots);
1549 index = 0;
1550 }
1551
1552 spapr->htab_save_index = index;
1553
1554 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1555 }
1556
1557 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1558 #define MAX_KVM_BUF_SIZE 2048
1559
1560 static int htab_save_iterate(QEMUFile *f, void *opaque)
1561 {
1562 sPAPRMachineState *spapr = opaque;
1563 int fd;
1564 int rc = 0;
1565
1566 /* Iteration header */
1567 qemu_put_be32(f, 0);
1568
1569 if (!spapr->htab) {
1570 assert(kvm_enabled());
1571
1572 fd = get_htab_fd(spapr);
1573 if (fd < 0) {
1574 return fd;
1575 }
1576
1577 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1578 if (rc < 0) {
1579 return rc;
1580 }
1581 } else if (spapr->htab_first_pass) {
1582 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1583 } else {
1584 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1585 }
1586
1587 /* End marker */
1588 qemu_put_be32(f, 0);
1589 qemu_put_be16(f, 0);
1590 qemu_put_be16(f, 0);
1591
1592 return rc;
1593 }
1594
1595 static int htab_save_complete(QEMUFile *f, void *opaque)
1596 {
1597 sPAPRMachineState *spapr = opaque;
1598 int fd;
1599
1600 /* Iteration header */
1601 qemu_put_be32(f, 0);
1602
1603 if (!spapr->htab) {
1604 int rc;
1605
1606 assert(kvm_enabled());
1607
1608 fd = get_htab_fd(spapr);
1609 if (fd < 0) {
1610 return fd;
1611 }
1612
1613 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1614 if (rc < 0) {
1615 return rc;
1616 }
1617 } else {
1618 if (spapr->htab_first_pass) {
1619 htab_save_first_pass(f, spapr, -1);
1620 }
1621 htab_save_later_pass(f, spapr, -1);
1622 }
1623
1624 /* End marker */
1625 qemu_put_be32(f, 0);
1626 qemu_put_be16(f, 0);
1627 qemu_put_be16(f, 0);
1628
1629 return 0;
1630 }
1631
1632 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1633 {
1634 sPAPRMachineState *spapr = opaque;
1635 uint32_t section_hdr;
1636 int fd = -1;
1637
1638 if (version_id < 1 || version_id > 1) {
1639 error_report("htab_load() bad version");
1640 return -EINVAL;
1641 }
1642
1643 section_hdr = qemu_get_be32(f);
1644
1645 if (section_hdr) {
1646 Error *local_err = NULL;
1647
1648 /* First section gives the htab size */
1649 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1650 if (local_err) {
1651 error_report_err(local_err);
1652 return -EINVAL;
1653 }
1654 return 0;
1655 }
1656
1657 if (!spapr->htab) {
1658 assert(kvm_enabled());
1659
1660 fd = kvmppc_get_htab_fd(true);
1661 if (fd < 0) {
1662 error_report("Unable to open fd to restore KVM hash table: %s",
1663 strerror(errno));
1664 }
1665 }
1666
1667 while (true) {
1668 uint32_t index;
1669 uint16_t n_valid, n_invalid;
1670
1671 index = qemu_get_be32(f);
1672 n_valid = qemu_get_be16(f);
1673 n_invalid = qemu_get_be16(f);
1674
1675 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1676 /* End of Stream */
1677 break;
1678 }
1679
1680 if ((index + n_valid + n_invalid) >
1681 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1682 /* Bad index in stream */
1683 error_report(
1684 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1685 index, n_valid, n_invalid, spapr->htab_shift);
1686 return -EINVAL;
1687 }
1688
1689 if (spapr->htab) {
1690 if (n_valid) {
1691 qemu_get_buffer(f, HPTE(spapr->htab, index),
1692 HASH_PTE_SIZE_64 * n_valid);
1693 }
1694 if (n_invalid) {
1695 memset(HPTE(spapr->htab, index + n_valid), 0,
1696 HASH_PTE_SIZE_64 * n_invalid);
1697 }
1698 } else {
1699 int rc;
1700
1701 assert(fd >= 0);
1702
1703 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1704 if (rc < 0) {
1705 return rc;
1706 }
1707 }
1708 }
1709
1710 if (!spapr->htab) {
1711 assert(fd >= 0);
1712 close(fd);
1713 }
1714
1715 return 0;
1716 }
1717
1718 static void htab_cleanup(void *opaque)
1719 {
1720 sPAPRMachineState *spapr = opaque;
1721
1722 close_htab_fd(spapr);
1723 }
1724
1725 static SaveVMHandlers savevm_htab_handlers = {
1726 .save_live_setup = htab_save_setup,
1727 .save_live_iterate = htab_save_iterate,
1728 .save_live_complete_precopy = htab_save_complete,
1729 .cleanup = htab_cleanup,
1730 .load_state = htab_load,
1731 };
1732
1733 static void spapr_boot_set(void *opaque, const char *boot_device,
1734 Error **errp)
1735 {
1736 MachineState *machine = MACHINE(qdev_get_machine());
1737 machine->boot_order = g_strdup(boot_device);
1738 }
1739
1740 /*
1741 * Reset routine for LMB DR devices.
1742 *
1743 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1744 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1745 * when it walks all its children devices. LMB devices reset occurs
1746 * as part of spapr_ppc_reset().
1747 */
1748 static void spapr_drc_reset(void *opaque)
1749 {
1750 sPAPRDRConnector *drc = opaque;
1751 DeviceState *d = DEVICE(drc);
1752
1753 if (d) {
1754 device_reset(d);
1755 }
1756 }
1757
1758 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1759 {
1760 MachineState *machine = MACHINE(spapr);
1761 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1762 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1763 int i;
1764
1765 for (i = 0; i < nr_lmbs; i++) {
1766 sPAPRDRConnector *drc;
1767 uint64_t addr;
1768
1769 addr = i * lmb_size + spapr->hotplug_memory.base;
1770 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1771 addr/lmb_size);
1772 qemu_register_reset(spapr_drc_reset, drc);
1773 }
1774 }
1775
1776 /*
1777 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1778 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1779 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1780 */
1781 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1782 {
1783 int i;
1784
1785 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1786 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1787 " is not aligned to %llu MiB",
1788 machine->ram_size,
1789 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1790 return;
1791 }
1792
1793 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1794 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1795 " is not aligned to %llu MiB",
1796 machine->ram_size,
1797 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1798 return;
1799 }
1800
1801 for (i = 0; i < nb_numa_nodes; i++) {
1802 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1803 error_setg(errp,
1804 "Node %d memory size 0x%" PRIx64
1805 " is not aligned to %llu MiB",
1806 i, numa_info[i].node_mem,
1807 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1808 return;
1809 }
1810 }
1811 }
1812
1813 /* find cpu slot in machine->possible_cpus by core_id */
1814 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1815 {
1816 int index = id / smp_threads;
1817
1818 if (index >= ms->possible_cpus->len) {
1819 return NULL;
1820 }
1821 if (idx) {
1822 *idx = index;
1823 }
1824 return &ms->possible_cpus->cpus[index];
1825 }
1826
1827 static void spapr_init_cpus(sPAPRMachineState *spapr)
1828 {
1829 MachineState *machine = MACHINE(spapr);
1830 MachineClass *mc = MACHINE_GET_CLASS(machine);
1831 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1832 int smt = kvmppc_smt_threads();
1833 const CPUArchIdList *possible_cpus;
1834 int boot_cores_nr = smp_cpus / smp_threads;
1835 int i;
1836
1837 if (!type) {
1838 error_report("Unable to find sPAPR CPU Core definition");
1839 exit(1);
1840 }
1841
1842 possible_cpus = mc->possible_cpu_arch_ids(machine);
1843 if (mc->has_hotpluggable_cpus) {
1844 if (smp_cpus % smp_threads) {
1845 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1846 smp_cpus, smp_threads);
1847 exit(1);
1848 }
1849 if (max_cpus % smp_threads) {
1850 error_report("max_cpus (%u) must be multiple of threads (%u)",
1851 max_cpus, smp_threads);
1852 exit(1);
1853 }
1854 } else {
1855 if (max_cpus != smp_cpus) {
1856 error_report("This machine version does not support CPU hotplug");
1857 exit(1);
1858 }
1859 boot_cores_nr = possible_cpus->len;
1860 }
1861
1862 for (i = 0; i < possible_cpus->len; i++) {
1863 int core_id = i * smp_threads;
1864
1865 if (mc->has_hotpluggable_cpus) {
1866 sPAPRDRConnector *drc =
1867 spapr_dr_connector_new(OBJECT(spapr),
1868 SPAPR_DR_CONNECTOR_TYPE_CPU,
1869 (core_id / smp_threads) * smt);
1870
1871 qemu_register_reset(spapr_drc_reset, drc);
1872 }
1873
1874 if (i < boot_cores_nr) {
1875 Object *core = object_new(type);
1876 int nr_threads = smp_threads;
1877
1878 /* Handle the partially filled core for older machine types */
1879 if ((i + 1) * smp_threads >= smp_cpus) {
1880 nr_threads = smp_cpus - i * smp_threads;
1881 }
1882
1883 object_property_set_int(core, nr_threads, "nr-threads",
1884 &error_fatal);
1885 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
1886 &error_fatal);
1887 object_property_set_bool(core, true, "realized", &error_fatal);
1888 }
1889 }
1890 g_free(type);
1891 }
1892
1893 /* pSeries LPAR / sPAPR hardware init */
1894 static void ppc_spapr_init(MachineState *machine)
1895 {
1896 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1897 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1898 const char *kernel_filename = machine->kernel_filename;
1899 const char *initrd_filename = machine->initrd_filename;
1900 PCIHostState *phb;
1901 int i;
1902 MemoryRegion *sysmem = get_system_memory();
1903 MemoryRegion *ram = g_new(MemoryRegion, 1);
1904 MemoryRegion *rma_region;
1905 void *rma = NULL;
1906 hwaddr rma_alloc_size;
1907 hwaddr node0_size = spapr_node0_size();
1908 long load_limit, fw_size;
1909 char *filename;
1910 int smt = kvmppc_smt_threads();
1911
1912 msi_nonbroken = true;
1913
1914 QLIST_INIT(&spapr->phbs);
1915
1916 /* Allocate RMA if necessary */
1917 rma_alloc_size = kvmppc_alloc_rma(&rma);
1918
1919 if (rma_alloc_size == -1) {
1920 error_report("Unable to create RMA");
1921 exit(1);
1922 }
1923
1924 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1925 spapr->rma_size = rma_alloc_size;
1926 } else {
1927 spapr->rma_size = node0_size;
1928
1929 /* With KVM, we don't actually know whether KVM supports an
1930 * unbounded RMA (PR KVM) or is limited by the hash table size
1931 * (HV KVM using VRMA), so we always assume the latter
1932 *
1933 * In that case, we also limit the initial allocations for RTAS
1934 * etc... to 256M since we have no way to know what the VRMA size
1935 * is going to be as it depends on the size of the hash table
1936 * isn't determined yet.
1937 */
1938 if (kvm_enabled()) {
1939 spapr->vrma_adjust = 1;
1940 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1941 }
1942
1943 /* Actually we don't support unbounded RMA anymore since we
1944 * added proper emulation of HV mode. The max we can get is
1945 * 16G which also happens to be what we configure for PAPR
1946 * mode so make sure we don't do anything bigger than that
1947 */
1948 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
1949 }
1950
1951 if (spapr->rma_size > node0_size) {
1952 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1953 spapr->rma_size);
1954 exit(1);
1955 }
1956
1957 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1958 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1959
1960 /* Set up Interrupt Controller before we create the VCPUs */
1961 spapr->xics = xics_system_init(machine,
1962 DIV_ROUND_UP(max_cpus * smt, smp_threads),
1963 XICS_IRQS_SPAPR, &error_fatal);
1964
1965 /* Set up containers for ibm,client-set-architecture negotiated options */
1966 spapr->ov5 = spapr_ovec_new();
1967 spapr->ov5_cas = spapr_ovec_new();
1968
1969 if (smc->dr_lmb_enabled) {
1970 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
1971 spapr_validate_node_memory(machine, &error_fatal);
1972 }
1973
1974 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
1975
1976 /* advertise support for dedicated HP event source to guests */
1977 if (spapr->use_hotplug_event_source) {
1978 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
1979 }
1980
1981 /* init CPUs */
1982 if (machine->cpu_model == NULL) {
1983 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
1984 }
1985
1986 ppc_cpu_parse_features(machine->cpu_model);
1987
1988 spapr_init_cpus(spapr);
1989
1990 if (kvm_enabled()) {
1991 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1992 kvmppc_enable_logical_ci_hcalls();
1993 kvmppc_enable_set_mode_hcall();
1994
1995 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
1996 kvmppc_enable_clear_ref_mod_hcalls();
1997 }
1998
1999 /* allocate RAM */
2000 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2001 machine->ram_size);
2002 memory_region_add_subregion(sysmem, 0, ram);
2003
2004 if (rma_alloc_size && rma) {
2005 rma_region = g_new(MemoryRegion, 1);
2006 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2007 rma_alloc_size, rma);
2008 vmstate_register_ram_global(rma_region);
2009 memory_region_add_subregion(sysmem, 0, rma_region);
2010 }
2011
2012 /* initialize hotplug memory address space */
2013 if (machine->ram_size < machine->maxram_size) {
2014 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2015 /*
2016 * Limit the number of hotpluggable memory slots to half the number
2017 * slots that KVM supports, leaving the other half for PCI and other
2018 * devices. However ensure that number of slots doesn't drop below 32.
2019 */
2020 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2021 SPAPR_MAX_RAM_SLOTS;
2022
2023 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2024 max_memslots = SPAPR_MAX_RAM_SLOTS;
2025 }
2026 if (machine->ram_slots > max_memslots) {
2027 error_report("Specified number of memory slots %"
2028 PRIu64" exceeds max supported %d",
2029 machine->ram_slots, max_memslots);
2030 exit(1);
2031 }
2032
2033 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2034 SPAPR_HOTPLUG_MEM_ALIGN);
2035 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2036 "hotplug-memory", hotplug_mem_size);
2037 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2038 &spapr->hotplug_memory.mr);
2039 }
2040
2041 if (smc->dr_lmb_enabled) {
2042 spapr_create_lmb_dr_connectors(spapr);
2043 }
2044
2045 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2046 if (!filename) {
2047 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2048 exit(1);
2049 }
2050 spapr->rtas_size = get_image_size(filename);
2051 if (spapr->rtas_size < 0) {
2052 error_report("Could not get size of LPAR rtas '%s'", filename);
2053 exit(1);
2054 }
2055 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2056 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2057 error_report("Could not load LPAR rtas '%s'", filename);
2058 exit(1);
2059 }
2060 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2061 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2062 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2063 exit(1);
2064 }
2065 g_free(filename);
2066
2067 /* Set up RTAS event infrastructure */
2068 spapr_events_init(spapr);
2069
2070 /* Set up the RTC RTAS interfaces */
2071 spapr_rtc_create(spapr);
2072
2073 /* Set up VIO bus */
2074 spapr->vio_bus = spapr_vio_bus_init();
2075
2076 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2077 if (serial_hds[i]) {
2078 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2079 }
2080 }
2081
2082 /* We always have at least the nvram device on VIO */
2083 spapr_create_nvram(spapr);
2084
2085 /* Set up PCI */
2086 spapr_pci_rtas_init();
2087
2088 phb = spapr_create_phb(spapr, 0);
2089
2090 for (i = 0; i < nb_nics; i++) {
2091 NICInfo *nd = &nd_table[i];
2092
2093 if (!nd->model) {
2094 nd->model = g_strdup("ibmveth");
2095 }
2096
2097 if (strcmp(nd->model, "ibmveth") == 0) {
2098 spapr_vlan_create(spapr->vio_bus, nd);
2099 } else {
2100 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2101 }
2102 }
2103
2104 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2105 spapr_vscsi_create(spapr->vio_bus);
2106 }
2107
2108 /* Graphics */
2109 if (spapr_vga_init(phb->bus, &error_fatal)) {
2110 spapr->has_graphics = true;
2111 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2112 }
2113
2114 if (machine->usb) {
2115 if (smc->use_ohci_by_default) {
2116 pci_create_simple(phb->bus, -1, "pci-ohci");
2117 } else {
2118 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2119 }
2120
2121 if (spapr->has_graphics) {
2122 USBBus *usb_bus = usb_bus_find(-1);
2123
2124 usb_create_simple(usb_bus, "usb-kbd");
2125 usb_create_simple(usb_bus, "usb-mouse");
2126 }
2127 }
2128
2129 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2130 error_report(
2131 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2132 MIN_RMA_SLOF);
2133 exit(1);
2134 }
2135
2136 if (kernel_filename) {
2137 uint64_t lowaddr = 0;
2138
2139 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2140 NULL, NULL, &lowaddr, NULL, 1,
2141 PPC_ELF_MACHINE, 0, 0);
2142 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2143 spapr->kernel_size = load_elf(kernel_filename,
2144 translate_kernel_address, NULL, NULL,
2145 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2146 0, 0);
2147 spapr->kernel_le = spapr->kernel_size > 0;
2148 }
2149 if (spapr->kernel_size < 0) {
2150 error_report("error loading %s: %s", kernel_filename,
2151 load_elf_strerror(spapr->kernel_size));
2152 exit(1);
2153 }
2154
2155 /* load initrd */
2156 if (initrd_filename) {
2157 /* Try to locate the initrd in the gap between the kernel
2158 * and the firmware. Add a bit of space just in case
2159 */
2160 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2161 + 0x1ffff) & ~0xffff;
2162 spapr->initrd_size = load_image_targphys(initrd_filename,
2163 spapr->initrd_base,
2164 load_limit
2165 - spapr->initrd_base);
2166 if (spapr->initrd_size < 0) {
2167 error_report("could not load initial ram disk '%s'",
2168 initrd_filename);
2169 exit(1);
2170 }
2171 }
2172 }
2173
2174 if (bios_name == NULL) {
2175 bios_name = FW_FILE_NAME;
2176 }
2177 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2178 if (!filename) {
2179 error_report("Could not find LPAR firmware '%s'", bios_name);
2180 exit(1);
2181 }
2182 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2183 if (fw_size <= 0) {
2184 error_report("Could not load LPAR firmware '%s'", filename);
2185 exit(1);
2186 }
2187 g_free(filename);
2188
2189 /* FIXME: Should register things through the MachineState's qdev
2190 * interface, this is a legacy from the sPAPREnvironment structure
2191 * which predated MachineState but had a similar function */
2192 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2193 register_savevm_live(NULL, "spapr/htab", -1, 1,
2194 &savevm_htab_handlers, spapr);
2195
2196 /* used by RTAS */
2197 QTAILQ_INIT(&spapr->ccs_list);
2198 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2199
2200 qemu_register_boot_set(spapr_boot_set, spapr);
2201
2202 /* to stop and start vmclock */
2203 if (kvm_enabled()) {
2204 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2205 &spapr->tb);
2206 }
2207 }
2208
2209 static int spapr_kvm_type(const char *vm_type)
2210 {
2211 if (!vm_type) {
2212 return 0;
2213 }
2214
2215 if (!strcmp(vm_type, "HV")) {
2216 return 1;
2217 }
2218
2219 if (!strcmp(vm_type, "PR")) {
2220 return 2;
2221 }
2222
2223 error_report("Unknown kvm-type specified '%s'", vm_type);
2224 exit(1);
2225 }
2226
2227 /*
2228 * Implementation of an interface to adjust firmware path
2229 * for the bootindex property handling.
2230 */
2231 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2232 DeviceState *dev)
2233 {
2234 #define CAST(type, obj, name) \
2235 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2236 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2237 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2238
2239 if (d) {
2240 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2241 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2242 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2243
2244 if (spapr) {
2245 /*
2246 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2247 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2248 * in the top 16 bits of the 64-bit LUN
2249 */
2250 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2251 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2252 (uint64_t)id << 48);
2253 } else if (virtio) {
2254 /*
2255 * We use SRP luns of the form 01000000 | (target << 8) | lun
2256 * in the top 32 bits of the 64-bit LUN
2257 * Note: the quote above is from SLOF and it is wrong,
2258 * the actual binding is:
2259 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2260 */
2261 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2262 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2263 (uint64_t)id << 32);
2264 } else if (usb) {
2265 /*
2266 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2267 * in the top 32 bits of the 64-bit LUN
2268 */
2269 unsigned usb_port = atoi(usb->port->path);
2270 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2271 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2272 (uint64_t)id << 32);
2273 }
2274 }
2275
2276 /*
2277 * SLOF probes the USB devices, and if it recognizes that the device is a
2278 * storage device, it changes its name to "storage" instead of "usb-host",
2279 * and additionally adds a child node for the SCSI LUN, so the correct
2280 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2281 */
2282 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2283 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2284 if (usb_host_dev_is_scsi_storage(usbdev)) {
2285 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2286 }
2287 }
2288
2289 if (phb) {
2290 /* Replace "pci" with "pci@800000020000000" */
2291 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2292 }
2293
2294 return NULL;
2295 }
2296
2297 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2298 {
2299 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2300
2301 return g_strdup(spapr->kvm_type);
2302 }
2303
2304 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2305 {
2306 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2307
2308 g_free(spapr->kvm_type);
2309 spapr->kvm_type = g_strdup(value);
2310 }
2311
2312 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2313 {
2314 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2315
2316 return spapr->use_hotplug_event_source;
2317 }
2318
2319 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2320 Error **errp)
2321 {
2322 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2323
2324 spapr->use_hotplug_event_source = value;
2325 }
2326
2327 static void spapr_machine_initfn(Object *obj)
2328 {
2329 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2330
2331 spapr->htab_fd = -1;
2332 spapr->use_hotplug_event_source = true;
2333 object_property_add_str(obj, "kvm-type",
2334 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2335 object_property_set_description(obj, "kvm-type",
2336 "Specifies the KVM virtualization mode (HV, PR)",
2337 NULL);
2338 object_property_add_bool(obj, "modern-hotplug-events",
2339 spapr_get_modern_hotplug_events,
2340 spapr_set_modern_hotplug_events,
2341 NULL);
2342 object_property_set_description(obj, "modern-hotplug-events",
2343 "Use dedicated hotplug event mechanism in"
2344 " place of standard EPOW events when possible"
2345 " (required for memory hot-unplug support)",
2346 NULL);
2347 }
2348
2349 static void spapr_machine_finalizefn(Object *obj)
2350 {
2351 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2352
2353 g_free(spapr->kvm_type);
2354 }
2355
2356 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2357 {
2358 cpu_synchronize_state(cs);
2359 ppc_cpu_do_system_reset(cs);
2360 }
2361
2362 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2363 {
2364 CPUState *cs;
2365
2366 CPU_FOREACH(cs) {
2367 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2368 }
2369 }
2370
2371 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2372 uint32_t node, bool dedicated_hp_event_source,
2373 Error **errp)
2374 {
2375 sPAPRDRConnector *drc;
2376 sPAPRDRConnectorClass *drck;
2377 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2378 int i, fdt_offset, fdt_size;
2379 void *fdt;
2380 uint64_t addr = addr_start;
2381
2382 for (i = 0; i < nr_lmbs; i++) {
2383 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2384 addr/SPAPR_MEMORY_BLOCK_SIZE);
2385 g_assert(drc);
2386
2387 fdt = create_device_tree(&fdt_size);
2388 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2389 SPAPR_MEMORY_BLOCK_SIZE);
2390
2391 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2392 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2393 addr += SPAPR_MEMORY_BLOCK_SIZE;
2394 if (!dev->hotplugged) {
2395 /* guests expect coldplugged LMBs to be pre-allocated */
2396 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
2397 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
2398 }
2399 }
2400 /* send hotplug notification to the
2401 * guest only in case of hotplugged memory
2402 */
2403 if (dev->hotplugged) {
2404 if (dedicated_hp_event_source) {
2405 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2406 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2407 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2408 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2409 nr_lmbs,
2410 drck->get_index(drc));
2411 } else {
2412 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
2413 nr_lmbs);
2414 }
2415 }
2416 }
2417
2418 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2419 uint32_t node, Error **errp)
2420 {
2421 Error *local_err = NULL;
2422 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2423 PCDIMMDevice *dimm = PC_DIMM(dev);
2424 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2425 MemoryRegion *mr = ddc->get_memory_region(dimm);
2426 uint64_t align = memory_region_get_alignment(mr);
2427 uint64_t size = memory_region_size(mr);
2428 uint64_t addr;
2429 char *mem_dev;
2430
2431 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2432 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2433 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2434 goto out;
2435 }
2436
2437 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
2438 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
2439 error_setg(&local_err, "Memory backend has bad page size. "
2440 "Use 'memory-backend-file' with correct mem-path.");
2441 goto out;
2442 }
2443
2444 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2445 if (local_err) {
2446 goto out;
2447 }
2448
2449 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2450 if (local_err) {
2451 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2452 goto out;
2453 }
2454
2455 spapr_add_lmbs(dev, addr, size, node,
2456 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
2457 &error_abort);
2458
2459 out:
2460 error_propagate(errp, local_err);
2461 }
2462
2463 typedef struct sPAPRDIMMState {
2464 uint32_t nr_lmbs;
2465 } sPAPRDIMMState;
2466
2467 static void spapr_lmb_release(DeviceState *dev, void *opaque)
2468 {
2469 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque;
2470 HotplugHandler *hotplug_ctrl;
2471
2472 if (--ds->nr_lmbs) {
2473 return;
2474 }
2475
2476 g_free(ds);
2477
2478 /*
2479 * Now that all the LMBs have been removed by the guest, call the
2480 * pc-dimm unplug handler to cleanup up the pc-dimm device.
2481 */
2482 hotplug_ctrl = qdev_get_hotplug_handler(dev);
2483 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2484 }
2485
2486 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2487 Error **errp)
2488 {
2489 sPAPRDRConnector *drc;
2490 sPAPRDRConnectorClass *drck;
2491 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
2492 int i;
2493 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState));
2494 uint64_t addr = addr_start;
2495
2496 ds->nr_lmbs = nr_lmbs;
2497 for (i = 0; i < nr_lmbs; i++) {
2498 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2499 addr / SPAPR_MEMORY_BLOCK_SIZE);
2500 g_assert(drc);
2501
2502 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2503 drck->detach(drc, dev, spapr_lmb_release, ds, errp);
2504 addr += SPAPR_MEMORY_BLOCK_SIZE;
2505 }
2506
2507 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2508 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2509 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2510 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2511 nr_lmbs,
2512 drck->get_index(drc));
2513 }
2514
2515 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2516 Error **errp)
2517 {
2518 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2519 PCDIMMDevice *dimm = PC_DIMM(dev);
2520 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2521 MemoryRegion *mr = ddc->get_memory_region(dimm);
2522
2523 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2524 object_unparent(OBJECT(dev));
2525 }
2526
2527 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
2528 DeviceState *dev, Error **errp)
2529 {
2530 Error *local_err = NULL;
2531 PCDIMMDevice *dimm = PC_DIMM(dev);
2532 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2533 MemoryRegion *mr = ddc->get_memory_region(dimm);
2534 uint64_t size = memory_region_size(mr);
2535 uint64_t addr;
2536
2537 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2538 if (local_err) {
2539 goto out;
2540 }
2541
2542 spapr_del_lmbs(dev, addr, size, &error_abort);
2543 out:
2544 error_propagate(errp, local_err);
2545 }
2546
2547 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2548 sPAPRMachineState *spapr)
2549 {
2550 PowerPCCPU *cpu = POWERPC_CPU(cs);
2551 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2552 int id = ppc_get_vcpu_dt_id(cpu);
2553 void *fdt;
2554 int offset, fdt_size;
2555 char *nodename;
2556
2557 fdt = create_device_tree(&fdt_size);
2558 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2559 offset = fdt_add_subnode(fdt, 0, nodename);
2560
2561 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2562 g_free(nodename);
2563
2564 *fdt_offset = offset;
2565 return fdt;
2566 }
2567
2568 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2569 Error **errp)
2570 {
2571 MachineState *ms = MACHINE(qdev_get_machine());
2572 CPUCore *cc = CPU_CORE(dev);
2573 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
2574
2575 core_slot->cpu = NULL;
2576 object_unparent(OBJECT(dev));
2577 }
2578
2579 static void spapr_core_release(DeviceState *dev, void *opaque)
2580 {
2581 HotplugHandler *hotplug_ctrl;
2582
2583 hotplug_ctrl = qdev_get_hotplug_handler(dev);
2584 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2585 }
2586
2587 static
2588 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
2589 Error **errp)
2590 {
2591 int index;
2592 sPAPRDRConnector *drc;
2593 sPAPRDRConnectorClass *drck;
2594 Error *local_err = NULL;
2595 CPUCore *cc = CPU_CORE(dev);
2596 int smt = kvmppc_smt_threads();
2597
2598 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
2599 error_setg(errp, "Unable to find CPU core with core-id: %d",
2600 cc->core_id);
2601 return;
2602 }
2603 if (index == 0) {
2604 error_setg(errp, "Boot CPU core may not be unplugged");
2605 return;
2606 }
2607
2608 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2609 g_assert(drc);
2610
2611 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2612 drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
2613 if (local_err) {
2614 error_propagate(errp, local_err);
2615 return;
2616 }
2617
2618 spapr_hotplug_req_remove_by_index(drc);
2619 }
2620
2621 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2622 Error **errp)
2623 {
2624 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
2625 MachineClass *mc = MACHINE_GET_CLASS(spapr);
2626 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
2627 CPUCore *cc = CPU_CORE(dev);
2628 CPUState *cs = CPU(core->threads);
2629 sPAPRDRConnector *drc;
2630 Error *local_err = NULL;
2631 void *fdt = NULL;
2632 int fdt_offset = 0;
2633 int smt = kvmppc_smt_threads();
2634 CPUArchId *core_slot;
2635 int index;
2636
2637 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2638 if (!core_slot) {
2639 error_setg(errp, "Unable to find CPU core with core-id: %d",
2640 cc->core_id);
2641 return;
2642 }
2643 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2644
2645 g_assert(drc || !mc->has_hotpluggable_cpus);
2646
2647 /*
2648 * Setup CPU DT entries only for hotplugged CPUs. For boot time or
2649 * coldplugged CPUs DT entries are setup in spapr_build_fdt().
2650 */
2651 if (dev->hotplugged) {
2652 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
2653 }
2654
2655 if (drc) {
2656 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2657 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
2658 if (local_err) {
2659 g_free(fdt);
2660 error_propagate(errp, local_err);
2661 return;
2662 }
2663 }
2664
2665 if (dev->hotplugged) {
2666 /*
2667 * Send hotplug notification interrupt to the guest only in case
2668 * of hotplugged CPUs.
2669 */
2670 spapr_hotplug_req_add_by_index(drc);
2671 } else {
2672 /*
2673 * Set the right DRC states for cold plugged CPU.
2674 */
2675 if (drc) {
2676 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2677 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
2678 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
2679 }
2680 }
2681 core_slot->cpu = OBJECT(dev);
2682 }
2683
2684 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2685 Error **errp)
2686 {
2687 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
2688 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
2689 Error *local_err = NULL;
2690 CPUCore *cc = CPU_CORE(dev);
2691 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
2692 const char *type = object_get_typename(OBJECT(dev));
2693 CPUArchId *core_slot;
2694 int index;
2695
2696 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
2697 error_setg(&local_err, "CPU hotplug not supported for this machine");
2698 goto out;
2699 }
2700
2701 if (strcmp(base_core_type, type)) {
2702 error_setg(&local_err, "CPU core type should be %s", base_core_type);
2703 goto out;
2704 }
2705
2706 if (cc->core_id % smp_threads) {
2707 error_setg(&local_err, "invalid core id %d", cc->core_id);
2708 goto out;
2709 }
2710
2711 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2712 if (!core_slot) {
2713 error_setg(&local_err, "core id %d out of range", cc->core_id);
2714 goto out;
2715 }
2716
2717 if (core_slot->cpu) {
2718 error_setg(&local_err, "core %d already populated", cc->core_id);
2719 goto out;
2720 }
2721
2722 out:
2723 g_free(base_core_type);
2724 error_propagate(errp, local_err);
2725 }
2726
2727 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2728 DeviceState *dev, Error **errp)
2729 {
2730 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2731
2732 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2733 int node;
2734
2735 if (!smc->dr_lmb_enabled) {
2736 error_setg(errp, "Memory hotplug not supported for this machine");
2737 return;
2738 }
2739 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2740 if (*errp) {
2741 return;
2742 }
2743 if (node < 0 || node >= MAX_NODES) {
2744 error_setg(errp, "Invaild node %d", node);
2745 return;
2746 }
2747
2748 /*
2749 * Currently PowerPC kernel doesn't allow hot-adding memory to
2750 * memory-less node, but instead will silently add the memory
2751 * to the first node that has some memory. This causes two
2752 * unexpected behaviours for the user.
2753 *
2754 * - Memory gets hotplugged to a different node than what the user
2755 * specified.
2756 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2757 * to memory-less node, a reboot will set things accordingly
2758 * and the previously hotplugged memory now ends in the right node.
2759 * This appears as if some memory moved from one node to another.
2760 *
2761 * So until kernel starts supporting memory hotplug to memory-less
2762 * nodes, just prevent such attempts upfront in QEMU.
2763 */
2764 if (nb_numa_nodes && !numa_info[node].node_mem) {
2765 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2766 node);
2767 return;
2768 }
2769
2770 spapr_memory_plug(hotplug_dev, dev, node, errp);
2771 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2772 spapr_core_plug(hotplug_dev, dev, errp);
2773 }
2774 }
2775
2776 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2777 DeviceState *dev, Error **errp)
2778 {
2779 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
2780 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2781
2782 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2783 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
2784 spapr_memory_unplug(hotplug_dev, dev, errp);
2785 } else {
2786 error_setg(errp, "Memory hot unplug not supported for this guest");
2787 }
2788 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2789 if (!mc->has_hotpluggable_cpus) {
2790 error_setg(errp, "CPU hot unplug not supported on this machine");
2791 return;
2792 }
2793 spapr_core_unplug(hotplug_dev, dev, errp);
2794 }
2795 }
2796
2797 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
2798 DeviceState *dev, Error **errp)
2799 {
2800 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
2801 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2802
2803 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2804 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
2805 spapr_memory_unplug_request(hotplug_dev, dev, errp);
2806 } else {
2807 /* NOTE: this means there is a window after guest reset, prior to
2808 * CAS negotiation, where unplug requests will fail due to the
2809 * capability not being detected yet. This is a bit different than
2810 * the case with PCI unplug, where the events will be queued and
2811 * eventually handled by the guest after boot
2812 */
2813 error_setg(errp, "Memory hot unplug not supported for this guest");
2814 }
2815 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2816 if (!mc->has_hotpluggable_cpus) {
2817 error_setg(errp, "CPU hot unplug not supported on this machine");
2818 return;
2819 }
2820 spapr_core_unplug_request(hotplug_dev, dev, errp);
2821 }
2822 }
2823
2824 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2825 DeviceState *dev, Error **errp)
2826 {
2827 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2828 spapr_core_pre_plug(hotplug_dev, dev, errp);
2829 }
2830 }
2831
2832 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
2833 DeviceState *dev)
2834 {
2835 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2836 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2837 return HOTPLUG_HANDLER(machine);
2838 }
2839 return NULL;
2840 }
2841
2842 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2843 {
2844 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2845 * socket means much for the paravirtualized PAPR platform) */
2846 return cpu_index / smp_threads / smp_cores;
2847 }
2848
2849 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
2850 {
2851 int i;
2852 int spapr_max_cores = max_cpus / smp_threads;
2853 MachineClass *mc = MACHINE_GET_CLASS(machine);
2854
2855 if (!mc->has_hotpluggable_cpus) {
2856 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
2857 }
2858 if (machine->possible_cpus) {
2859 assert(machine->possible_cpus->len == spapr_max_cores);
2860 return machine->possible_cpus;
2861 }
2862
2863 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2864 sizeof(CPUArchId) * spapr_max_cores);
2865 machine->possible_cpus->len = spapr_max_cores;
2866 for (i = 0; i < machine->possible_cpus->len; i++) {
2867 int core_id = i * smp_threads;
2868
2869 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
2870 machine->possible_cpus->cpus[i].arch_id = core_id;
2871 machine->possible_cpus->cpus[i].props.has_core_id = true;
2872 machine->possible_cpus->cpus[i].props.core_id = core_id;
2873 /* TODO: add 'has_node/node' here to describe
2874 to which node core belongs */
2875 }
2876 return machine->possible_cpus;
2877 }
2878
2879 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
2880 uint64_t *buid, hwaddr *pio,
2881 hwaddr *mmio32, hwaddr *mmio64,
2882 unsigned n_dma, uint32_t *liobns, Error **errp)
2883 {
2884 /*
2885 * New-style PHB window placement.
2886 *
2887 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
2888 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
2889 * windows.
2890 *
2891 * Some guest kernels can't work with MMIO windows above 1<<46
2892 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
2893 *
2894 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
2895 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
2896 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
2897 * 1TiB 64-bit MMIO windows for each PHB.
2898 */
2899 const uint64_t base_buid = 0x800000020000000ULL;
2900 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
2901 SPAPR_PCI_MEM64_WIN_SIZE - 1)
2902 int i;
2903
2904 /* Sanity check natural alignments */
2905 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2906 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2907 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
2908 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
2909 /* Sanity check bounds */
2910 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
2911 SPAPR_PCI_MEM32_WIN_SIZE);
2912 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
2913 SPAPR_PCI_MEM64_WIN_SIZE);
2914
2915 if (index >= SPAPR_MAX_PHBS) {
2916 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
2917 SPAPR_MAX_PHBS - 1);
2918 return;
2919 }
2920
2921 *buid = base_buid + index;
2922 for (i = 0; i < n_dma; ++i) {
2923 liobns[i] = SPAPR_PCI_LIOBN(index, i);
2924 }
2925
2926 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
2927 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
2928 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
2929 }
2930
2931 static void spapr_machine_class_init(ObjectClass *oc, void *data)
2932 {
2933 MachineClass *mc = MACHINE_CLASS(oc);
2934 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2935 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2936 NMIClass *nc = NMI_CLASS(oc);
2937 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2938 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
2939
2940 mc->desc = "pSeries Logical Partition (PAPR compliant)";
2941
2942 /*
2943 * We set up the default / latest behaviour here. The class_init
2944 * functions for the specific versioned machine types can override
2945 * these details for backwards compatibility
2946 */
2947 mc->init = ppc_spapr_init;
2948 mc->reset = ppc_spapr_reset;
2949 mc->block_default_type = IF_SCSI;
2950 mc->max_cpus = 1024;
2951 mc->no_parallel = 1;
2952 mc->default_boot_order = "";
2953 mc->default_ram_size = 512 * M_BYTE;
2954 mc->kvm_type = spapr_kvm_type;
2955 mc->has_dynamic_sysbus = true;
2956 mc->pci_allow_0_address = true;
2957 mc->get_hotplug_handler = spapr_get_hotplug_handler;
2958 hc->pre_plug = spapr_machine_device_pre_plug;
2959 hc->plug = spapr_machine_device_plug;
2960 hc->unplug = spapr_machine_device_unplug;
2961 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2962 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
2963 hc->unplug_request = spapr_machine_device_unplug_request;
2964
2965 smc->dr_lmb_enabled = true;
2966 smc->tcg_default_cpu = "POWER8";
2967 mc->has_hotpluggable_cpus = true;
2968 fwc->get_dev_path = spapr_get_fw_dev_path;
2969 nc->nmi_monitor_handler = spapr_nmi;
2970 smc->phb_placement = spapr_phb_placement;
2971 vhc->hypercall = emulate_spapr_hypercall;
2972 vhc->hpt_mask = spapr_hpt_mask;
2973 vhc->map_hptes = spapr_map_hptes;
2974 vhc->unmap_hptes = spapr_unmap_hptes;
2975 vhc->store_hpte = spapr_store_hpte;
2976 }
2977
2978 static const TypeInfo spapr_machine_info = {
2979 .name = TYPE_SPAPR_MACHINE,
2980 .parent = TYPE_MACHINE,
2981 .abstract = true,
2982 .instance_size = sizeof(sPAPRMachineState),
2983 .instance_init = spapr_machine_initfn,
2984 .instance_finalize = spapr_machine_finalizefn,
2985 .class_size = sizeof(sPAPRMachineClass),
2986 .class_init = spapr_machine_class_init,
2987 .interfaces = (InterfaceInfo[]) {
2988 { TYPE_FW_PATH_PROVIDER },
2989 { TYPE_NMI },
2990 { TYPE_HOTPLUG_HANDLER },
2991 { TYPE_PPC_VIRTUAL_HYPERVISOR },
2992 { }
2993 },
2994 };
2995
2996 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
2997 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2998 void *data) \
2999 { \
3000 MachineClass *mc = MACHINE_CLASS(oc); \
3001 spapr_machine_##suffix##_class_options(mc); \
3002 if (latest) { \
3003 mc->alias = "pseries"; \
3004 mc->is_default = 1; \
3005 } \
3006 } \
3007 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3008 { \
3009 MachineState *machine = MACHINE(obj); \
3010 spapr_machine_##suffix##_instance_options(machine); \
3011 } \
3012 static const TypeInfo spapr_machine_##suffix##_info = { \
3013 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3014 .parent = TYPE_SPAPR_MACHINE, \
3015 .class_init = spapr_machine_##suffix##_class_init, \
3016 .instance_init = spapr_machine_##suffix##_instance_init, \
3017 }; \
3018 static void spapr_machine_register_##suffix(void) \
3019 { \
3020 type_register(&spapr_machine_##suffix##_info); \
3021 } \
3022 type_init(spapr_machine_register_##suffix)
3023
3024 /*
3025 * pseries-2.9
3026 */
3027 static void spapr_machine_2_9_instance_options(MachineState *machine)
3028 {
3029 }
3030
3031 static void spapr_machine_2_9_class_options(MachineClass *mc)
3032 {
3033 /* Defaults for the latest behaviour inherited from the base class */
3034 }
3035
3036 DEFINE_SPAPR_MACHINE(2_9, "2.9", true);
3037
3038 /*
3039 * pseries-2.8
3040 */
3041 #define SPAPR_COMPAT_2_8 \
3042 HW_COMPAT_2_8
3043
3044 static void spapr_machine_2_8_instance_options(MachineState *machine)
3045 {
3046 spapr_machine_2_9_instance_options(machine);
3047 }
3048
3049 static void spapr_machine_2_8_class_options(MachineClass *mc)
3050 {
3051 spapr_machine_2_9_class_options(mc);
3052 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
3053 }
3054
3055 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
3056
3057 /*
3058 * pseries-2.7
3059 */
3060 #define SPAPR_COMPAT_2_7 \
3061 HW_COMPAT_2_7 \
3062 { \
3063 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3064 .property = "mem_win_size", \
3065 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
3066 }, \
3067 { \
3068 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3069 .property = "mem64_win_size", \
3070 .value = "0", \
3071 }, \
3072 { \
3073 .driver = TYPE_POWERPC_CPU, \
3074 .property = "pre-2.8-migration", \
3075 .value = "on", \
3076 }, \
3077 { \
3078 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3079 .property = "pre-2.8-migration", \
3080 .value = "on", \
3081 },
3082
3083 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
3084 uint64_t *buid, hwaddr *pio,
3085 hwaddr *mmio32, hwaddr *mmio64,
3086 unsigned n_dma, uint32_t *liobns, Error **errp)
3087 {
3088 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
3089 const uint64_t base_buid = 0x800000020000000ULL;
3090 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
3091 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
3092 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
3093 const uint32_t max_index = 255;
3094 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
3095
3096 uint64_t ram_top = MACHINE(spapr)->ram_size;
3097 hwaddr phb0_base, phb_base;
3098 int i;
3099
3100 /* Do we have hotpluggable memory? */
3101 if (MACHINE(spapr)->maxram_size > ram_top) {
3102 /* Can't just use maxram_size, because there may be an
3103 * alignment gap between normal and hotpluggable memory
3104 * regions */
3105 ram_top = spapr->hotplug_memory.base +
3106 memory_region_size(&spapr->hotplug_memory.mr);
3107 }
3108
3109 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
3110
3111 if (index > max_index) {
3112 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
3113 max_index);
3114 return;
3115 }
3116
3117 *buid = base_buid + index;
3118 for (i = 0; i < n_dma; ++i) {
3119 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3120 }
3121
3122 phb_base = phb0_base + index * phb_spacing;
3123 *pio = phb_base + pio_offset;
3124 *mmio32 = phb_base + mmio_offset;
3125 /*
3126 * We don't set the 64-bit MMIO window, relying on the PHB's
3127 * fallback behaviour of automatically splitting a large "32-bit"
3128 * window into contiguous 32-bit and 64-bit windows
3129 */
3130 }
3131
3132 static void spapr_machine_2_7_instance_options(MachineState *machine)
3133 {
3134 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
3135
3136 spapr_machine_2_8_instance_options(machine);
3137 spapr->use_hotplug_event_source = false;
3138 }
3139
3140 static void spapr_machine_2_7_class_options(MachineClass *mc)
3141 {
3142 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3143
3144 spapr_machine_2_8_class_options(mc);
3145 smc->tcg_default_cpu = "POWER7";
3146 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
3147 smc->phb_placement = phb_placement_2_7;
3148 }
3149
3150 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
3151
3152 /*
3153 * pseries-2.6
3154 */
3155 #define SPAPR_COMPAT_2_6 \
3156 HW_COMPAT_2_6 \
3157 { \
3158 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3159 .property = "ddw",\
3160 .value = stringify(off),\
3161 },
3162
3163 static void spapr_machine_2_6_instance_options(MachineState *machine)
3164 {
3165 spapr_machine_2_7_instance_options(machine);
3166 }
3167
3168 static void spapr_machine_2_6_class_options(MachineClass *mc)
3169 {
3170 spapr_machine_2_7_class_options(mc);
3171 mc->has_hotpluggable_cpus = false;
3172 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
3173 }
3174
3175 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
3176
3177 /*
3178 * pseries-2.5
3179 */
3180 #define SPAPR_COMPAT_2_5 \
3181 HW_COMPAT_2_5 \
3182 { \
3183 .driver = "spapr-vlan", \
3184 .property = "use-rx-buffer-pools", \
3185 .value = "off", \
3186 },
3187
3188 static void spapr_machine_2_5_instance_options(MachineState *machine)
3189 {
3190 spapr_machine_2_6_instance_options(machine);
3191 }
3192
3193 static void spapr_machine_2_5_class_options(MachineClass *mc)
3194 {
3195 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3196
3197 spapr_machine_2_6_class_options(mc);
3198 smc->use_ohci_by_default = true;
3199 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
3200 }
3201
3202 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
3203
3204 /*
3205 * pseries-2.4
3206 */
3207 #define SPAPR_COMPAT_2_4 \
3208 HW_COMPAT_2_4
3209
3210 static void spapr_machine_2_4_instance_options(MachineState *machine)
3211 {
3212 spapr_machine_2_5_instance_options(machine);
3213 }
3214
3215 static void spapr_machine_2_4_class_options(MachineClass *mc)
3216 {
3217 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3218
3219 spapr_machine_2_5_class_options(mc);
3220 smc->dr_lmb_enabled = false;
3221 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
3222 }
3223
3224 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
3225
3226 /*
3227 * pseries-2.3
3228 */
3229 #define SPAPR_COMPAT_2_3 \
3230 HW_COMPAT_2_3 \
3231 {\
3232 .driver = "spapr-pci-host-bridge",\
3233 .property = "dynamic-reconfiguration",\
3234 .value = "off",\
3235 },
3236
3237 static void spapr_machine_2_3_instance_options(MachineState *machine)
3238 {
3239 spapr_machine_2_4_instance_options(machine);
3240 savevm_skip_section_footers();
3241 global_state_set_optional();
3242 savevm_skip_configuration();
3243 }
3244
3245 static void spapr_machine_2_3_class_options(MachineClass *mc)
3246 {
3247 spapr_machine_2_4_class_options(mc);
3248 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
3249 }
3250 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
3251
3252 /*
3253 * pseries-2.2
3254 */
3255
3256 #define SPAPR_COMPAT_2_2 \
3257 HW_COMPAT_2_2 \
3258 {\
3259 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3260 .property = "mem_win_size",\
3261 .value = "0x20000000",\
3262 },
3263
3264 static void spapr_machine_2_2_instance_options(MachineState *machine)
3265 {
3266 spapr_machine_2_3_instance_options(machine);
3267 machine->suppress_vmdesc = true;
3268 }
3269
3270 static void spapr_machine_2_2_class_options(MachineClass *mc)
3271 {
3272 spapr_machine_2_3_class_options(mc);
3273 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
3274 }
3275 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
3276
3277 /*
3278 * pseries-2.1
3279 */
3280 #define SPAPR_COMPAT_2_1 \
3281 HW_COMPAT_2_1
3282
3283 static void spapr_machine_2_1_instance_options(MachineState *machine)
3284 {
3285 spapr_machine_2_2_instance_options(machine);
3286 }
3287
3288 static void spapr_machine_2_1_class_options(MachineClass *mc)
3289 {
3290 spapr_machine_2_2_class_options(mc);
3291 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
3292 }
3293 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
3294
3295 static void spapr_machine_register_types(void)
3296 {
3297 type_register_static(&spapr_machine_info);
3298 }
3299
3300 type_init(spapr_machine_register_types)
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