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spapr_events: add support for dedicated hotplug event source
[mirror_qemu.git] / hw / ppc / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/kvm.h"
40 #include "sysemu/device_tree.h"
41 #include "kvm_ppc.h"
42 #include "migration/migration.h"
43 #include "mmu-hash64.h"
44 #include "qom/cpu.h"
45
46 #include "hw/boards.h"
47 #include "hw/ppc/ppc.h"
48 #include "hw/loader.h"
49
50 #include "hw/ppc/fdt.h"
51 #include "hw/ppc/spapr.h"
52 #include "hw/ppc/spapr_vio.h"
53 #include "hw/pci-host/spapr.h"
54 #include "hw/ppc/xics.h"
55 #include "hw/pci/msi.h"
56
57 #include "hw/pci/pci.h"
58 #include "hw/scsi/scsi.h"
59 #include "hw/virtio/virtio-scsi.h"
60
61 #include "exec/address-spaces.h"
62 #include "hw/usb.h"
63 #include "qemu/config-file.h"
64 #include "qemu/error-report.h"
65 #include "trace.h"
66 #include "hw/nmi.h"
67
68 #include "hw/compat.h"
69 #include "qemu/cutils.h"
70 #include "hw/ppc/spapr_cpu_core.h"
71 #include "qmp-commands.h"
72
73 #include <libfdt.h>
74
75 /* SLOF memory layout:
76 *
77 * SLOF raw image loaded at 0, copies its romfs right below the flat
78 * device-tree, then position SLOF itself 31M below that
79 *
80 * So we set FW_OVERHEAD to 40MB which should account for all of that
81 * and more
82 *
83 * We load our kernel at 4M, leaving space for SLOF initial image
84 */
85 #define FDT_MAX_SIZE 0x100000
86 #define RTAS_MAX_SIZE 0x10000
87 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
88 #define FW_MAX_SIZE 0x400000
89 #define FW_FILE_NAME "slof.bin"
90 #define FW_OVERHEAD 0x2800000
91 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
92
93 #define MIN_RMA_SLOF 128UL
94
95 #define PHANDLE_XICP 0x00001111
96
97 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
98
99 static XICSState *try_create_xics(const char *type, int nr_servers,
100 int nr_irqs, Error **errp)
101 {
102 Error *err = NULL;
103 DeviceState *dev;
104
105 dev = qdev_create(NULL, type);
106 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
107 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
108 object_property_set_bool(OBJECT(dev), true, "realized", &err);
109 if (err) {
110 error_propagate(errp, err);
111 object_unparent(OBJECT(dev));
112 return NULL;
113 }
114 return XICS_COMMON(dev);
115 }
116
117 static XICSState *xics_system_init(MachineState *machine,
118 int nr_servers, int nr_irqs, Error **errp)
119 {
120 XICSState *xics = NULL;
121
122 if (kvm_enabled()) {
123 Error *err = NULL;
124
125 if (machine_kernel_irqchip_allowed(machine)) {
126 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
127 &err);
128 }
129 if (machine_kernel_irqchip_required(machine) && !xics) {
130 error_reportf_err(err,
131 "kernel_irqchip requested but unavailable: ");
132 } else {
133 error_free(err);
134 }
135 }
136
137 if (!xics) {
138 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
139 }
140
141 return xics;
142 }
143
144 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
145 int smt_threads)
146 {
147 int i, ret = 0;
148 uint32_t servers_prop[smt_threads];
149 uint32_t gservers_prop[smt_threads * 2];
150 int index = ppc_get_vcpu_dt_id(cpu);
151
152 if (cpu->cpu_version) {
153 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
154 if (ret < 0) {
155 return ret;
156 }
157 }
158
159 /* Build interrupt servers and gservers properties */
160 for (i = 0; i < smt_threads; i++) {
161 servers_prop[i] = cpu_to_be32(index + i);
162 /* Hack, direct the group queues back to cpu 0 */
163 gservers_prop[i*2] = cpu_to_be32(index + i);
164 gservers_prop[i*2 + 1] = 0;
165 }
166 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
167 servers_prop, sizeof(servers_prop));
168 if (ret < 0) {
169 return ret;
170 }
171 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
172 gservers_prop, sizeof(gservers_prop));
173
174 return ret;
175 }
176
177 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
178 {
179 int ret = 0;
180 PowerPCCPU *cpu = POWERPC_CPU(cs);
181 int index = ppc_get_vcpu_dt_id(cpu);
182 uint32_t associativity[] = {cpu_to_be32(0x5),
183 cpu_to_be32(0x0),
184 cpu_to_be32(0x0),
185 cpu_to_be32(0x0),
186 cpu_to_be32(cs->numa_node),
187 cpu_to_be32(index)};
188
189 /* Advertise NUMA via ibm,associativity */
190 if (nb_numa_nodes > 1) {
191 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
192 sizeof(associativity));
193 }
194
195 return ret;
196 }
197
198 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
199 {
200 int ret = 0, offset, cpus_offset;
201 CPUState *cs;
202 char cpu_model[32];
203 int smt = kvmppc_smt_threads();
204 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
205
206 CPU_FOREACH(cs) {
207 PowerPCCPU *cpu = POWERPC_CPU(cs);
208 DeviceClass *dc = DEVICE_GET_CLASS(cs);
209 int index = ppc_get_vcpu_dt_id(cpu);
210
211 if ((index % smt) != 0) {
212 continue;
213 }
214
215 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
216
217 cpus_offset = fdt_path_offset(fdt, "/cpus");
218 if (cpus_offset < 0) {
219 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
220 "cpus");
221 if (cpus_offset < 0) {
222 return cpus_offset;
223 }
224 }
225 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
226 if (offset < 0) {
227 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
228 if (offset < 0) {
229 return offset;
230 }
231 }
232
233 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
234 pft_size_prop, sizeof(pft_size_prop));
235 if (ret < 0) {
236 return ret;
237 }
238
239 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
240 if (ret < 0) {
241 return ret;
242 }
243
244 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
245 ppc_get_compat_smt_threads(cpu));
246 if (ret < 0) {
247 return ret;
248 }
249 }
250 return ret;
251 }
252
253 static hwaddr spapr_node0_size(void)
254 {
255 MachineState *machine = MACHINE(qdev_get_machine());
256
257 if (nb_numa_nodes) {
258 int i;
259 for (i = 0; i < nb_numa_nodes; ++i) {
260 if (numa_info[i].node_mem) {
261 return MIN(pow2floor(numa_info[i].node_mem),
262 machine->ram_size);
263 }
264 }
265 }
266 return machine->ram_size;
267 }
268
269 static void add_str(GString *s, const gchar *s1)
270 {
271 g_string_append_len(s, s1, strlen(s1) + 1);
272 }
273
274 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
275 hwaddr size)
276 {
277 uint32_t associativity[] = {
278 cpu_to_be32(0x4), /* length */
279 cpu_to_be32(0x0), cpu_to_be32(0x0),
280 cpu_to_be32(0x0), cpu_to_be32(nodeid)
281 };
282 char mem_name[32];
283 uint64_t mem_reg_property[2];
284 int off;
285
286 mem_reg_property[0] = cpu_to_be64(start);
287 mem_reg_property[1] = cpu_to_be64(size);
288
289 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
290 off = fdt_add_subnode(fdt, 0, mem_name);
291 _FDT(off);
292 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
293 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
294 sizeof(mem_reg_property))));
295 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
296 sizeof(associativity))));
297 return off;
298 }
299
300 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
301 {
302 MachineState *machine = MACHINE(spapr);
303 hwaddr mem_start, node_size;
304 int i, nb_nodes = nb_numa_nodes;
305 NodeInfo *nodes = numa_info;
306 NodeInfo ramnode;
307
308 /* No NUMA nodes, assume there is just one node with whole RAM */
309 if (!nb_numa_nodes) {
310 nb_nodes = 1;
311 ramnode.node_mem = machine->ram_size;
312 nodes = &ramnode;
313 }
314
315 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
316 if (!nodes[i].node_mem) {
317 continue;
318 }
319 if (mem_start >= machine->ram_size) {
320 node_size = 0;
321 } else {
322 node_size = nodes[i].node_mem;
323 if (node_size > machine->ram_size - mem_start) {
324 node_size = machine->ram_size - mem_start;
325 }
326 }
327 if (!mem_start) {
328 /* ppc_spapr_init() checks for rma_size <= node0_size already */
329 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
330 mem_start += spapr->rma_size;
331 node_size -= spapr->rma_size;
332 }
333 for ( ; node_size; ) {
334 hwaddr sizetmp = pow2floor(node_size);
335
336 /* mem_start != 0 here */
337 if (ctzl(mem_start) < ctzl(sizetmp)) {
338 sizetmp = 1ULL << ctzl(mem_start);
339 }
340
341 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
342 node_size -= sizetmp;
343 mem_start += sizetmp;
344 }
345 }
346
347 return 0;
348 }
349
350 /* Populate the "ibm,pa-features" property */
351 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
352 {
353 uint8_t pa_features_206[] = { 6, 0,
354 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
355 uint8_t pa_features_207[] = { 24, 0,
356 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
357 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
358 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
359 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
360 uint8_t *pa_features;
361 size_t pa_size;
362
363 switch (env->mmu_model) {
364 case POWERPC_MMU_2_06:
365 case POWERPC_MMU_2_06a:
366 pa_features = pa_features_206;
367 pa_size = sizeof(pa_features_206);
368 break;
369 case POWERPC_MMU_2_07:
370 case POWERPC_MMU_2_07a:
371 pa_features = pa_features_207;
372 pa_size = sizeof(pa_features_207);
373 break;
374 default:
375 return;
376 }
377
378 if (env->ci_large_pages) {
379 /*
380 * Note: we keep CI large pages off by default because a 64K capable
381 * guest provisioned with large pages might otherwise try to map a qemu
382 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
383 * even if that qemu runs on a 4k host.
384 * We dd this bit back here if we are confident this is not an issue
385 */
386 pa_features[3] |= 0x20;
387 }
388 if (kvmppc_has_cap_htm() && pa_size > 24) {
389 pa_features[24] |= 0x80; /* Transactional memory support */
390 }
391
392 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
393 }
394
395 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
396 sPAPRMachineState *spapr)
397 {
398 PowerPCCPU *cpu = POWERPC_CPU(cs);
399 CPUPPCState *env = &cpu->env;
400 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
401 int index = ppc_get_vcpu_dt_id(cpu);
402 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
403 0xffffffff, 0xffffffff};
404 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
405 : SPAPR_TIMEBASE_FREQ;
406 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
407 uint32_t page_sizes_prop[64];
408 size_t page_sizes_prop_size;
409 uint32_t vcpus_per_socket = smp_threads * smp_cores;
410 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
411 sPAPRDRConnector *drc;
412 sPAPRDRConnectorClass *drck;
413 int drc_index;
414
415 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
416 if (drc) {
417 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
418 drc_index = drck->get_index(drc);
419 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
420 }
421
422 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
423 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
424
425 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
426 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
427 env->dcache_line_size)));
428 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
429 env->dcache_line_size)));
430 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
431 env->icache_line_size)));
432 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
433 env->icache_line_size)));
434
435 if (pcc->l1_dcache_size) {
436 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
437 pcc->l1_dcache_size)));
438 } else {
439 error_report("Warning: Unknown L1 dcache size for cpu");
440 }
441 if (pcc->l1_icache_size) {
442 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
443 pcc->l1_icache_size)));
444 } else {
445 error_report("Warning: Unknown L1 icache size for cpu");
446 }
447
448 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
449 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
450 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
451 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
452 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
453 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
454
455 if (env->spr_cb[SPR_PURR].oea_read) {
456 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
457 }
458
459 if (env->mmu_model & POWERPC_MMU_1TSEG) {
460 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
461 segs, sizeof(segs))));
462 }
463
464 /* Advertise VMX/VSX (vector extensions) if available
465 * 0 / no property == no vector extensions
466 * 1 == VMX / Altivec available
467 * 2 == VSX available */
468 if (env->insns_flags & PPC_ALTIVEC) {
469 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
470
471 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
472 }
473
474 /* Advertise DFP (Decimal Floating Point) if available
475 * 0 / no property == no DFP
476 * 1 == DFP available */
477 if (env->insns_flags2 & PPC2_DFP) {
478 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
479 }
480
481 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
482 sizeof(page_sizes_prop));
483 if (page_sizes_prop_size) {
484 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
485 page_sizes_prop, page_sizes_prop_size)));
486 }
487
488 spapr_populate_pa_features(env, fdt, offset);
489
490 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
491 cs->cpu_index / vcpus_per_socket)));
492
493 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
494 pft_size_prop, sizeof(pft_size_prop))));
495
496 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
497
498 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
499 ppc_get_compat_smt_threads(cpu)));
500 }
501
502 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
503 {
504 CPUState *cs;
505 int cpus_offset;
506 char *nodename;
507 int smt = kvmppc_smt_threads();
508
509 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
510 _FDT(cpus_offset);
511 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
512 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
513
514 /*
515 * We walk the CPUs in reverse order to ensure that CPU DT nodes
516 * created by fdt_add_subnode() end up in the right order in FDT
517 * for the guest kernel the enumerate the CPUs correctly.
518 */
519 CPU_FOREACH_REVERSE(cs) {
520 PowerPCCPU *cpu = POWERPC_CPU(cs);
521 int index = ppc_get_vcpu_dt_id(cpu);
522 DeviceClass *dc = DEVICE_GET_CLASS(cs);
523 int offset;
524
525 if ((index % smt) != 0) {
526 continue;
527 }
528
529 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
530 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
531 g_free(nodename);
532 _FDT(offset);
533 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
534 }
535
536 }
537
538 /*
539 * Adds ibm,dynamic-reconfiguration-memory node.
540 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
541 * of this device tree node.
542 */
543 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
544 {
545 MachineState *machine = MACHINE(spapr);
546 int ret, i, offset;
547 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
548 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
549 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
550 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
551 memory_region_size(&spapr->hotplug_memory.mr)) /
552 lmb_size;
553 uint32_t *int_buf, *cur_index, buf_len;
554 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
555
556 /*
557 * Don't create the node if there is no hotpluggable memory
558 */
559 if (machine->ram_size == machine->maxram_size) {
560 return 0;
561 }
562
563 /*
564 * Allocate enough buffer size to fit in ibm,dynamic-memory
565 * or ibm,associativity-lookup-arrays
566 */
567 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
568 * sizeof(uint32_t);
569 cur_index = int_buf = g_malloc0(buf_len);
570
571 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
572
573 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
574 sizeof(prop_lmb_size));
575 if (ret < 0) {
576 goto out;
577 }
578
579 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
580 if (ret < 0) {
581 goto out;
582 }
583
584 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
585 if (ret < 0) {
586 goto out;
587 }
588
589 /* ibm,dynamic-memory */
590 int_buf[0] = cpu_to_be32(nr_lmbs);
591 cur_index++;
592 for (i = 0; i < nr_lmbs; i++) {
593 uint64_t addr = i * lmb_size;
594 uint32_t *dynamic_memory = cur_index;
595
596 if (i >= hotplug_lmb_start) {
597 sPAPRDRConnector *drc;
598 sPAPRDRConnectorClass *drck;
599
600 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
601 g_assert(drc);
602 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
603
604 dynamic_memory[0] = cpu_to_be32(addr >> 32);
605 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
606 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
607 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
608 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
609 if (memory_region_present(get_system_memory(), addr)) {
610 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
611 } else {
612 dynamic_memory[5] = cpu_to_be32(0);
613 }
614 } else {
615 /*
616 * LMB information for RMA, boot time RAM and gap b/n RAM and
617 * hotplug memory region -- all these are marked as reserved
618 * and as having no valid DRC.
619 */
620 dynamic_memory[0] = cpu_to_be32(addr >> 32);
621 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
622 dynamic_memory[2] = cpu_to_be32(0);
623 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
624 dynamic_memory[4] = cpu_to_be32(-1);
625 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
626 SPAPR_LMB_FLAGS_DRC_INVALID);
627 }
628
629 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
630 }
631 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
632 if (ret < 0) {
633 goto out;
634 }
635
636 /* ibm,associativity-lookup-arrays */
637 cur_index = int_buf;
638 int_buf[0] = cpu_to_be32(nr_nodes);
639 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
640 cur_index += 2;
641 for (i = 0; i < nr_nodes; i++) {
642 uint32_t associativity[] = {
643 cpu_to_be32(0x0),
644 cpu_to_be32(0x0),
645 cpu_to_be32(0x0),
646 cpu_to_be32(i)
647 };
648 memcpy(cur_index, associativity, sizeof(associativity));
649 cur_index += 4;
650 }
651 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
652 (cur_index - int_buf) * sizeof(uint32_t));
653 out:
654 g_free(int_buf);
655 return ret;
656 }
657
658 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
659 sPAPROptionVector *ov5_updates)
660 {
661 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
662 int ret = 0, offset;
663
664 /* Generate ibm,dynamic-reconfiguration-memory node if required */
665 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
666 g_assert(smc->dr_lmb_enabled);
667 ret = spapr_populate_drconf_memory(spapr, fdt);
668 if (ret) {
669 goto out;
670 }
671 }
672
673 offset = fdt_path_offset(fdt, "/chosen");
674 if (offset < 0) {
675 offset = fdt_add_subnode(fdt, 0, "chosen");
676 if (offset < 0) {
677 return offset;
678 }
679 }
680 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
681 "ibm,architecture-vec-5");
682
683 out:
684 return ret;
685 }
686
687 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
688 target_ulong addr, target_ulong size,
689 bool cpu_update,
690 sPAPROptionVector *ov5_updates)
691 {
692 void *fdt, *fdt_skel;
693 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
694
695 size -= sizeof(hdr);
696
697 /* Create sceleton */
698 fdt_skel = g_malloc0(size);
699 _FDT((fdt_create(fdt_skel, size)));
700 _FDT((fdt_begin_node(fdt_skel, "")));
701 _FDT((fdt_end_node(fdt_skel)));
702 _FDT((fdt_finish(fdt_skel)));
703 fdt = g_malloc0(size);
704 _FDT((fdt_open_into(fdt_skel, fdt, size)));
705 g_free(fdt_skel);
706
707 /* Fixup cpu nodes */
708 if (cpu_update) {
709 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
710 }
711
712 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
713 return -1;
714 }
715
716 /* Pack resulting tree */
717 _FDT((fdt_pack(fdt)));
718
719 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
720 trace_spapr_cas_failed(size);
721 return -1;
722 }
723
724 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
725 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
726 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
727 g_free(fdt);
728
729 return 0;
730 }
731
732 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
733 {
734 int rtas;
735 GString *hypertas = g_string_sized_new(256);
736 GString *qemu_hypertas = g_string_sized_new(256);
737 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
738 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
739 memory_region_size(&spapr->hotplug_memory.mr);
740 uint32_t lrdr_capacity[] = {
741 cpu_to_be32(max_hotplug_addr >> 32),
742 cpu_to_be32(max_hotplug_addr & 0xffffffff),
743 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
744 cpu_to_be32(max_cpus / smp_threads),
745 };
746
747 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
748
749 /* hypertas */
750 add_str(hypertas, "hcall-pft");
751 add_str(hypertas, "hcall-term");
752 add_str(hypertas, "hcall-dabr");
753 add_str(hypertas, "hcall-interrupt");
754 add_str(hypertas, "hcall-tce");
755 add_str(hypertas, "hcall-vio");
756 add_str(hypertas, "hcall-splpar");
757 add_str(hypertas, "hcall-bulk");
758 add_str(hypertas, "hcall-set-mode");
759 add_str(hypertas, "hcall-sprg0");
760 add_str(hypertas, "hcall-copy");
761 add_str(hypertas, "hcall-debug");
762 add_str(qemu_hypertas, "hcall-memop1");
763
764 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
765 add_str(hypertas, "hcall-multi-tce");
766 }
767 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
768 hypertas->str, hypertas->len));
769 g_string_free(hypertas, TRUE);
770 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
771 qemu_hypertas->str, qemu_hypertas->len));
772 g_string_free(qemu_hypertas, TRUE);
773
774 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
775 refpoints, sizeof(refpoints)));
776
777 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
778 RTAS_ERROR_LOG_MAX));
779 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
780 RTAS_EVENT_SCAN_RATE));
781
782 if (msi_nonbroken) {
783 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
784 }
785
786 /*
787 * According to PAPR, rtas ibm,os-term does not guarantee a return
788 * back to the guest cpu.
789 *
790 * While an additional ibm,extended-os-term property indicates
791 * that rtas call return will always occur. Set this property.
792 */
793 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
794
795 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
796 lrdr_capacity, sizeof(lrdr_capacity)));
797
798 spapr_dt_rtas_tokens(fdt, rtas);
799 }
800
801 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
802 {
803 MachineState *machine = MACHINE(spapr);
804 int chosen;
805 const char *boot_device = machine->boot_order;
806 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
807 size_t cb = 0;
808 char *bootlist = get_boot_devices_list(&cb, true);
809
810 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
811
812 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
813 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
814 spapr->initrd_base));
815 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
816 spapr->initrd_base + spapr->initrd_size));
817
818 if (spapr->kernel_size) {
819 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
820 cpu_to_be64(spapr->kernel_size) };
821
822 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
823 &kprop, sizeof(kprop)));
824 if (spapr->kernel_le) {
825 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
826 }
827 }
828 if (boot_menu) {
829 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
830 }
831 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
832 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
833 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
834
835 if (cb && bootlist) {
836 int i;
837
838 for (i = 0; i < cb; i++) {
839 if (bootlist[i] == '\n') {
840 bootlist[i] = ' ';
841 }
842 }
843 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
844 }
845
846 if (boot_device && strlen(boot_device)) {
847 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
848 }
849
850 if (!spapr->has_graphics && stdout_path) {
851 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
852 }
853
854 g_free(stdout_path);
855 g_free(bootlist);
856 }
857
858 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
859 {
860 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
861 * KVM to work under pHyp with some guest co-operation */
862 int hypervisor;
863 uint8_t hypercall[16];
864
865 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
866 /* indicate KVM hypercall interface */
867 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
868 if (kvmppc_has_cap_fixup_hcalls()) {
869 /*
870 * Older KVM versions with older guest kernels were broken
871 * with the magic page, don't allow the guest to map it.
872 */
873 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
874 sizeof(hypercall))) {
875 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
876 hypercall, sizeof(hypercall)));
877 }
878 }
879 }
880
881 static void *spapr_build_fdt(sPAPRMachineState *spapr,
882 hwaddr rtas_addr,
883 hwaddr rtas_size)
884 {
885 MachineState *machine = MACHINE(qdev_get_machine());
886 MachineClass *mc = MACHINE_GET_CLASS(machine);
887 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
888 int ret;
889 void *fdt;
890 sPAPRPHBState *phb;
891 char *buf;
892
893 fdt = g_malloc0(FDT_MAX_SIZE);
894 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
895
896 /* Root node */
897 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
898 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
899 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
900
901 /*
902 * Add info to guest to indentify which host is it being run on
903 * and what is the uuid of the guest
904 */
905 if (kvmppc_get_host_model(&buf)) {
906 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
907 g_free(buf);
908 }
909 if (kvmppc_get_host_serial(&buf)) {
910 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
911 g_free(buf);
912 }
913
914 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
915
916 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
917 if (qemu_uuid_set) {
918 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
919 }
920 g_free(buf);
921
922 if (qemu_get_vm_name()) {
923 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
924 qemu_get_vm_name()));
925 }
926
927 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
928 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
929
930 /* /interrupt controller */
931 spapr_dt_xics(spapr->xics, fdt, PHANDLE_XICP);
932
933 ret = spapr_populate_memory(spapr, fdt);
934 if (ret < 0) {
935 error_report("couldn't setup memory nodes in fdt");
936 exit(1);
937 }
938
939 /* /vdevice */
940 spapr_dt_vdevice(spapr->vio_bus, fdt);
941
942 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
943 ret = spapr_rng_populate_dt(fdt);
944 if (ret < 0) {
945 error_report("could not set up rng device in the fdt");
946 exit(1);
947 }
948 }
949
950 QLIST_FOREACH(phb, &spapr->phbs, list) {
951 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
952 if (ret < 0) {
953 error_report("couldn't setup PCI devices in fdt");
954 exit(1);
955 }
956 }
957
958 /* cpus */
959 spapr_populate_cpus_dt_node(fdt, spapr);
960
961 if (smc->dr_lmb_enabled) {
962 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
963 }
964
965 if (mc->query_hotpluggable_cpus) {
966 int offset = fdt_path_offset(fdt, "/cpus");
967 ret = spapr_drc_populate_dt(fdt, offset, NULL,
968 SPAPR_DR_CONNECTOR_TYPE_CPU);
969 if (ret < 0) {
970 error_report("Couldn't set up CPU DR device tree properties");
971 exit(1);
972 }
973 }
974
975 /* /event-sources */
976 spapr_dt_events(spapr, fdt);
977
978 /* /rtas */
979 spapr_dt_rtas(spapr, fdt);
980
981 /* /chosen */
982 spapr_dt_chosen(spapr, fdt);
983
984 /* /hypervisor */
985 if (kvm_enabled()) {
986 spapr_dt_hypervisor(spapr, fdt);
987 }
988
989 /* Build memory reserve map */
990 if (spapr->kernel_size) {
991 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
992 }
993 if (spapr->initrd_size) {
994 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
995 }
996
997 /* ibm,client-architecture-support updates */
998 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
999 if (ret < 0) {
1000 error_report("couldn't setup CAS properties fdt");
1001 exit(1);
1002 }
1003
1004 return fdt;
1005 }
1006
1007 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1008 {
1009 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1010 }
1011
1012 static void emulate_spapr_hypercall(PowerPCCPU *cpu)
1013 {
1014 CPUPPCState *env = &cpu->env;
1015
1016 if (msr_pr) {
1017 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1018 env->gpr[3] = H_PRIVILEGE;
1019 } else {
1020 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1021 }
1022 }
1023
1024 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1025 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1026 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1027 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1028 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1029
1030 /*
1031 * Get the fd to access the kernel htab, re-opening it if necessary
1032 */
1033 static int get_htab_fd(sPAPRMachineState *spapr)
1034 {
1035 if (spapr->htab_fd >= 0) {
1036 return spapr->htab_fd;
1037 }
1038
1039 spapr->htab_fd = kvmppc_get_htab_fd(false);
1040 if (spapr->htab_fd < 0) {
1041 error_report("Unable to open fd for reading hash table from KVM: %s",
1042 strerror(errno));
1043 }
1044
1045 return spapr->htab_fd;
1046 }
1047
1048 static void close_htab_fd(sPAPRMachineState *spapr)
1049 {
1050 if (spapr->htab_fd >= 0) {
1051 close(spapr->htab_fd);
1052 }
1053 spapr->htab_fd = -1;
1054 }
1055
1056 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1057 {
1058 int shift;
1059
1060 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1061 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1062 * that's much more than is needed for Linux guests */
1063 shift = ctz64(pow2ceil(ramsize)) - 7;
1064 shift = MAX(shift, 18); /* Minimum architected size */
1065 shift = MIN(shift, 46); /* Maximum architected size */
1066 return shift;
1067 }
1068
1069 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1070 Error **errp)
1071 {
1072 long rc;
1073
1074 /* Clean up any HPT info from a previous boot */
1075 g_free(spapr->htab);
1076 spapr->htab = NULL;
1077 spapr->htab_shift = 0;
1078 close_htab_fd(spapr);
1079
1080 rc = kvmppc_reset_htab(shift);
1081 if (rc < 0) {
1082 /* kernel-side HPT needed, but couldn't allocate one */
1083 error_setg_errno(errp, errno,
1084 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1085 shift);
1086 /* This is almost certainly fatal, but if the caller really
1087 * wants to carry on with shift == 0, it's welcome to try */
1088 } else if (rc > 0) {
1089 /* kernel-side HPT allocated */
1090 if (rc != shift) {
1091 error_setg(errp,
1092 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1093 shift, rc);
1094 }
1095
1096 spapr->htab_shift = shift;
1097 spapr->htab = NULL;
1098 } else {
1099 /* kernel-side HPT not needed, allocate in userspace instead */
1100 size_t size = 1ULL << shift;
1101 int i;
1102
1103 spapr->htab = qemu_memalign(size, size);
1104 if (!spapr->htab) {
1105 error_setg_errno(errp, errno,
1106 "Could not allocate HPT of order %d", shift);
1107 return;
1108 }
1109
1110 memset(spapr->htab, 0, size);
1111 spapr->htab_shift = shift;
1112
1113 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1114 DIRTY_HPTE(HPTE(spapr->htab, i));
1115 }
1116 }
1117 }
1118
1119 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1120 {
1121 bool matched = false;
1122
1123 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1124 matched = true;
1125 }
1126
1127 if (!matched) {
1128 error_report("Device %s is not supported by this machine yet.",
1129 qdev_fw_name(DEVICE(sbdev)));
1130 exit(1);
1131 }
1132 }
1133
1134 static void ppc_spapr_reset(void)
1135 {
1136 MachineState *machine = MACHINE(qdev_get_machine());
1137 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1138 PowerPCCPU *first_ppc_cpu;
1139 uint32_t rtas_limit;
1140 hwaddr rtas_addr, fdt_addr;
1141 void *fdt;
1142 int rc;
1143
1144 /* Check for unknown sysbus devices */
1145 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1146
1147 /* Allocate and/or reset the hash page table */
1148 spapr_reallocate_hpt(spapr,
1149 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1150 &error_fatal);
1151
1152 /* Update the RMA size if necessary */
1153 if (spapr->vrma_adjust) {
1154 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1155 spapr->htab_shift);
1156 }
1157
1158 qemu_devices_reset();
1159
1160 /*
1161 * We place the device tree and RTAS just below either the top of the RMA,
1162 * or just below 2GB, whichever is lowere, so that it can be
1163 * processed with 32-bit real mode code if necessary
1164 */
1165 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1166 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1167 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1168
1169 /* if this reset wasn't generated by CAS, we should reset our
1170 * negotiated options and start from scratch */
1171 if (!spapr->cas_reboot) {
1172 spapr_ovec_cleanup(spapr->ov5_cas);
1173 spapr->ov5_cas = spapr_ovec_new();
1174 }
1175
1176 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1177
1178 spapr_load_rtas(spapr, fdt, rtas_addr);
1179
1180 rc = fdt_pack(fdt);
1181
1182 /* Should only fail if we've built a corrupted tree */
1183 assert(rc == 0);
1184
1185 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1186 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1187 fdt_totalsize(fdt), FDT_MAX_SIZE);
1188 exit(1);
1189 }
1190
1191 /* Load the fdt */
1192 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1193 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1194 g_free(fdt);
1195
1196 /* Set up the entry state */
1197 first_ppc_cpu = POWERPC_CPU(first_cpu);
1198 first_ppc_cpu->env.gpr[3] = fdt_addr;
1199 first_ppc_cpu->env.gpr[5] = 0;
1200 first_cpu->halted = 0;
1201 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1202
1203 spapr->cas_reboot = false;
1204 }
1205
1206 static void spapr_create_nvram(sPAPRMachineState *spapr)
1207 {
1208 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1209 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1210
1211 if (dinfo) {
1212 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1213 &error_fatal);
1214 }
1215
1216 qdev_init_nofail(dev);
1217
1218 spapr->nvram = (struct sPAPRNVRAM *)dev;
1219 }
1220
1221 static void spapr_rtc_create(sPAPRMachineState *spapr)
1222 {
1223 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1224
1225 qdev_init_nofail(dev);
1226 spapr->rtc = dev;
1227
1228 object_property_add_alias(qdev_get_machine(), "rtc-time",
1229 OBJECT(spapr->rtc), "date", NULL);
1230 }
1231
1232 /* Returns whether we want to use VGA or not */
1233 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1234 {
1235 switch (vga_interface_type) {
1236 case VGA_NONE:
1237 return false;
1238 case VGA_DEVICE:
1239 return true;
1240 case VGA_STD:
1241 case VGA_VIRTIO:
1242 return pci_vga_init(pci_bus) != NULL;
1243 default:
1244 error_setg(errp,
1245 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1246 return false;
1247 }
1248 }
1249
1250 static int spapr_post_load(void *opaque, int version_id)
1251 {
1252 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1253 int err = 0;
1254
1255 /* In earlier versions, there was no separate qdev for the PAPR
1256 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1257 * So when migrating from those versions, poke the incoming offset
1258 * value into the RTC device */
1259 if (version_id < 3) {
1260 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1261 }
1262
1263 return err;
1264 }
1265
1266 static bool version_before_3(void *opaque, int version_id)
1267 {
1268 return version_id < 3;
1269 }
1270
1271 static const VMStateDescription vmstate_spapr = {
1272 .name = "spapr",
1273 .version_id = 3,
1274 .minimum_version_id = 1,
1275 .post_load = spapr_post_load,
1276 .fields = (VMStateField[]) {
1277 /* used to be @next_irq */
1278 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1279
1280 /* RTC offset */
1281 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1282
1283 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1284 VMSTATE_END_OF_LIST()
1285 },
1286 };
1287
1288 static int htab_save_setup(QEMUFile *f, void *opaque)
1289 {
1290 sPAPRMachineState *spapr = opaque;
1291
1292 /* "Iteration" header */
1293 qemu_put_be32(f, spapr->htab_shift);
1294
1295 if (spapr->htab) {
1296 spapr->htab_save_index = 0;
1297 spapr->htab_first_pass = true;
1298 } else {
1299 assert(kvm_enabled());
1300 }
1301
1302
1303 return 0;
1304 }
1305
1306 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1307 int64_t max_ns)
1308 {
1309 bool has_timeout = max_ns != -1;
1310 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1311 int index = spapr->htab_save_index;
1312 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1313
1314 assert(spapr->htab_first_pass);
1315
1316 do {
1317 int chunkstart;
1318
1319 /* Consume invalid HPTEs */
1320 while ((index < htabslots)
1321 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1322 index++;
1323 CLEAN_HPTE(HPTE(spapr->htab, index));
1324 }
1325
1326 /* Consume valid HPTEs */
1327 chunkstart = index;
1328 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1329 && HPTE_VALID(HPTE(spapr->htab, index))) {
1330 index++;
1331 CLEAN_HPTE(HPTE(spapr->htab, index));
1332 }
1333
1334 if (index > chunkstart) {
1335 int n_valid = index - chunkstart;
1336
1337 qemu_put_be32(f, chunkstart);
1338 qemu_put_be16(f, n_valid);
1339 qemu_put_be16(f, 0);
1340 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1341 HASH_PTE_SIZE_64 * n_valid);
1342
1343 if (has_timeout &&
1344 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1345 break;
1346 }
1347 }
1348 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1349
1350 if (index >= htabslots) {
1351 assert(index == htabslots);
1352 index = 0;
1353 spapr->htab_first_pass = false;
1354 }
1355 spapr->htab_save_index = index;
1356 }
1357
1358 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1359 int64_t max_ns)
1360 {
1361 bool final = max_ns < 0;
1362 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1363 int examined = 0, sent = 0;
1364 int index = spapr->htab_save_index;
1365 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1366
1367 assert(!spapr->htab_first_pass);
1368
1369 do {
1370 int chunkstart, invalidstart;
1371
1372 /* Consume non-dirty HPTEs */
1373 while ((index < htabslots)
1374 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1375 index++;
1376 examined++;
1377 }
1378
1379 chunkstart = index;
1380 /* Consume valid dirty HPTEs */
1381 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1382 && HPTE_DIRTY(HPTE(spapr->htab, index))
1383 && HPTE_VALID(HPTE(spapr->htab, index))) {
1384 CLEAN_HPTE(HPTE(spapr->htab, index));
1385 index++;
1386 examined++;
1387 }
1388
1389 invalidstart = index;
1390 /* Consume invalid dirty HPTEs */
1391 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1392 && HPTE_DIRTY(HPTE(spapr->htab, index))
1393 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1394 CLEAN_HPTE(HPTE(spapr->htab, index));
1395 index++;
1396 examined++;
1397 }
1398
1399 if (index > chunkstart) {
1400 int n_valid = invalidstart - chunkstart;
1401 int n_invalid = index - invalidstart;
1402
1403 qemu_put_be32(f, chunkstart);
1404 qemu_put_be16(f, n_valid);
1405 qemu_put_be16(f, n_invalid);
1406 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1407 HASH_PTE_SIZE_64 * n_valid);
1408 sent += index - chunkstart;
1409
1410 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1411 break;
1412 }
1413 }
1414
1415 if (examined >= htabslots) {
1416 break;
1417 }
1418
1419 if (index >= htabslots) {
1420 assert(index == htabslots);
1421 index = 0;
1422 }
1423 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1424
1425 if (index >= htabslots) {
1426 assert(index == htabslots);
1427 index = 0;
1428 }
1429
1430 spapr->htab_save_index = index;
1431
1432 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1433 }
1434
1435 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1436 #define MAX_KVM_BUF_SIZE 2048
1437
1438 static int htab_save_iterate(QEMUFile *f, void *opaque)
1439 {
1440 sPAPRMachineState *spapr = opaque;
1441 int fd;
1442 int rc = 0;
1443
1444 /* Iteration header */
1445 qemu_put_be32(f, 0);
1446
1447 if (!spapr->htab) {
1448 assert(kvm_enabled());
1449
1450 fd = get_htab_fd(spapr);
1451 if (fd < 0) {
1452 return fd;
1453 }
1454
1455 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1456 if (rc < 0) {
1457 return rc;
1458 }
1459 } else if (spapr->htab_first_pass) {
1460 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1461 } else {
1462 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1463 }
1464
1465 /* End marker */
1466 qemu_put_be32(f, 0);
1467 qemu_put_be16(f, 0);
1468 qemu_put_be16(f, 0);
1469
1470 return rc;
1471 }
1472
1473 static int htab_save_complete(QEMUFile *f, void *opaque)
1474 {
1475 sPAPRMachineState *spapr = opaque;
1476 int fd;
1477
1478 /* Iteration header */
1479 qemu_put_be32(f, 0);
1480
1481 if (!spapr->htab) {
1482 int rc;
1483
1484 assert(kvm_enabled());
1485
1486 fd = get_htab_fd(spapr);
1487 if (fd < 0) {
1488 return fd;
1489 }
1490
1491 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1492 if (rc < 0) {
1493 return rc;
1494 }
1495 } else {
1496 if (spapr->htab_first_pass) {
1497 htab_save_first_pass(f, spapr, -1);
1498 }
1499 htab_save_later_pass(f, spapr, -1);
1500 }
1501
1502 /* End marker */
1503 qemu_put_be32(f, 0);
1504 qemu_put_be16(f, 0);
1505 qemu_put_be16(f, 0);
1506
1507 return 0;
1508 }
1509
1510 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1511 {
1512 sPAPRMachineState *spapr = opaque;
1513 uint32_t section_hdr;
1514 int fd = -1;
1515
1516 if (version_id < 1 || version_id > 1) {
1517 error_report("htab_load() bad version");
1518 return -EINVAL;
1519 }
1520
1521 section_hdr = qemu_get_be32(f);
1522
1523 if (section_hdr) {
1524 Error *local_err = NULL;
1525
1526 /* First section gives the htab size */
1527 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1528 if (local_err) {
1529 error_report_err(local_err);
1530 return -EINVAL;
1531 }
1532 return 0;
1533 }
1534
1535 if (!spapr->htab) {
1536 assert(kvm_enabled());
1537
1538 fd = kvmppc_get_htab_fd(true);
1539 if (fd < 0) {
1540 error_report("Unable to open fd to restore KVM hash table: %s",
1541 strerror(errno));
1542 }
1543 }
1544
1545 while (true) {
1546 uint32_t index;
1547 uint16_t n_valid, n_invalid;
1548
1549 index = qemu_get_be32(f);
1550 n_valid = qemu_get_be16(f);
1551 n_invalid = qemu_get_be16(f);
1552
1553 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1554 /* End of Stream */
1555 break;
1556 }
1557
1558 if ((index + n_valid + n_invalid) >
1559 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1560 /* Bad index in stream */
1561 error_report(
1562 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1563 index, n_valid, n_invalid, spapr->htab_shift);
1564 return -EINVAL;
1565 }
1566
1567 if (spapr->htab) {
1568 if (n_valid) {
1569 qemu_get_buffer(f, HPTE(spapr->htab, index),
1570 HASH_PTE_SIZE_64 * n_valid);
1571 }
1572 if (n_invalid) {
1573 memset(HPTE(spapr->htab, index + n_valid), 0,
1574 HASH_PTE_SIZE_64 * n_invalid);
1575 }
1576 } else {
1577 int rc;
1578
1579 assert(fd >= 0);
1580
1581 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1582 if (rc < 0) {
1583 return rc;
1584 }
1585 }
1586 }
1587
1588 if (!spapr->htab) {
1589 assert(fd >= 0);
1590 close(fd);
1591 }
1592
1593 return 0;
1594 }
1595
1596 static void htab_cleanup(void *opaque)
1597 {
1598 sPAPRMachineState *spapr = opaque;
1599
1600 close_htab_fd(spapr);
1601 }
1602
1603 static SaveVMHandlers savevm_htab_handlers = {
1604 .save_live_setup = htab_save_setup,
1605 .save_live_iterate = htab_save_iterate,
1606 .save_live_complete_precopy = htab_save_complete,
1607 .cleanup = htab_cleanup,
1608 .load_state = htab_load,
1609 };
1610
1611 static void spapr_boot_set(void *opaque, const char *boot_device,
1612 Error **errp)
1613 {
1614 MachineState *machine = MACHINE(qdev_get_machine());
1615 machine->boot_order = g_strdup(boot_device);
1616 }
1617
1618 /*
1619 * Reset routine for LMB DR devices.
1620 *
1621 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1622 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1623 * when it walks all its children devices. LMB devices reset occurs
1624 * as part of spapr_ppc_reset().
1625 */
1626 static void spapr_drc_reset(void *opaque)
1627 {
1628 sPAPRDRConnector *drc = opaque;
1629 DeviceState *d = DEVICE(drc);
1630
1631 if (d) {
1632 device_reset(d);
1633 }
1634 }
1635
1636 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1637 {
1638 MachineState *machine = MACHINE(spapr);
1639 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1640 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1641 int i;
1642
1643 for (i = 0; i < nr_lmbs; i++) {
1644 sPAPRDRConnector *drc;
1645 uint64_t addr;
1646
1647 addr = i * lmb_size + spapr->hotplug_memory.base;
1648 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1649 addr/lmb_size);
1650 qemu_register_reset(spapr_drc_reset, drc);
1651 }
1652 }
1653
1654 /*
1655 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1656 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1657 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1658 */
1659 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1660 {
1661 int i;
1662
1663 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1664 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1665 " is not aligned to %llu MiB",
1666 machine->ram_size,
1667 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1668 return;
1669 }
1670
1671 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1672 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1673 " is not aligned to %llu MiB",
1674 machine->ram_size,
1675 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1676 return;
1677 }
1678
1679 for (i = 0; i < nb_numa_nodes; i++) {
1680 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1681 error_setg(errp,
1682 "Node %d memory size 0x%" PRIx64
1683 " is not aligned to %llu MiB",
1684 i, numa_info[i].node_mem,
1685 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1686 return;
1687 }
1688 }
1689 }
1690
1691 /* pSeries LPAR / sPAPR hardware init */
1692 static void ppc_spapr_init(MachineState *machine)
1693 {
1694 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1695 MachineClass *mc = MACHINE_GET_CLASS(machine);
1696 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1697 const char *kernel_filename = machine->kernel_filename;
1698 const char *initrd_filename = machine->initrd_filename;
1699 PCIHostState *phb;
1700 int i;
1701 MemoryRegion *sysmem = get_system_memory();
1702 MemoryRegion *ram = g_new(MemoryRegion, 1);
1703 MemoryRegion *rma_region;
1704 void *rma = NULL;
1705 hwaddr rma_alloc_size;
1706 hwaddr node0_size = spapr_node0_size();
1707 long load_limit, fw_size;
1708 char *filename;
1709 int smt = kvmppc_smt_threads();
1710 int spapr_cores = smp_cpus / smp_threads;
1711 int spapr_max_cores = max_cpus / smp_threads;
1712
1713 if (mc->query_hotpluggable_cpus) {
1714 if (smp_cpus % smp_threads) {
1715 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1716 smp_cpus, smp_threads);
1717 exit(1);
1718 }
1719 if (max_cpus % smp_threads) {
1720 error_report("max_cpus (%u) must be multiple of threads (%u)",
1721 max_cpus, smp_threads);
1722 exit(1);
1723 }
1724 }
1725
1726 msi_nonbroken = true;
1727
1728 QLIST_INIT(&spapr->phbs);
1729
1730 cpu_ppc_hypercall = emulate_spapr_hypercall;
1731
1732 /* Allocate RMA if necessary */
1733 rma_alloc_size = kvmppc_alloc_rma(&rma);
1734
1735 if (rma_alloc_size == -1) {
1736 error_report("Unable to create RMA");
1737 exit(1);
1738 }
1739
1740 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1741 spapr->rma_size = rma_alloc_size;
1742 } else {
1743 spapr->rma_size = node0_size;
1744
1745 /* With KVM, we don't actually know whether KVM supports an
1746 * unbounded RMA (PR KVM) or is limited by the hash table size
1747 * (HV KVM using VRMA), so we always assume the latter
1748 *
1749 * In that case, we also limit the initial allocations for RTAS
1750 * etc... to 256M since we have no way to know what the VRMA size
1751 * is going to be as it depends on the size of the hash table
1752 * isn't determined yet.
1753 */
1754 if (kvm_enabled()) {
1755 spapr->vrma_adjust = 1;
1756 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1757 }
1758
1759 /* Actually we don't support unbounded RMA anymore since we
1760 * added proper emulation of HV mode. The max we can get is
1761 * 16G which also happens to be what we configure for PAPR
1762 * mode so make sure we don't do anything bigger than that
1763 */
1764 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
1765 }
1766
1767 if (spapr->rma_size > node0_size) {
1768 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1769 spapr->rma_size);
1770 exit(1);
1771 }
1772
1773 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1774 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1775
1776 /* Set up Interrupt Controller before we create the VCPUs */
1777 spapr->xics = xics_system_init(machine,
1778 DIV_ROUND_UP(max_cpus * smt, smp_threads),
1779 XICS_IRQS_SPAPR, &error_fatal);
1780
1781 /* Set up containers for ibm,client-set-architecture negotiated options */
1782 spapr->ov5 = spapr_ovec_new();
1783 spapr->ov5_cas = spapr_ovec_new();
1784
1785 if (smc->dr_lmb_enabled) {
1786 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
1787 spapr_validate_node_memory(machine, &error_fatal);
1788 }
1789
1790 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
1791
1792 /* advertise support for dedicated HP event source to guests */
1793 if (spapr->use_hotplug_event_source) {
1794 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
1795 }
1796
1797 /* init CPUs */
1798 if (machine->cpu_model == NULL) {
1799 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
1800 }
1801
1802 ppc_cpu_parse_features(machine->cpu_model);
1803
1804 if (mc->query_hotpluggable_cpus) {
1805 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1806
1807 if (type == NULL) {
1808 error_report("Unable to find sPAPR CPU Core definition");
1809 exit(1);
1810 }
1811
1812 spapr->cores = g_new0(Object *, spapr_max_cores);
1813 for (i = 0; i < spapr_max_cores; i++) {
1814 int core_id = i * smp_threads;
1815 sPAPRDRConnector *drc =
1816 spapr_dr_connector_new(OBJECT(spapr),
1817 SPAPR_DR_CONNECTOR_TYPE_CPU,
1818 (core_id / smp_threads) * smt);
1819
1820 qemu_register_reset(spapr_drc_reset, drc);
1821
1822 if (i < spapr_cores) {
1823 Object *core = object_new(type);
1824 object_property_set_int(core, smp_threads, "nr-threads",
1825 &error_fatal);
1826 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
1827 &error_fatal);
1828 object_property_set_bool(core, true, "realized", &error_fatal);
1829 }
1830 }
1831 g_free(type);
1832 } else {
1833 for (i = 0; i < smp_cpus; i++) {
1834 PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model);
1835 if (cpu == NULL) {
1836 error_report("Unable to find PowerPC CPU definition");
1837 exit(1);
1838 }
1839 spapr_cpu_init(spapr, cpu, &error_fatal);
1840 }
1841 }
1842
1843 if (kvm_enabled()) {
1844 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1845 kvmppc_enable_logical_ci_hcalls();
1846 kvmppc_enable_set_mode_hcall();
1847
1848 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
1849 kvmppc_enable_clear_ref_mod_hcalls();
1850 }
1851
1852 /* allocate RAM */
1853 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
1854 machine->ram_size);
1855 memory_region_add_subregion(sysmem, 0, ram);
1856
1857 if (rma_alloc_size && rma) {
1858 rma_region = g_new(MemoryRegion, 1);
1859 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1860 rma_alloc_size, rma);
1861 vmstate_register_ram_global(rma_region);
1862 memory_region_add_subregion(sysmem, 0, rma_region);
1863 }
1864
1865 /* initialize hotplug memory address space */
1866 if (machine->ram_size < machine->maxram_size) {
1867 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1868 /*
1869 * Limit the number of hotpluggable memory slots to half the number
1870 * slots that KVM supports, leaving the other half for PCI and other
1871 * devices. However ensure that number of slots doesn't drop below 32.
1872 */
1873 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
1874 SPAPR_MAX_RAM_SLOTS;
1875
1876 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
1877 max_memslots = SPAPR_MAX_RAM_SLOTS;
1878 }
1879 if (machine->ram_slots > max_memslots) {
1880 error_report("Specified number of memory slots %"
1881 PRIu64" exceeds max supported %d",
1882 machine->ram_slots, max_memslots);
1883 exit(1);
1884 }
1885
1886 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1887 SPAPR_HOTPLUG_MEM_ALIGN);
1888 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1889 "hotplug-memory", hotplug_mem_size);
1890 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1891 &spapr->hotplug_memory.mr);
1892 }
1893
1894 if (smc->dr_lmb_enabled) {
1895 spapr_create_lmb_dr_connectors(spapr);
1896 }
1897
1898 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1899 if (!filename) {
1900 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1901 exit(1);
1902 }
1903 spapr->rtas_size = get_image_size(filename);
1904 if (spapr->rtas_size < 0) {
1905 error_report("Could not get size of LPAR rtas '%s'", filename);
1906 exit(1);
1907 }
1908 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1909 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
1910 error_report("Could not load LPAR rtas '%s'", filename);
1911 exit(1);
1912 }
1913 if (spapr->rtas_size > RTAS_MAX_SIZE) {
1914 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1915 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
1916 exit(1);
1917 }
1918 g_free(filename);
1919
1920 /* Set up RTAS event infrastructure */
1921 spapr_events_init(spapr);
1922
1923 /* Set up the RTC RTAS interfaces */
1924 spapr_rtc_create(spapr);
1925
1926 /* Set up VIO bus */
1927 spapr->vio_bus = spapr_vio_bus_init();
1928
1929 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1930 if (serial_hds[i]) {
1931 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1932 }
1933 }
1934
1935 /* We always have at least the nvram device on VIO */
1936 spapr_create_nvram(spapr);
1937
1938 /* Set up PCI */
1939 spapr_pci_rtas_init();
1940
1941 phb = spapr_create_phb(spapr, 0);
1942
1943 for (i = 0; i < nb_nics; i++) {
1944 NICInfo *nd = &nd_table[i];
1945
1946 if (!nd->model) {
1947 nd->model = g_strdup("ibmveth");
1948 }
1949
1950 if (strcmp(nd->model, "ibmveth") == 0) {
1951 spapr_vlan_create(spapr->vio_bus, nd);
1952 } else {
1953 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1954 }
1955 }
1956
1957 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1958 spapr_vscsi_create(spapr->vio_bus);
1959 }
1960
1961 /* Graphics */
1962 if (spapr_vga_init(phb->bus, &error_fatal)) {
1963 spapr->has_graphics = true;
1964 machine->usb |= defaults_enabled() && !machine->usb_disabled;
1965 }
1966
1967 if (machine->usb) {
1968 if (smc->use_ohci_by_default) {
1969 pci_create_simple(phb->bus, -1, "pci-ohci");
1970 } else {
1971 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1972 }
1973
1974 if (spapr->has_graphics) {
1975 USBBus *usb_bus = usb_bus_find(-1);
1976
1977 usb_create_simple(usb_bus, "usb-kbd");
1978 usb_create_simple(usb_bus, "usb-mouse");
1979 }
1980 }
1981
1982 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
1983 error_report(
1984 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
1985 MIN_RMA_SLOF);
1986 exit(1);
1987 }
1988
1989 if (kernel_filename) {
1990 uint64_t lowaddr = 0;
1991
1992 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
1993 NULL, NULL, &lowaddr, NULL, 1,
1994 PPC_ELF_MACHINE, 0, 0);
1995 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
1996 spapr->kernel_size = load_elf(kernel_filename,
1997 translate_kernel_address, NULL, NULL,
1998 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
1999 0, 0);
2000 spapr->kernel_le = spapr->kernel_size > 0;
2001 }
2002 if (spapr->kernel_size < 0) {
2003 error_report("error loading %s: %s", kernel_filename,
2004 load_elf_strerror(spapr->kernel_size));
2005 exit(1);
2006 }
2007
2008 /* load initrd */
2009 if (initrd_filename) {
2010 /* Try to locate the initrd in the gap between the kernel
2011 * and the firmware. Add a bit of space just in case
2012 */
2013 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2014 + 0x1ffff) & ~0xffff;
2015 spapr->initrd_size = load_image_targphys(initrd_filename,
2016 spapr->initrd_base,
2017 load_limit
2018 - spapr->initrd_base);
2019 if (spapr->initrd_size < 0) {
2020 error_report("could not load initial ram disk '%s'",
2021 initrd_filename);
2022 exit(1);
2023 }
2024 }
2025 }
2026
2027 if (bios_name == NULL) {
2028 bios_name = FW_FILE_NAME;
2029 }
2030 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2031 if (!filename) {
2032 error_report("Could not find LPAR firmware '%s'", bios_name);
2033 exit(1);
2034 }
2035 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2036 if (fw_size <= 0) {
2037 error_report("Could not load LPAR firmware '%s'", filename);
2038 exit(1);
2039 }
2040 g_free(filename);
2041
2042 /* FIXME: Should register things through the MachineState's qdev
2043 * interface, this is a legacy from the sPAPREnvironment structure
2044 * which predated MachineState but had a similar function */
2045 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2046 register_savevm_live(NULL, "spapr/htab", -1, 1,
2047 &savevm_htab_handlers, spapr);
2048
2049 /* used by RTAS */
2050 QTAILQ_INIT(&spapr->ccs_list);
2051 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2052
2053 qemu_register_boot_set(spapr_boot_set, spapr);
2054 }
2055
2056 static int spapr_kvm_type(const char *vm_type)
2057 {
2058 if (!vm_type) {
2059 return 0;
2060 }
2061
2062 if (!strcmp(vm_type, "HV")) {
2063 return 1;
2064 }
2065
2066 if (!strcmp(vm_type, "PR")) {
2067 return 2;
2068 }
2069
2070 error_report("Unknown kvm-type specified '%s'", vm_type);
2071 exit(1);
2072 }
2073
2074 /*
2075 * Implementation of an interface to adjust firmware path
2076 * for the bootindex property handling.
2077 */
2078 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2079 DeviceState *dev)
2080 {
2081 #define CAST(type, obj, name) \
2082 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2083 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2084 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2085
2086 if (d) {
2087 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2088 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2089 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2090
2091 if (spapr) {
2092 /*
2093 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2094 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2095 * in the top 16 bits of the 64-bit LUN
2096 */
2097 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2098 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2099 (uint64_t)id << 48);
2100 } else if (virtio) {
2101 /*
2102 * We use SRP luns of the form 01000000 | (target << 8) | lun
2103 * in the top 32 bits of the 64-bit LUN
2104 * Note: the quote above is from SLOF and it is wrong,
2105 * the actual binding is:
2106 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2107 */
2108 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2109 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2110 (uint64_t)id << 32);
2111 } else if (usb) {
2112 /*
2113 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2114 * in the top 32 bits of the 64-bit LUN
2115 */
2116 unsigned usb_port = atoi(usb->port->path);
2117 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2118 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2119 (uint64_t)id << 32);
2120 }
2121 }
2122
2123 if (phb) {
2124 /* Replace "pci" with "pci@800000020000000" */
2125 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2126 }
2127
2128 return NULL;
2129 }
2130
2131 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2132 {
2133 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2134
2135 return g_strdup(spapr->kvm_type);
2136 }
2137
2138 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2139 {
2140 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2141
2142 g_free(spapr->kvm_type);
2143 spapr->kvm_type = g_strdup(value);
2144 }
2145
2146 static void spapr_machine_initfn(Object *obj)
2147 {
2148 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2149
2150 spapr->htab_fd = -1;
2151 object_property_add_str(obj, "kvm-type",
2152 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2153 object_property_set_description(obj, "kvm-type",
2154 "Specifies the KVM virtualization mode (HV, PR)",
2155 NULL);
2156 }
2157
2158 static void spapr_machine_finalizefn(Object *obj)
2159 {
2160 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2161
2162 g_free(spapr->kvm_type);
2163 }
2164
2165 static void ppc_cpu_do_nmi_on_cpu(CPUState *cs, void *arg)
2166 {
2167 cpu_synchronize_state(cs);
2168 ppc_cpu_do_system_reset(cs);
2169 }
2170
2171 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2172 {
2173 CPUState *cs;
2174
2175 CPU_FOREACH(cs) {
2176 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, NULL);
2177 }
2178 }
2179
2180 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2181 uint32_t node, Error **errp)
2182 {
2183 sPAPRDRConnector *drc;
2184 sPAPRDRConnectorClass *drck;
2185 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2186 int i, fdt_offset, fdt_size;
2187 void *fdt;
2188
2189 for (i = 0; i < nr_lmbs; i++) {
2190 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2191 addr/SPAPR_MEMORY_BLOCK_SIZE);
2192 g_assert(drc);
2193
2194 fdt = create_device_tree(&fdt_size);
2195 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2196 SPAPR_MEMORY_BLOCK_SIZE);
2197
2198 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2199 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2200 addr += SPAPR_MEMORY_BLOCK_SIZE;
2201 }
2202 /* send hotplug notification to the
2203 * guest only in case of hotplugged memory
2204 */
2205 if (dev->hotplugged) {
2206 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2207 }
2208 }
2209
2210 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2211 uint32_t node, Error **errp)
2212 {
2213 Error *local_err = NULL;
2214 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2215 PCDIMMDevice *dimm = PC_DIMM(dev);
2216 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2217 MemoryRegion *mr = ddc->get_memory_region(dimm);
2218 uint64_t align = memory_region_get_alignment(mr);
2219 uint64_t size = memory_region_size(mr);
2220 uint64_t addr;
2221
2222 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2223 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2224 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2225 goto out;
2226 }
2227
2228 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2229 if (local_err) {
2230 goto out;
2231 }
2232
2233 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2234 if (local_err) {
2235 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2236 goto out;
2237 }
2238
2239 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2240
2241 out:
2242 error_propagate(errp, local_err);
2243 }
2244
2245 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2246 sPAPRMachineState *spapr)
2247 {
2248 PowerPCCPU *cpu = POWERPC_CPU(cs);
2249 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2250 int id = ppc_get_vcpu_dt_id(cpu);
2251 void *fdt;
2252 int offset, fdt_size;
2253 char *nodename;
2254
2255 fdt = create_device_tree(&fdt_size);
2256 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2257 offset = fdt_add_subnode(fdt, 0, nodename);
2258
2259 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2260 g_free(nodename);
2261
2262 *fdt_offset = offset;
2263 return fdt;
2264 }
2265
2266 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2267 DeviceState *dev, Error **errp)
2268 {
2269 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2270
2271 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2272 int node;
2273
2274 if (!smc->dr_lmb_enabled) {
2275 error_setg(errp, "Memory hotplug not supported for this machine");
2276 return;
2277 }
2278 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2279 if (*errp) {
2280 return;
2281 }
2282 if (node < 0 || node >= MAX_NODES) {
2283 error_setg(errp, "Invaild node %d", node);
2284 return;
2285 }
2286
2287 /*
2288 * Currently PowerPC kernel doesn't allow hot-adding memory to
2289 * memory-less node, but instead will silently add the memory
2290 * to the first node that has some memory. This causes two
2291 * unexpected behaviours for the user.
2292 *
2293 * - Memory gets hotplugged to a different node than what the user
2294 * specified.
2295 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2296 * to memory-less node, a reboot will set things accordingly
2297 * and the previously hotplugged memory now ends in the right node.
2298 * This appears as if some memory moved from one node to another.
2299 *
2300 * So until kernel starts supporting memory hotplug to memory-less
2301 * nodes, just prevent such attempts upfront in QEMU.
2302 */
2303 if (nb_numa_nodes && !numa_info[node].node_mem) {
2304 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2305 node);
2306 return;
2307 }
2308
2309 spapr_memory_plug(hotplug_dev, dev, node, errp);
2310 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2311 spapr_core_plug(hotplug_dev, dev, errp);
2312 }
2313 }
2314
2315 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2316 DeviceState *dev, Error **errp)
2317 {
2318 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2319
2320 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2321 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2322 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2323 if (!mc->query_hotpluggable_cpus) {
2324 error_setg(errp, "CPU hot unplug not supported on this machine");
2325 return;
2326 }
2327 spapr_core_unplug(hotplug_dev, dev, errp);
2328 }
2329 }
2330
2331 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2332 DeviceState *dev, Error **errp)
2333 {
2334 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2335 spapr_core_pre_plug(hotplug_dev, dev, errp);
2336 }
2337 }
2338
2339 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
2340 DeviceState *dev)
2341 {
2342 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2343 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2344 return HOTPLUG_HANDLER(machine);
2345 }
2346 return NULL;
2347 }
2348
2349 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2350 {
2351 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2352 * socket means much for the paravirtualized PAPR platform) */
2353 return cpu_index / smp_threads / smp_cores;
2354 }
2355
2356 static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
2357 {
2358 int i;
2359 HotpluggableCPUList *head = NULL;
2360 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2361 int spapr_max_cores = max_cpus / smp_threads;
2362
2363 for (i = 0; i < spapr_max_cores; i++) {
2364 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
2365 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
2366 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
2367
2368 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
2369 cpu_item->vcpus_count = smp_threads;
2370 cpu_props->has_core_id = true;
2371 cpu_props->core_id = i * smp_threads;
2372 /* TODO: add 'has_node/node' here to describe
2373 to which node core belongs */
2374
2375 cpu_item->props = cpu_props;
2376 if (spapr->cores[i]) {
2377 cpu_item->has_qom_path = true;
2378 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
2379 }
2380 list_item->value = cpu_item;
2381 list_item->next = head;
2382 head = list_item;
2383 }
2384 return head;
2385 }
2386
2387 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
2388 uint64_t *buid, hwaddr *pio,
2389 hwaddr *mmio32, hwaddr *mmio64,
2390 unsigned n_dma, uint32_t *liobns, Error **errp)
2391 {
2392 /*
2393 * New-style PHB window placement.
2394 *
2395 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
2396 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
2397 * windows.
2398 *
2399 * Some guest kernels can't work with MMIO windows above 1<<46
2400 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
2401 *
2402 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
2403 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
2404 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
2405 * 1TiB 64-bit MMIO windows for each PHB.
2406 */
2407 const uint64_t base_buid = 0x800000020000000ULL;
2408 const int max_phbs =
2409 (SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / SPAPR_PCI_MEM64_WIN_SIZE - 1;
2410 int i;
2411
2412 /* Sanity check natural alignments */
2413 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2414 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2415 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
2416 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
2417 /* Sanity check bounds */
2418 QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_IO_WIN_SIZE) > SPAPR_PCI_MEM32_WIN_SIZE);
2419 QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_MEM32_WIN_SIZE) > SPAPR_PCI_MEM64_WIN_SIZE);
2420
2421 if (index >= max_phbs) {
2422 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
2423 max_phbs - 1);
2424 return;
2425 }
2426
2427 *buid = base_buid + index;
2428 for (i = 0; i < n_dma; ++i) {
2429 liobns[i] = SPAPR_PCI_LIOBN(index, i);
2430 }
2431
2432 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
2433 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
2434 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
2435 }
2436
2437 static void spapr_machine_class_init(ObjectClass *oc, void *data)
2438 {
2439 MachineClass *mc = MACHINE_CLASS(oc);
2440 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2441 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2442 NMIClass *nc = NMI_CLASS(oc);
2443 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2444
2445 mc->desc = "pSeries Logical Partition (PAPR compliant)";
2446
2447 /*
2448 * We set up the default / latest behaviour here. The class_init
2449 * functions for the specific versioned machine types can override
2450 * these details for backwards compatibility
2451 */
2452 mc->init = ppc_spapr_init;
2453 mc->reset = ppc_spapr_reset;
2454 mc->block_default_type = IF_SCSI;
2455 mc->max_cpus = 255;
2456 mc->no_parallel = 1;
2457 mc->default_boot_order = "";
2458 mc->default_ram_size = 512 * M_BYTE;
2459 mc->kvm_type = spapr_kvm_type;
2460 mc->has_dynamic_sysbus = true;
2461 mc->pci_allow_0_address = true;
2462 mc->get_hotplug_handler = spapr_get_hotplug_handler;
2463 hc->pre_plug = spapr_machine_device_pre_plug;
2464 hc->plug = spapr_machine_device_plug;
2465 hc->unplug = spapr_machine_device_unplug;
2466 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2467
2468 smc->dr_lmb_enabled = true;
2469 smc->tcg_default_cpu = "POWER8";
2470 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus;
2471 fwc->get_dev_path = spapr_get_fw_dev_path;
2472 nc->nmi_monitor_handler = spapr_nmi;
2473 smc->phb_placement = spapr_phb_placement;
2474 }
2475
2476 static const TypeInfo spapr_machine_info = {
2477 .name = TYPE_SPAPR_MACHINE,
2478 .parent = TYPE_MACHINE,
2479 .abstract = true,
2480 .instance_size = sizeof(sPAPRMachineState),
2481 .instance_init = spapr_machine_initfn,
2482 .instance_finalize = spapr_machine_finalizefn,
2483 .class_size = sizeof(sPAPRMachineClass),
2484 .class_init = spapr_machine_class_init,
2485 .interfaces = (InterfaceInfo[]) {
2486 { TYPE_FW_PATH_PROVIDER },
2487 { TYPE_NMI },
2488 { TYPE_HOTPLUG_HANDLER },
2489 { }
2490 },
2491 };
2492
2493 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
2494 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2495 void *data) \
2496 { \
2497 MachineClass *mc = MACHINE_CLASS(oc); \
2498 spapr_machine_##suffix##_class_options(mc); \
2499 if (latest) { \
2500 mc->alias = "pseries"; \
2501 mc->is_default = 1; \
2502 } \
2503 } \
2504 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2505 { \
2506 MachineState *machine = MACHINE(obj); \
2507 spapr_machine_##suffix##_instance_options(machine); \
2508 } \
2509 static const TypeInfo spapr_machine_##suffix##_info = { \
2510 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2511 .parent = TYPE_SPAPR_MACHINE, \
2512 .class_init = spapr_machine_##suffix##_class_init, \
2513 .instance_init = spapr_machine_##suffix##_instance_init, \
2514 }; \
2515 static void spapr_machine_register_##suffix(void) \
2516 { \
2517 type_register(&spapr_machine_##suffix##_info); \
2518 } \
2519 type_init(spapr_machine_register_##suffix)
2520
2521 /*
2522 * pseries-2.8
2523 */
2524 static void spapr_machine_2_8_instance_options(MachineState *machine)
2525 {
2526 }
2527
2528 static void spapr_machine_2_8_class_options(MachineClass *mc)
2529 {
2530 /* Defaults for the latest behaviour inherited from the base class */
2531 }
2532
2533 DEFINE_SPAPR_MACHINE(2_8, "2.8", true);
2534
2535 /*
2536 * pseries-2.7
2537 */
2538 #define SPAPR_COMPAT_2_7 \
2539 HW_COMPAT_2_7 \
2540 { \
2541 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
2542 .property = "mem_win_size", \
2543 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
2544 }, \
2545 { \
2546 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
2547 .property = "mem64_win_size", \
2548 .value = "0", \
2549 },
2550
2551 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
2552 uint64_t *buid, hwaddr *pio,
2553 hwaddr *mmio32, hwaddr *mmio64,
2554 unsigned n_dma, uint32_t *liobns, Error **errp)
2555 {
2556 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
2557 const uint64_t base_buid = 0x800000020000000ULL;
2558 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
2559 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
2560 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
2561 const uint32_t max_index = 255;
2562 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
2563
2564 uint64_t ram_top = MACHINE(spapr)->ram_size;
2565 hwaddr phb0_base, phb_base;
2566 int i;
2567
2568 /* Do we have hotpluggable memory? */
2569 if (MACHINE(spapr)->maxram_size > ram_top) {
2570 /* Can't just use maxram_size, because there may be an
2571 * alignment gap between normal and hotpluggable memory
2572 * regions */
2573 ram_top = spapr->hotplug_memory.base +
2574 memory_region_size(&spapr->hotplug_memory.mr);
2575 }
2576
2577 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
2578
2579 if (index > max_index) {
2580 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
2581 max_index);
2582 return;
2583 }
2584
2585 *buid = base_buid + index;
2586 for (i = 0; i < n_dma; ++i) {
2587 liobns[i] = SPAPR_PCI_LIOBN(index, i);
2588 }
2589
2590 phb_base = phb0_base + index * phb_spacing;
2591 *pio = phb_base + pio_offset;
2592 *mmio32 = phb_base + mmio_offset;
2593 /*
2594 * We don't set the 64-bit MMIO window, relying on the PHB's
2595 * fallback behaviour of automatically splitting a large "32-bit"
2596 * window into contiguous 32-bit and 64-bit windows
2597 */
2598 }
2599
2600 static void spapr_machine_2_7_instance_options(MachineState *machine)
2601 {
2602 spapr_machine_2_8_instance_options(machine);
2603 }
2604
2605 static void spapr_machine_2_7_class_options(MachineClass *mc)
2606 {
2607 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2608
2609 spapr_machine_2_8_class_options(mc);
2610 smc->tcg_default_cpu = "POWER7";
2611 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
2612 smc->phb_placement = phb_placement_2_7;
2613 }
2614
2615 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
2616
2617 /*
2618 * pseries-2.6
2619 */
2620 #define SPAPR_COMPAT_2_6 \
2621 HW_COMPAT_2_6 \
2622 { \
2623 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2624 .property = "ddw",\
2625 .value = stringify(off),\
2626 },
2627
2628 static void spapr_machine_2_6_instance_options(MachineState *machine)
2629 {
2630 spapr_machine_2_7_instance_options(machine);
2631 }
2632
2633 static void spapr_machine_2_6_class_options(MachineClass *mc)
2634 {
2635 spapr_machine_2_7_class_options(mc);
2636 mc->query_hotpluggable_cpus = NULL;
2637 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
2638 }
2639
2640 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
2641
2642 /*
2643 * pseries-2.5
2644 */
2645 #define SPAPR_COMPAT_2_5 \
2646 HW_COMPAT_2_5 \
2647 { \
2648 .driver = "spapr-vlan", \
2649 .property = "use-rx-buffer-pools", \
2650 .value = "off", \
2651 },
2652
2653 static void spapr_machine_2_5_instance_options(MachineState *machine)
2654 {
2655 spapr_machine_2_6_instance_options(machine);
2656 }
2657
2658 static void spapr_machine_2_5_class_options(MachineClass *mc)
2659 {
2660 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2661
2662 spapr_machine_2_6_class_options(mc);
2663 smc->use_ohci_by_default = true;
2664 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
2665 }
2666
2667 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
2668
2669 /*
2670 * pseries-2.4
2671 */
2672 #define SPAPR_COMPAT_2_4 \
2673 HW_COMPAT_2_4
2674
2675 static void spapr_machine_2_4_instance_options(MachineState *machine)
2676 {
2677 spapr_machine_2_5_instance_options(machine);
2678 }
2679
2680 static void spapr_machine_2_4_class_options(MachineClass *mc)
2681 {
2682 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2683
2684 spapr_machine_2_5_class_options(mc);
2685 smc->dr_lmb_enabled = false;
2686 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
2687 }
2688
2689 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
2690
2691 /*
2692 * pseries-2.3
2693 */
2694 #define SPAPR_COMPAT_2_3 \
2695 HW_COMPAT_2_3 \
2696 {\
2697 .driver = "spapr-pci-host-bridge",\
2698 .property = "dynamic-reconfiguration",\
2699 .value = "off",\
2700 },
2701
2702 static void spapr_machine_2_3_instance_options(MachineState *machine)
2703 {
2704 spapr_machine_2_4_instance_options(machine);
2705 savevm_skip_section_footers();
2706 global_state_set_optional();
2707 savevm_skip_configuration();
2708 }
2709
2710 static void spapr_machine_2_3_class_options(MachineClass *mc)
2711 {
2712 spapr_machine_2_4_class_options(mc);
2713 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
2714 }
2715 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
2716
2717 /*
2718 * pseries-2.2
2719 */
2720
2721 #define SPAPR_COMPAT_2_2 \
2722 HW_COMPAT_2_2 \
2723 {\
2724 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2725 .property = "mem_win_size",\
2726 .value = "0x20000000",\
2727 },
2728
2729 static void spapr_machine_2_2_instance_options(MachineState *machine)
2730 {
2731 spapr_machine_2_3_instance_options(machine);
2732 machine->suppress_vmdesc = true;
2733 }
2734
2735 static void spapr_machine_2_2_class_options(MachineClass *mc)
2736 {
2737 spapr_machine_2_3_class_options(mc);
2738 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
2739 }
2740 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
2741
2742 /*
2743 * pseries-2.1
2744 */
2745 #define SPAPR_COMPAT_2_1 \
2746 HW_COMPAT_2_1
2747
2748 static void spapr_machine_2_1_instance_options(MachineState *machine)
2749 {
2750 spapr_machine_2_2_instance_options(machine);
2751 }
2752
2753 static void spapr_machine_2_1_class_options(MachineClass *mc)
2754 {
2755 spapr_machine_2_2_class_options(mc);
2756 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
2757 }
2758 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
2759
2760 static void spapr_machine_register_types(void)
2761 {
2762 type_register_static(&spapr_machine_info);
2763 }
2764
2765 type_init(spapr_machine_register_types)
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