hw/ppc/spapr_cpu_core.c

   1 /*
   2  * sPAPR CPU core device, acts as container of CPU thread devices.
   3  *
   4  * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/cpu/core.h"
  12 #include "hw/ppc/spapr_cpu_core.h"
  13 #include "hw/qdev-properties.h"
  14 #include "migration/vmstate.h"
  15 #include "target/ppc/cpu.h"
  16 #include "hw/ppc/spapr.h"
  17 #include "hw/boards.h"
  18 #include "qapi/error.h"
  19 #include "sysemu/cpus.h"
  20 #include "sysemu/kvm.h"
  21 #include "target/ppc/kvm_ppc.h"
  22 #include "hw/ppc/ppc.h"
  23 #include "target/ppc/mmu-hash64.h"
  24 #include "sysemu/numa.h"
  25 #include "sysemu/reset.h"
  26 #include "sysemu/hw_accel.h"
  27 #include "qemu/error-report.h"
  28
  29 static void spapr_cpu_reset(void *opaque)
  30 {
  31     PowerPCCPU *cpu = opaque;
  32     CPUState *cs = CPU(cpu);
  33     CPUPPCState *env = &cpu->env;
  34     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  35     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
  36     target_ulong lpcr;
  37
  38     cpu_reset(cs);
  39
  40     /* All CPUs start halted.  CPU0 is unhalted from the machine level
  41      * reset code and the rest are explicitly started up by the guest
  42      * using an RTAS call */
  43     cs->halted = 1;
  44
  45     /* Set compatibility mode to match the boot CPU, which was either set
  46      * by the machine reset code or by CAS. This should never fail.
  47      */
  48     ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);
  49
  50     env->spr[SPR_HIOR] = 0;
  51
  52     lpcr = env->spr[SPR_LPCR];
  53
  54     /* Set emulated LPCR to not send interrupts to hypervisor. Note that
  55      * under KVM, the actual HW LPCR will be set differently by KVM itself,
  56      * the settings below ensure proper operations with TCG in absence of
  57      * a real hypervisor.
  58      *
  59      * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
  60      * real mode accesses, which thankfully defaults to 0 and isn't
  61      * accessible in guest mode.
  62      *
  63      * Disable Power-saving mode Exit Cause exceptions for the CPU, so
  64      * we don't get spurious wakups before an RTAS start-cpu call.
  65      * For the same reason, set PSSCR_EC.
  66      */
  67     lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
  68     lpcr |= LPCR_LPES0 | LPCR_LPES1;
  69     env->spr[SPR_PSSCR] |= PSSCR_EC;
  70
  71     /* Set RMLS to the max (ie, 16G) */
  72     lpcr &= ~LPCR_RMLS;
  73     lpcr |= 1ull << LPCR_RMLS_SHIFT;
  74
  75     ppc_store_lpcr(cpu, lpcr);
  76
  77     /* Set a full AMOR so guest can use the AMR as it sees fit */
  78     env->spr[SPR_AMOR] = 0xffffffffffffffffull;
  79
  80     spapr_cpu->vpa_addr = 0;
  81     spapr_cpu->slb_shadow_addr = 0;
  82     spapr_cpu->slb_shadow_size = 0;
  83     spapr_cpu->dtl_addr = 0;
  84     spapr_cpu->dtl_size = 0;
  85
  86     spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu);
  87
  88     kvm_check_mmu(cpu, &error_fatal);
  89 }
  90
  91 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
  92 {
  93     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  94     CPUPPCState *env = &cpu->env;
  95
  96     env->nip = nip;
  97     env->gpr[3] = r3;
  98     kvmppc_set_reg_ppc_online(cpu, 1);
  99     CPU(cpu)->halted = 0;
 100     /* Enable Power-saving mode Exit Cause exceptions */
 101     ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
 102 }
 103
 104 /*
 105  * Return the sPAPR CPU core type for @model which essentially is the CPU
 106  * model specified with -cpu cmdline option.
 107  */
 108 const char *spapr_get_cpu_core_type(const char *cpu_type)
 109 {
 110     int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
 111     char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
 112                                       len, cpu_type);
 113     ObjectClass *oc = object_class_by_name(core_type);
 114
 115     g_free(core_type);
 116     if (!oc) {
 117         return NULL;
 118     }
 119
 120     return object_class_get_name(oc);
 121 }
 122
 123 static bool slb_shadow_needed(void *opaque)
 124 {
 125     SpaprCpuState *spapr_cpu = opaque;
 126
 127     return spapr_cpu->slb_shadow_addr != 0;
 128 }
 129
 130 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
 131     .name = "spapr_cpu/vpa/slb_shadow",
 132     .version_id = 1,
 133     .minimum_version_id = 1,
 134     .needed = slb_shadow_needed,
 135     .fields = (VMStateField[]) {
 136         VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState),
 137         VMSTATE_UINT64(slb_shadow_size, SpaprCpuState),
 138         VMSTATE_END_OF_LIST()
 139     }
 140 };
 141
 142 static bool dtl_needed(void *opaque)
 143 {
 144     SpaprCpuState *spapr_cpu = opaque;
 145
 146     return spapr_cpu->dtl_addr != 0;
 147 }
 148
 149 static const VMStateDescription vmstate_spapr_cpu_dtl = {
 150     .name = "spapr_cpu/vpa/dtl",
 151     .version_id = 1,
 152     .minimum_version_id = 1,
 153     .needed = dtl_needed,
 154     .fields = (VMStateField[]) {
 155         VMSTATE_UINT64(dtl_addr, SpaprCpuState),
 156         VMSTATE_UINT64(dtl_size, SpaprCpuState),
 157         VMSTATE_END_OF_LIST()
 158     }
 159 };
 160
 161 static bool vpa_needed(void *opaque)
 162 {
 163     SpaprCpuState *spapr_cpu = opaque;
 164
 165     return spapr_cpu->vpa_addr != 0;
 166 }
 167
 168 static const VMStateDescription vmstate_spapr_cpu_vpa = {
 169     .name = "spapr_cpu/vpa",
 170     .version_id = 1,
 171     .minimum_version_id = 1,
 172     .needed = vpa_needed,
 173     .fields = (VMStateField[]) {
 174         VMSTATE_UINT64(vpa_addr, SpaprCpuState),
 175         VMSTATE_END_OF_LIST()
 176     },
 177     .subsections = (const VMStateDescription * []) {
 178         &vmstate_spapr_cpu_slb_shadow,
 179         &vmstate_spapr_cpu_dtl,
 180         NULL
 181     }
 182 };
 183
 184 static const VMStateDescription vmstate_spapr_cpu_state = {
 185     .name = "spapr_cpu",
 186     .version_id = 1,
 187     .minimum_version_id = 1,
 188     .fields = (VMStateField[]) {
 189         VMSTATE_END_OF_LIST()
 190     },
 191     .subsections = (const VMStateDescription * []) {
 192         &vmstate_spapr_cpu_vpa,
 193         NULL
 194     }
 195 };
 196
 197 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
 198 {
 199     if (!sc->pre_3_0_migration) {
 200         vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
 201     }
 202     qemu_unregister_reset(spapr_cpu_reset, cpu);
 203     if (spapr_cpu_state(cpu)->icp) {
 204         object_unparent(OBJECT(spapr_cpu_state(cpu)->icp));
 205     }
 206     if (spapr_cpu_state(cpu)->tctx) {
 207         object_unparent(OBJECT(spapr_cpu_state(cpu)->tctx));
 208     }
 209     cpu_remove_sync(CPU(cpu));
 210     object_unparent(OBJECT(cpu));
 211 }
 212
 213 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp)
 214 {
 215     SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 216     CPUCore *cc = CPU_CORE(dev);
 217     int i;
 218
 219     for (i = 0; i < cc->nr_threads; i++) {
 220         spapr_unrealize_vcpu(sc->threads[i], sc);
 221     }
 222     g_free(sc->threads);
 223 }
 224
 225 static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
 226                                SpaprCpuCore *sc, Error **errp)
 227 {
 228     CPUPPCState *env = &cpu->env;
 229     CPUState *cs = CPU(cpu);
 230     Error *local_err = NULL;
 231
 232     object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
 233     if (local_err) {
 234         goto error;
 235     }
 236
 237     /* Set time-base frequency to 512 MHz */
 238     cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
 239
 240     cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
 241     kvmppc_set_papr(cpu);
 242
 243     qemu_register_reset(spapr_cpu_reset, cpu);
 244     spapr_cpu_reset(cpu);
 245
 246     spapr->irq->cpu_intc_create(spapr, cpu, &local_err);
 247     if (local_err) {
 248         goto error_unregister;
 249     }
 250
 251     if (!sc->pre_3_0_migration) {
 252         vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
 253                          cpu->machine_data);
 254     }
 255
 256     return;
 257
 258 error_unregister:
 259     qemu_unregister_reset(spapr_cpu_reset, cpu);
 260     cpu_remove_sync(CPU(cpu));
 261 error:
 262     error_propagate(errp, local_err);
 263 }
 264
 265 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
 266 {
 267     SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
 268     CPUCore *cc = CPU_CORE(sc);
 269     Object *obj;
 270     char *id;
 271     CPUState *cs;
 272     PowerPCCPU *cpu;
 273     Error *local_err = NULL;
 274
 275     obj = object_new(scc->cpu_type);
 276
 277     cs = CPU(obj);
 278     cpu = POWERPC_CPU(obj);
 279     cs->cpu_index = cc->core_id + i;
 280     spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
 281     if (local_err) {
 282         goto err;
 283     }
 284
 285     cpu->node_id = sc->node_id;
 286
 287     id = g_strdup_printf("thread[%d]", i);
 288     object_property_add_child(OBJECT(sc), id, obj, &local_err);
 289     g_free(id);
 290     if (local_err) {
 291         goto err;
 292     }
 293
 294     cpu->machine_data = g_new0(SpaprCpuState, 1);
 295
 296     object_unref(obj);
 297     return cpu;
 298
 299 err:
 300     object_unref(obj);
 301     error_propagate(errp, local_err);
 302     return NULL;
 303 }
 304
 305 static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
 306 {
 307     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 308
 309     cpu->machine_data = NULL;
 310     g_free(spapr_cpu);
 311     object_unparent(OBJECT(cpu));
 312 }
 313
 314 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
 315 {
 316     /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
 317      * tries to add a sPAPR CPU core to a non-pseries machine.
 318      */
 319     SpaprMachineState *spapr =
 320         (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
 321                                                   TYPE_SPAPR_MACHINE);
 322     SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 323     CPUCore *cc = CPU_CORE(OBJECT(dev));
 324     Error *local_err = NULL;
 325     int i, j;
 326
 327     if (!spapr) {
 328         error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
 329         return;
 330     }
 331
 332     sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
 333     for (i = 0; i < cc->nr_threads; i++) {
 334         sc->threads[i] = spapr_create_vcpu(sc, i, &local_err);
 335         if (local_err) {
 336             goto err;
 337         }
 338     }
 339
 340     for (j = 0; j < cc->nr_threads; j++) {
 341         spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err);
 342         if (local_err) {
 343             goto err_unrealize;
 344         }
 345     }
 346     return;
 347
 348 err_unrealize:
 349     while (--j >= 0) {
 350         spapr_unrealize_vcpu(sc->threads[j], sc);
 351     }
 352 err:
 353     while (--i >= 0) {
 354         spapr_delete_vcpu(sc->threads[i], sc);
 355     }
 356     g_free(sc->threads);
 357     error_propagate(errp, local_err);
 358 }
 359
 360 static Property spapr_cpu_core_properties[] = {
 361     DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
 362     DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration,
 363                      false),
 364     DEFINE_PROP_END_OF_LIST()
 365 };
 366
 367 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
 368 {
 369     DeviceClass *dc = DEVICE_CLASS(oc);
 370     SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
 371
 372     dc->realize = spapr_cpu_core_realize;
 373     dc->unrealize = spapr_cpu_core_unrealize;
 374     dc->props = spapr_cpu_core_properties;
 375     scc->cpu_type = data;
 376 }
 377
 378 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
 379     {                                                   \
 380         .parent = TYPE_SPAPR_CPU_CORE,                  \
 381         .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
 382         .class_init = spapr_cpu_core_class_init,        \
 383         .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model),    \
 384     }
 385
 386 static const TypeInfo spapr_cpu_core_type_infos[] = {
 387     {
 388         .name = TYPE_SPAPR_CPU_CORE,
 389         .parent = TYPE_CPU_CORE,
 390         .abstract = true,
 391         .instance_size = sizeof(SpaprCpuCore),
 392         .class_size = sizeof(SpaprCpuCoreClass),
 393     },
 394     DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
 395     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
 396     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
 397     DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
 398     DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
 399     DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
 400     DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
 401     DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
 402     DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
 403     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
 404     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
 405 #ifdef CONFIG_KVM
 406     DEFINE_SPAPR_CPU_CORE_TYPE("host"),
 407 #endif
 408 };
 409
 410 DEFINE_TYPES(spapr_cpu_core_type_infos)