2 * sPAPR CPU core device, acts as container of CPU thread devices.
4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
11 #include "hw/cpu/core.h"
12 #include "hw/ppc/spapr_cpu_core.h"
13 #include "hw/qdev-properties.h"
14 #include "migration/vmstate.h"
15 #include "target/ppc/cpu.h"
16 #include "hw/ppc/spapr.h"
17 #include "qapi/error.h"
18 #include "sysemu/cpus.h"
19 #include "sysemu/kvm.h"
20 #include "target/ppc/kvm_ppc.h"
21 #include "hw/ppc/ppc.h"
22 #include "target/ppc/mmu-hash64.h"
23 #include "target/ppc/power8-pmu.h"
24 #include "sysemu/numa.h"
25 #include "sysemu/reset.h"
26 #include "sysemu/hw_accel.h"
27 #include "qemu/error-report.h"
29 static void spapr_reset_vcpu(PowerPCCPU
*cpu
)
31 CPUState
*cs
= CPU(cpu
);
32 CPUPPCState
*env
= &cpu
->env
;
33 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
34 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
36 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
41 * "PowerPC Processor binding to IEEE 1275" defines the initial MSR state
42 * as 32bit (MSR_SF=0) in "8.2.1. Initial Register Values".
44 env
->msr
&= ~(1ULL << MSR_SF
);
45 env
->spr
[SPR_HIOR
] = 0;
47 lpcr
= env
->spr
[SPR_LPCR
];
49 /* Set emulated LPCR to not send interrupts to hypervisor. Note that
50 * under KVM, the actual HW LPCR will be set differently by KVM itself,
51 * the settings below ensure proper operations with TCG in absence of
54 * Disable Power-saving mode Exit Cause exceptions for the CPU, so
55 * we don't get spurious wakups before an RTAS start-cpu call.
56 * For the same reason, set PSSCR_EC.
58 lpcr
&= ~(LPCR_VPM1
| LPCR_ISL
| LPCR_KBV
| pcc
->lpcr_pm
);
59 lpcr
|= LPCR_LPES0
| LPCR_LPES1
;
60 env
->spr
[SPR_PSSCR
] |= PSSCR_EC
;
62 ppc_store_lpcr(cpu
, lpcr
);
64 /* Set a full AMOR so guest can use the AMR as it sees fit */
65 env
->spr
[SPR_AMOR
] = 0xffffffffffffffffull
;
67 spapr_cpu
->vpa_addr
= 0;
68 spapr_cpu
->slb_shadow_addr
= 0;
69 spapr_cpu
->slb_shadow_size
= 0;
70 spapr_cpu
->dtl_addr
= 0;
71 spapr_cpu
->dtl_size
= 0;
73 spapr_caps_cpu_apply(spapr
, cpu
);
75 kvm_check_mmu(cpu
, &error_fatal
);
77 cpu_ppc_tb_reset(env
);
79 spapr_irq_cpu_intc_reset(spapr
, cpu
);
82 void spapr_cpu_set_entry_state(PowerPCCPU
*cpu
, target_ulong nip
,
83 target_ulong r1
, target_ulong r3
,
86 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
87 CPUPPCState
*env
= &cpu
->env
;
93 kvmppc_set_reg_ppc_online(cpu
, 1);
95 /* Enable Power-saving mode Exit Cause exceptions */
96 ppc_store_lpcr(cpu
, env
->spr
[SPR_LPCR
] | pcc
->lpcr_pm
);
100 * Return the sPAPR CPU core type for @model which essentially is the CPU
101 * model specified with -cpu cmdline option.
103 const char *spapr_get_cpu_core_type(const char *cpu_type
)
105 int len
= strlen(cpu_type
) - strlen(POWERPC_CPU_TYPE_SUFFIX
);
106 char *core_type
= g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
108 ObjectClass
*oc
= object_class_by_name(core_type
);
115 return object_class_get_name(oc
);
118 static bool slb_shadow_needed(void *opaque
)
120 SpaprCpuState
*spapr_cpu
= opaque
;
122 return spapr_cpu
->slb_shadow_addr
!= 0;
125 static const VMStateDescription vmstate_spapr_cpu_slb_shadow
= {
126 .name
= "spapr_cpu/vpa/slb_shadow",
128 .minimum_version_id
= 1,
129 .needed
= slb_shadow_needed
,
130 .fields
= (VMStateField
[]) {
131 VMSTATE_UINT64(slb_shadow_addr
, SpaprCpuState
),
132 VMSTATE_UINT64(slb_shadow_size
, SpaprCpuState
),
133 VMSTATE_END_OF_LIST()
137 static bool dtl_needed(void *opaque
)
139 SpaprCpuState
*spapr_cpu
= opaque
;
141 return spapr_cpu
->dtl_addr
!= 0;
144 static const VMStateDescription vmstate_spapr_cpu_dtl
= {
145 .name
= "spapr_cpu/vpa/dtl",
147 .minimum_version_id
= 1,
148 .needed
= dtl_needed
,
149 .fields
= (VMStateField
[]) {
150 VMSTATE_UINT64(dtl_addr
, SpaprCpuState
),
151 VMSTATE_UINT64(dtl_size
, SpaprCpuState
),
152 VMSTATE_END_OF_LIST()
156 static bool vpa_needed(void *opaque
)
158 SpaprCpuState
*spapr_cpu
= opaque
;
160 return spapr_cpu
->vpa_addr
!= 0;
163 static const VMStateDescription vmstate_spapr_cpu_vpa
= {
164 .name
= "spapr_cpu/vpa",
166 .minimum_version_id
= 1,
167 .needed
= vpa_needed
,
168 .fields
= (VMStateField
[]) {
169 VMSTATE_UINT64(vpa_addr
, SpaprCpuState
),
170 VMSTATE_END_OF_LIST()
172 .subsections
= (const VMStateDescription
* []) {
173 &vmstate_spapr_cpu_slb_shadow
,
174 &vmstate_spapr_cpu_dtl
,
179 static const VMStateDescription vmstate_spapr_cpu_state
= {
182 .minimum_version_id
= 1,
183 .fields
= (VMStateField
[]) {
184 VMSTATE_END_OF_LIST()
186 .subsections
= (const VMStateDescription
* []) {
187 &vmstate_spapr_cpu_vpa
,
192 static void spapr_unrealize_vcpu(PowerPCCPU
*cpu
, SpaprCpuCore
*sc
)
194 CPUPPCState
*env
= &cpu
->env
;
196 if (!sc
->pre_3_0_migration
) {
197 vmstate_unregister(NULL
, &vmstate_spapr_cpu_state
, cpu
->machine_data
);
199 spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu
);
200 cpu_ppc_tb_free(env
);
201 qdev_unrealize(DEVICE(cpu
));
205 * Called when CPUs are hot-plugged.
207 static void spapr_cpu_core_reset(DeviceState
*dev
)
209 CPUCore
*cc
= CPU_CORE(dev
);
210 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(dev
);
213 for (i
= 0; i
< cc
->nr_threads
; i
++) {
214 spapr_reset_vcpu(sc
->threads
[i
]);
219 * Called by the machine reset.
221 static void spapr_cpu_core_reset_handler(void *opaque
)
223 spapr_cpu_core_reset(opaque
);
226 static void spapr_delete_vcpu(PowerPCCPU
*cpu
)
228 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
230 cpu
->machine_data
= NULL
;
232 object_unparent(OBJECT(cpu
));
235 static void spapr_cpu_core_unrealize(DeviceState
*dev
)
237 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
238 CPUCore
*cc
= CPU_CORE(dev
);
241 for (i
= 0; i
< cc
->nr_threads
; i
++) {
242 if (sc
->threads
[i
]) {
244 * Since this we can get here from the error path of
245 * spapr_cpu_core_realize(), make sure we only unrealize
246 * vCPUs that have already been realized.
248 if (object_property_get_bool(OBJECT(sc
->threads
[i
]), "realized",
250 spapr_unrealize_vcpu(sc
->threads
[i
], sc
);
252 spapr_delete_vcpu(sc
->threads
[i
]);
256 qemu_unregister_reset(spapr_cpu_core_reset_handler
, sc
);
259 static bool spapr_realize_vcpu(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
260 SpaprCpuCore
*sc
, int thread_index
, Error
**errp
)
262 CPUPPCState
*env
= &cpu
->env
;
263 CPUState
*cs
= CPU(cpu
);
265 if (!qdev_realize(DEVICE(cpu
), NULL
, errp
)) {
269 cpu_ppc_set_vhyp(cpu
, PPC_VIRTUAL_HYPERVISOR(spapr
));
270 kvmppc_set_papr(cpu
);
272 env
->spr_cb
[SPR_PIR
].default_value
= cs
->cpu_index
;
273 env
->spr_cb
[SPR_TIR
].default_value
= thread_index
;
275 cpu_ppc_set_1lpar(cpu
);
277 /* Set time-base frequency to 512 MHz. vhyp must be set first. */
278 cpu_ppc_tb_init(env
, SPAPR_TIMEBASE_FREQ
);
280 if (spapr_irq_cpu_intc_create(spapr
, cpu
, errp
) < 0) {
281 qdev_unrealize(DEVICE(cpu
));
285 if (!sc
->pre_3_0_migration
) {
286 vmstate_register(NULL
, cs
->cpu_index
, &vmstate_spapr_cpu_state
,
292 static PowerPCCPU
*spapr_create_vcpu(SpaprCpuCore
*sc
, int i
, Error
**errp
)
294 SpaprCpuCoreClass
*scc
= SPAPR_CPU_CORE_GET_CLASS(sc
);
295 CPUCore
*cc
= CPU_CORE(sc
);
296 g_autoptr(Object
) obj
= NULL
;
297 g_autofree
char *id
= NULL
;
301 obj
= object_new(scc
->cpu_type
);
304 cpu
= POWERPC_CPU(obj
);
306 * All CPUs start halted. CPU0 is unhalted from the machine level reset code
307 * and the rest are explicitly started up by the guest using an RTAS call.
309 cs
->start_powered_off
= true;
310 cs
->cpu_index
= cc
->core_id
+ i
;
311 if (!spapr_set_vcpu_id(cpu
, cs
->cpu_index
, errp
)) {
315 cpu
->node_id
= sc
->node_id
;
317 id
= g_strdup_printf("thread[%d]", i
);
318 object_property_add_child(OBJECT(sc
), id
, obj
);
320 cpu
->machine_data
= g_new0(SpaprCpuState
, 1);
325 static void spapr_cpu_core_realize(DeviceState
*dev
, Error
**errp
)
327 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
328 * tries to add a sPAPR CPU core to a non-pseries machine.
330 SpaprMachineState
*spapr
=
331 (SpaprMachineState
*) object_dynamic_cast(qdev_get_machine(),
333 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
334 CPUCore
*cc
= CPU_CORE(OBJECT(dev
));
338 error_setg(errp
, TYPE_SPAPR_CPU_CORE
" needs a pseries machine");
342 qemu_register_reset(spapr_cpu_core_reset_handler
, sc
);
343 sc
->threads
= g_new0(PowerPCCPU
*, cc
->nr_threads
);
344 for (i
= 0; i
< cc
->nr_threads
; i
++) {
345 sc
->threads
[i
] = spapr_create_vcpu(sc
, i
, errp
);
346 if (!sc
->threads
[i
] ||
347 !spapr_realize_vcpu(sc
->threads
[i
], spapr
, sc
, i
, errp
)) {
348 spapr_cpu_core_unrealize(dev
);
354 static Property spapr_cpu_core_properties
[] = {
355 DEFINE_PROP_INT32("node-id", SpaprCpuCore
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
356 DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore
, pre_3_0_migration
,
358 DEFINE_PROP_END_OF_LIST()
361 static void spapr_cpu_core_class_init(ObjectClass
*oc
, void *data
)
363 DeviceClass
*dc
= DEVICE_CLASS(oc
);
364 SpaprCpuCoreClass
*scc
= SPAPR_CPU_CORE_CLASS(oc
);
366 dc
->realize
= spapr_cpu_core_realize
;
367 dc
->unrealize
= spapr_cpu_core_unrealize
;
368 dc
->reset
= spapr_cpu_core_reset
;
369 device_class_set_props(dc
, spapr_cpu_core_properties
);
370 scc
->cpu_type
= data
;
373 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
375 .parent = TYPE_SPAPR_CPU_CORE, \
376 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
377 .class_init = spapr_cpu_core_class_init, \
378 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \
381 static const TypeInfo spapr_cpu_core_type_infos
[] = {
383 .name
= TYPE_SPAPR_CPU_CORE
,
384 .parent
= TYPE_CPU_CORE
,
386 .instance_size
= sizeof(SpaprCpuCore
),
387 .class_size
= sizeof(SpaprCpuCoreClass
),
389 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
390 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
391 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
392 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
393 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
394 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
395 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
396 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
397 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
398 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
399 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
400 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
401 DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"),
402 DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
404 DEFINE_SPAPR_CPU_CORE_TYPE("host"),
408 DEFINE_TYPES(spapr_cpu_core_type_infos
)