hw/ppc/spapr_cpu_core.c

   1 /*
   2  * sPAPR CPU core device, acts as container of CPU thread devices.
   3  *
   4  * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/cpu/core.h"
  12 #include "hw/ppc/spapr_cpu_core.h"
  13 #include "hw/qdev-properties.h"
  14 #include "migration/vmstate.h"
  15 #include "target/ppc/cpu.h"
  16 #include "hw/ppc/spapr.h"
  17 #include "qapi/error.h"
  18 #include "sysemu/cpus.h"
  19 #include "sysemu/kvm.h"
  20 #include "target/ppc/kvm_ppc.h"
  21 #include "hw/ppc/ppc.h"
  22 #include "target/ppc/mmu-hash64.h"
  23 #include "sysemu/numa.h"
  24 #include "sysemu/reset.h"
  25 #include "sysemu/hw_accel.h"
  26 #include "qemu/error-report.h"
  27
  28 static void spapr_reset_vcpu(PowerPCCPU *cpu)
  29 {
  30     CPUState *cs = CPU(cpu);
  31     CPUPPCState *env = &cpu->env;
  32     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  33     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
  34     target_ulong lpcr;
  35     SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
  36
  37     cpu_reset(cs);
  38
  39     /* All CPUs start halted.  CPU0 is unhalted from the machine level
  40      * reset code and the rest are explicitly started up by the guest
  41      * using an RTAS call */
  42     cs->halted = 1;
  43
  44     env->spr[SPR_HIOR] = 0;
  45
  46     lpcr = env->spr[SPR_LPCR];
  47
  48     /* Set emulated LPCR to not send interrupts to hypervisor. Note that
  49      * under KVM, the actual HW LPCR will be set differently by KVM itself,
  50      * the settings below ensure proper operations with TCG in absence of
  51      * a real hypervisor.
  52      *
  53      * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
  54      * real mode accesses, which thankfully defaults to 0 and isn't
  55      * accessible in guest mode.
  56      *
  57      * Disable Power-saving mode Exit Cause exceptions for the CPU, so
  58      * we don't get spurious wakups before an RTAS start-cpu call.
  59      * For the same reason, set PSSCR_EC.
  60      */
  61     lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
  62     lpcr |= LPCR_LPES0 | LPCR_LPES1;
  63     env->spr[SPR_PSSCR] |= PSSCR_EC;
  64
  65     /* Set RMLS to the max (ie, 16G) */
  66     lpcr &= ~LPCR_RMLS;
  67     lpcr |= 1ull << LPCR_RMLS_SHIFT;
  68
  69     ppc_store_lpcr(cpu, lpcr);
  70
  71     /* Set a full AMOR so guest can use the AMR as it sees fit */
  72     env->spr[SPR_AMOR] = 0xffffffffffffffffull;
  73
  74     spapr_cpu->vpa_addr = 0;
  75     spapr_cpu->slb_shadow_addr = 0;
  76     spapr_cpu->slb_shadow_size = 0;
  77     spapr_cpu->dtl_addr = 0;
  78     spapr_cpu->dtl_size = 0;
  79
  80     spapr_caps_cpu_apply(spapr, cpu);
  81
  82     kvm_check_mmu(cpu, &error_fatal);
  83
  84     spapr_irq_cpu_intc_reset(spapr, cpu);
  85 }
  86
  87 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
  88 {
  89     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  90     CPUPPCState *env = &cpu->env;
  91
  92     env->nip = nip;
  93     env->gpr[3] = r3;
  94     kvmppc_set_reg_ppc_online(cpu, 1);
  95     CPU(cpu)->halted = 0;
  96     /* Enable Power-saving mode Exit Cause exceptions */
  97     ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
  98 }
  99
 100 /*
 101  * Return the sPAPR CPU core type for @model which essentially is the CPU
 102  * model specified with -cpu cmdline option.
 103  */
 104 const char *spapr_get_cpu_core_type(const char *cpu_type)
 105 {
 106     int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
 107     char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
 108                                       len, cpu_type);
 109     ObjectClass *oc = object_class_by_name(core_type);
 110
 111     g_free(core_type);
 112     if (!oc) {
 113         return NULL;
 114     }
 115
 116     return object_class_get_name(oc);
 117 }
 118
 119 static bool slb_shadow_needed(void *opaque)
 120 {
 121     SpaprCpuState *spapr_cpu = opaque;
 122
 123     return spapr_cpu->slb_shadow_addr != 0;
 124 }
 125
 126 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
 127     .name = "spapr_cpu/vpa/slb_shadow",
 128     .version_id = 1,
 129     .minimum_version_id = 1,
 130     .needed = slb_shadow_needed,
 131     .fields = (VMStateField[]) {
 132         VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState),
 133         VMSTATE_UINT64(slb_shadow_size, SpaprCpuState),
 134         VMSTATE_END_OF_LIST()
 135     }
 136 };
 137
 138 static bool dtl_needed(void *opaque)
 139 {
 140     SpaprCpuState *spapr_cpu = opaque;
 141
 142     return spapr_cpu->dtl_addr != 0;
 143 }
 144
 145 static const VMStateDescription vmstate_spapr_cpu_dtl = {
 146     .name = "spapr_cpu/vpa/dtl",
 147     .version_id = 1,
 148     .minimum_version_id = 1,
 149     .needed = dtl_needed,
 150     .fields = (VMStateField[]) {
 151         VMSTATE_UINT64(dtl_addr, SpaprCpuState),
 152         VMSTATE_UINT64(dtl_size, SpaprCpuState),
 153         VMSTATE_END_OF_LIST()
 154     }
 155 };
 156
 157 static bool vpa_needed(void *opaque)
 158 {
 159     SpaprCpuState *spapr_cpu = opaque;
 160
 161     return spapr_cpu->vpa_addr != 0;
 162 }
 163
 164 static const VMStateDescription vmstate_spapr_cpu_vpa = {
 165     .name = "spapr_cpu/vpa",
 166     .version_id = 1,
 167     .minimum_version_id = 1,
 168     .needed = vpa_needed,
 169     .fields = (VMStateField[]) {
 170         VMSTATE_UINT64(vpa_addr, SpaprCpuState),
 171         VMSTATE_END_OF_LIST()
 172     },
 173     .subsections = (const VMStateDescription * []) {
 174         &vmstate_spapr_cpu_slb_shadow,
 175         &vmstate_spapr_cpu_dtl,
 176         NULL
 177     }
 178 };
 179
 180 static const VMStateDescription vmstate_spapr_cpu_state = {
 181     .name = "spapr_cpu",
 182     .version_id = 1,
 183     .minimum_version_id = 1,
 184     .fields = (VMStateField[]) {
 185         VMSTATE_END_OF_LIST()
 186     },
 187     .subsections = (const VMStateDescription * []) {
 188         &vmstate_spapr_cpu_vpa,
 189         NULL
 190     }
 191 };
 192
 193 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
 194 {
 195     if (!sc->pre_3_0_migration) {
 196         vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
 197     }
 198     if (spapr_cpu_state(cpu)->icp) {
 199         object_unparent(OBJECT(spapr_cpu_state(cpu)->icp));
 200     }
 201     if (spapr_cpu_state(cpu)->tctx) {
 202         object_unparent(OBJECT(spapr_cpu_state(cpu)->tctx));
 203     }
 204     cpu_remove_sync(CPU(cpu));
 205     object_unparent(OBJECT(cpu));
 206 }
 207
 208 /*
 209  * Called when CPUs are hot-plugged.
 210  */
 211 static void spapr_cpu_core_reset(DeviceState *dev)
 212 {
 213     CPUCore *cc = CPU_CORE(dev);
 214     SpaprCpuCore *sc = SPAPR_CPU_CORE(dev);
 215     int i;
 216
 217     for (i = 0; i < cc->nr_threads; i++) {
 218         spapr_reset_vcpu(sc->threads[i]);
 219     }
 220 }
 221
 222 /*
 223  * Called by the machine reset.
 224  */
 225 static void spapr_cpu_core_reset_handler(void *opaque)
 226 {
 227     spapr_cpu_core_reset(opaque);
 228 }
 229
 230 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp)
 231 {
 232     SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 233     CPUCore *cc = CPU_CORE(dev);
 234     int i;
 235
 236     qemu_unregister_reset(spapr_cpu_core_reset_handler, sc);
 237
 238     for (i = 0; i < cc->nr_threads; i++) {
 239         spapr_unrealize_vcpu(sc->threads[i], sc);
 240     }
 241     g_free(sc->threads);
 242 }
 243
 244 static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
 245                                SpaprCpuCore *sc, Error **errp)
 246 {
 247     CPUPPCState *env = &cpu->env;
 248     CPUState *cs = CPU(cpu);
 249     Error *local_err = NULL;
 250
 251     object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
 252     if (local_err) {
 253         goto error;
 254     }
 255
 256     /* Set time-base frequency to 512 MHz */
 257     cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
 258
 259     cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
 260     kvmppc_set_papr(cpu);
 261
 262     if (spapr_irq_cpu_intc_create(spapr, cpu, &local_err) < 0) {
 263         goto error_intc_create;
 264     }
 265
 266     if (!sc->pre_3_0_migration) {
 267         vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
 268                          cpu->machine_data);
 269     }
 270
 271     return;
 272
 273 error_intc_create:
 274     cpu_remove_sync(CPU(cpu));
 275 error:
 276     error_propagate(errp, local_err);
 277 }
 278
 279 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
 280 {
 281     SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
 282     CPUCore *cc = CPU_CORE(sc);
 283     Object *obj;
 284     char *id;
 285     CPUState *cs;
 286     PowerPCCPU *cpu;
 287     Error *local_err = NULL;
 288
 289     obj = object_new(scc->cpu_type);
 290
 291     cs = CPU(obj);
 292     cpu = POWERPC_CPU(obj);
 293     cs->cpu_index = cc->core_id + i;
 294     spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
 295     if (local_err) {
 296         goto err;
 297     }
 298
 299     cpu->node_id = sc->node_id;
 300
 301     id = g_strdup_printf("thread[%d]", i);
 302     object_property_add_child(OBJECT(sc), id, obj, &local_err);
 303     g_free(id);
 304     if (local_err) {
 305         goto err;
 306     }
 307
 308     cpu->machine_data = g_new0(SpaprCpuState, 1);
 309
 310     object_unref(obj);
 311     return cpu;
 312
 313 err:
 314     object_unref(obj);
 315     error_propagate(errp, local_err);
 316     return NULL;
 317 }
 318
 319 static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
 320 {
 321     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 322
 323     cpu->machine_data = NULL;
 324     g_free(spapr_cpu);
 325     object_unparent(OBJECT(cpu));
 326 }
 327
 328 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
 329 {
 330     /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
 331      * tries to add a sPAPR CPU core to a non-pseries machine.
 332      */
 333     SpaprMachineState *spapr =
 334         (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
 335                                                   TYPE_SPAPR_MACHINE);
 336     SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 337     CPUCore *cc = CPU_CORE(OBJECT(dev));
 338     Error *local_err = NULL;
 339     int i, j;
 340
 341     if (!spapr) {
 342         error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
 343         return;
 344     }
 345
 346     sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
 347     for (i = 0; i < cc->nr_threads; i++) {
 348         sc->threads[i] = spapr_create_vcpu(sc, i, &local_err);
 349         if (local_err) {
 350             goto err;
 351         }
 352     }
 353
 354     for (j = 0; j < cc->nr_threads; j++) {
 355         spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err);
 356         if (local_err) {
 357             goto err_unrealize;
 358         }
 359     }
 360
 361     qemu_register_reset(spapr_cpu_core_reset_handler, sc);
 362     return;
 363
 364 err_unrealize:
 365     while (--j >= 0) {
 366         spapr_unrealize_vcpu(sc->threads[j], sc);
 367     }
 368 err:
 369     while (--i >= 0) {
 370         spapr_delete_vcpu(sc->threads[i], sc);
 371     }
 372     g_free(sc->threads);
 373     error_propagate(errp, local_err);
 374 }
 375
 376 static Property spapr_cpu_core_properties[] = {
 377     DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
 378     DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration,
 379                      false),
 380     DEFINE_PROP_END_OF_LIST()
 381 };
 382
 383 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
 384 {
 385     DeviceClass *dc = DEVICE_CLASS(oc);
 386     SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
 387
 388     dc->realize = spapr_cpu_core_realize;
 389     dc->unrealize = spapr_cpu_core_unrealize;
 390     dc->reset = spapr_cpu_core_reset;
 391     dc->props = spapr_cpu_core_properties;
 392     scc->cpu_type = data;
 393 }
 394
 395 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
 396     {                                                   \
 397         .parent = TYPE_SPAPR_CPU_CORE,                  \
 398         .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
 399         .class_init = spapr_cpu_core_class_init,        \
 400         .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model),    \
 401     }
 402
 403 static const TypeInfo spapr_cpu_core_type_infos[] = {
 404     {
 405         .name = TYPE_SPAPR_CPU_CORE,
 406         .parent = TYPE_CPU_CORE,
 407         .abstract = true,
 408         .instance_size = sizeof(SpaprCpuCore),
 409         .class_size = sizeof(SpaprCpuCoreClass),
 410     },
 411     DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
 412     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
 413     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
 414     DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
 415     DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
 416     DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
 417     DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
 418     DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
 419     DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
 420     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
 421     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
 422 #ifdef CONFIG_KVM
 423     DEFINE_SPAPR_CPU_CORE_TYPE("host"),
 424 #endif
 425 };
 426
 427 DEFINE_TYPES(spapr_cpu_core_type_infos)