hw/ppc/spapr_cpu_core.c

   1 /*
   2  * sPAPR CPU core device, acts as container of CPU thread devices.
   3  *
   4  * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/cpu/core.h"
  12 #include "hw/ppc/spapr_cpu_core.h"
  13 #include "hw/qdev-properties.h"
  14 #include "migration/vmstate.h"
  15 #include "target/ppc/cpu.h"
  16 #include "hw/ppc/spapr.h"
  17 #include "qapi/error.h"
  18 #include "sysemu/cpus.h"
  19 #include "sysemu/kvm.h"
  20 #include "target/ppc/kvm_ppc.h"
  21 #include "hw/ppc/ppc.h"
  22 #include "target/ppc/mmu-hash64.h"
  23 #include "sysemu/numa.h"
  24 #include "sysemu/reset.h"
  25 #include "sysemu/hw_accel.h"
  26 #include "qemu/error-report.h"
  27
  28 static void spapr_reset_vcpu(PowerPCCPU *cpu)
  29 {
  30     CPUState *cs = CPU(cpu);
  31     CPUPPCState *env = &cpu->env;
  32     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  33     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
  34     target_ulong lpcr;
  35
  36     cpu_reset(cs);
  37
  38     /* All CPUs start halted.  CPU0 is unhalted from the machine level
  39      * reset code and the rest are explicitly started up by the guest
  40      * using an RTAS call */
  41     cs->halted = 1;
  42
  43     env->spr[SPR_HIOR] = 0;
  44
  45     lpcr = env->spr[SPR_LPCR];
  46
  47     /* Set emulated LPCR to not send interrupts to hypervisor. Note that
  48      * under KVM, the actual HW LPCR will be set differently by KVM itself,
  49      * the settings below ensure proper operations with TCG in absence of
  50      * a real hypervisor.
  51      *
  52      * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
  53      * real mode accesses, which thankfully defaults to 0 and isn't
  54      * accessible in guest mode.
  55      *
  56      * Disable Power-saving mode Exit Cause exceptions for the CPU, so
  57      * we don't get spurious wakups before an RTAS start-cpu call.
  58      * For the same reason, set PSSCR_EC.
  59      */
  60     lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
  61     lpcr |= LPCR_LPES0 | LPCR_LPES1;
  62     env->spr[SPR_PSSCR] |= PSSCR_EC;
  63
  64     /* Set RMLS to the max (ie, 16G) */
  65     lpcr &= ~LPCR_RMLS;
  66     lpcr |= 1ull << LPCR_RMLS_SHIFT;
  67
  68     ppc_store_lpcr(cpu, lpcr);
  69
  70     /* Set a full AMOR so guest can use the AMR as it sees fit */
  71     env->spr[SPR_AMOR] = 0xffffffffffffffffull;
  72
  73     spapr_cpu->vpa_addr = 0;
  74     spapr_cpu->slb_shadow_addr = 0;
  75     spapr_cpu->slb_shadow_size = 0;
  76     spapr_cpu->dtl_addr = 0;
  77     spapr_cpu->dtl_size = 0;
  78
  79     spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu);
  80
  81     kvm_check_mmu(cpu, &error_fatal);
  82 }
  83
  84 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
  85 {
  86     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  87     CPUPPCState *env = &cpu->env;
  88
  89     env->nip = nip;
  90     env->gpr[3] = r3;
  91     kvmppc_set_reg_ppc_online(cpu, 1);
  92     CPU(cpu)->halted = 0;
  93     /* Enable Power-saving mode Exit Cause exceptions */
  94     ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
  95 }
  96
  97 /*
  98  * Return the sPAPR CPU core type for @model which essentially is the CPU
  99  * model specified with -cpu cmdline option.
 100  */
 101 const char *spapr_get_cpu_core_type(const char *cpu_type)
 102 {
 103     int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
 104     char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
 105                                       len, cpu_type);
 106     ObjectClass *oc = object_class_by_name(core_type);
 107
 108     g_free(core_type);
 109     if (!oc) {
 110         return NULL;
 111     }
 112
 113     return object_class_get_name(oc);
 114 }
 115
 116 static bool slb_shadow_needed(void *opaque)
 117 {
 118     SpaprCpuState *spapr_cpu = opaque;
 119
 120     return spapr_cpu->slb_shadow_addr != 0;
 121 }
 122
 123 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
 124     .name = "spapr_cpu/vpa/slb_shadow",
 125     .version_id = 1,
 126     .minimum_version_id = 1,
 127     .needed = slb_shadow_needed,
 128     .fields = (VMStateField[]) {
 129         VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState),
 130         VMSTATE_UINT64(slb_shadow_size, SpaprCpuState),
 131         VMSTATE_END_OF_LIST()
 132     }
 133 };
 134
 135 static bool dtl_needed(void *opaque)
 136 {
 137     SpaprCpuState *spapr_cpu = opaque;
 138
 139     return spapr_cpu->dtl_addr != 0;
 140 }
 141
 142 static const VMStateDescription vmstate_spapr_cpu_dtl = {
 143     .name = "spapr_cpu/vpa/dtl",
 144     .version_id = 1,
 145     .minimum_version_id = 1,
 146     .needed = dtl_needed,
 147     .fields = (VMStateField[]) {
 148         VMSTATE_UINT64(dtl_addr, SpaprCpuState),
 149         VMSTATE_UINT64(dtl_size, SpaprCpuState),
 150         VMSTATE_END_OF_LIST()
 151     }
 152 };
 153
 154 static bool vpa_needed(void *opaque)
 155 {
 156     SpaprCpuState *spapr_cpu = opaque;
 157
 158     return spapr_cpu->vpa_addr != 0;
 159 }
 160
 161 static const VMStateDescription vmstate_spapr_cpu_vpa = {
 162     .name = "spapr_cpu/vpa",
 163     .version_id = 1,
 164     .minimum_version_id = 1,
 165     .needed = vpa_needed,
 166     .fields = (VMStateField[]) {
 167         VMSTATE_UINT64(vpa_addr, SpaprCpuState),
 168         VMSTATE_END_OF_LIST()
 169     },
 170     .subsections = (const VMStateDescription * []) {
 171         &vmstate_spapr_cpu_slb_shadow,
 172         &vmstate_spapr_cpu_dtl,
 173         NULL
 174     }
 175 };
 176
 177 static const VMStateDescription vmstate_spapr_cpu_state = {
 178     .name = "spapr_cpu",
 179     .version_id = 1,
 180     .minimum_version_id = 1,
 181     .fields = (VMStateField[]) {
 182         VMSTATE_END_OF_LIST()
 183     },
 184     .subsections = (const VMStateDescription * []) {
 185         &vmstate_spapr_cpu_vpa,
 186         NULL
 187     }
 188 };
 189
 190 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
 191 {
 192     if (!sc->pre_3_0_migration) {
 193         vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
 194     }
 195     if (spapr_cpu_state(cpu)->icp) {
 196         object_unparent(OBJECT(spapr_cpu_state(cpu)->icp));
 197     }
 198     if (spapr_cpu_state(cpu)->tctx) {
 199         object_unparent(OBJECT(spapr_cpu_state(cpu)->tctx));
 200     }
 201     cpu_remove_sync(CPU(cpu));
 202     object_unparent(OBJECT(cpu));
 203 }
 204
 205 /*
 206  * Called when CPUs are hot-plugged.
 207  */
 208 static void spapr_cpu_core_reset(DeviceState *dev)
 209 {
 210     CPUCore *cc = CPU_CORE(dev);
 211     SpaprCpuCore *sc = SPAPR_CPU_CORE(dev);
 212     int i;
 213
 214     for (i = 0; i < cc->nr_threads; i++) {
 215         spapr_reset_vcpu(sc->threads[i]);
 216     }
 217 }
 218
 219 /*
 220  * Called by the machine reset.
 221  */
 222 static void spapr_cpu_core_reset_handler(void *opaque)
 223 {
 224     spapr_cpu_core_reset(opaque);
 225 }
 226
 227 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp)
 228 {
 229     SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 230     CPUCore *cc = CPU_CORE(dev);
 231     int i;
 232
 233     qemu_unregister_reset(spapr_cpu_core_reset_handler, sc);
 234
 235     for (i = 0; i < cc->nr_threads; i++) {
 236         spapr_unrealize_vcpu(sc->threads[i], sc);
 237     }
 238     g_free(sc->threads);
 239 }
 240
 241 static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
 242                                SpaprCpuCore *sc, Error **errp)
 243 {
 244     CPUPPCState *env = &cpu->env;
 245     CPUState *cs = CPU(cpu);
 246     Error *local_err = NULL;
 247
 248     object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
 249     if (local_err) {
 250         goto error;
 251     }
 252
 253     /* Set time-base frequency to 512 MHz */
 254     cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
 255
 256     cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
 257     kvmppc_set_papr(cpu);
 258
 259     if (spapr_irq_cpu_intc_create(spapr, cpu, &local_err) < 0) {
 260         goto error_intc_create;
 261     }
 262
 263     if (!sc->pre_3_0_migration) {
 264         vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
 265                          cpu->machine_data);
 266     }
 267
 268     return;
 269
 270 error_intc_create:
 271     cpu_remove_sync(CPU(cpu));
 272 error:
 273     error_propagate(errp, local_err);
 274 }
 275
 276 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
 277 {
 278     SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
 279     CPUCore *cc = CPU_CORE(sc);
 280     Object *obj;
 281     char *id;
 282     CPUState *cs;
 283     PowerPCCPU *cpu;
 284     Error *local_err = NULL;
 285
 286     obj = object_new(scc->cpu_type);
 287
 288     cs = CPU(obj);
 289     cpu = POWERPC_CPU(obj);
 290     cs->cpu_index = cc->core_id + i;
 291     spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
 292     if (local_err) {
 293         goto err;
 294     }
 295
 296     cpu->node_id = sc->node_id;
 297
 298     id = g_strdup_printf("thread[%d]", i);
 299     object_property_add_child(OBJECT(sc), id, obj, &local_err);
 300     g_free(id);
 301     if (local_err) {
 302         goto err;
 303     }
 304
 305     cpu->machine_data = g_new0(SpaprCpuState, 1);
 306
 307     object_unref(obj);
 308     return cpu;
 309
 310 err:
 311     object_unref(obj);
 312     error_propagate(errp, local_err);
 313     return NULL;
 314 }
 315
 316 static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
 317 {
 318     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 319
 320     cpu->machine_data = NULL;
 321     g_free(spapr_cpu);
 322     object_unparent(OBJECT(cpu));
 323 }
 324
 325 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
 326 {
 327     /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
 328      * tries to add a sPAPR CPU core to a non-pseries machine.
 329      */
 330     SpaprMachineState *spapr =
 331         (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
 332                                                   TYPE_SPAPR_MACHINE);
 333     SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 334     CPUCore *cc = CPU_CORE(OBJECT(dev));
 335     Error *local_err = NULL;
 336     int i, j;
 337
 338     if (!spapr) {
 339         error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
 340         return;
 341     }
 342
 343     sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
 344     for (i = 0; i < cc->nr_threads; i++) {
 345         sc->threads[i] = spapr_create_vcpu(sc, i, &local_err);
 346         if (local_err) {
 347             goto err;
 348         }
 349     }
 350
 351     for (j = 0; j < cc->nr_threads; j++) {
 352         spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err);
 353         if (local_err) {
 354             goto err_unrealize;
 355         }
 356     }
 357
 358     qemu_register_reset(spapr_cpu_core_reset_handler, sc);
 359     return;
 360
 361 err_unrealize:
 362     while (--j >= 0) {
 363         spapr_unrealize_vcpu(sc->threads[j], sc);
 364     }
 365 err:
 366     while (--i >= 0) {
 367         spapr_delete_vcpu(sc->threads[i], sc);
 368     }
 369     g_free(sc->threads);
 370     error_propagate(errp, local_err);
 371 }
 372
 373 static Property spapr_cpu_core_properties[] = {
 374     DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
 375     DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration,
 376                      false),
 377     DEFINE_PROP_END_OF_LIST()
 378 };
 379
 380 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
 381 {
 382     DeviceClass *dc = DEVICE_CLASS(oc);
 383     SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
 384
 385     dc->realize = spapr_cpu_core_realize;
 386     dc->unrealize = spapr_cpu_core_unrealize;
 387     dc->reset = spapr_cpu_core_reset;
 388     dc->props = spapr_cpu_core_properties;
 389     scc->cpu_type = data;
 390 }
 391
 392 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
 393     {                                                   \
 394         .parent = TYPE_SPAPR_CPU_CORE,                  \
 395         .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
 396         .class_init = spapr_cpu_core_class_init,        \
 397         .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model),    \
 398     }
 399
 400 static const TypeInfo spapr_cpu_core_type_infos[] = {
 401     {
 402         .name = TYPE_SPAPR_CPU_CORE,
 403         .parent = TYPE_CPU_CORE,
 404         .abstract = true,
 405         .instance_size = sizeof(SpaprCpuCore),
 406         .class_size = sizeof(SpaprCpuCoreClass),
 407     },
 408     DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
 409     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
 410     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
 411     DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
 412     DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
 413     DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
 414     DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
 415     DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
 416     DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
 417     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
 418     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
 419 #ifdef CONFIG_KVM
 420     DEFINE_SPAPR_CPU_CORE_TYPE("host"),
 421 #endif
 422 };
 423
 424 DEFINE_TYPES(spapr_cpu_core_type_infos)