hw/ppc/spapr_hcall.c

   1 #include "qemu/osdep.h"
   2 #include "qemu/cutils.h"
   3 #include "qapi/error.h"
   4 #include "sysemu/hw_accel.h"
   5 #include "sysemu/runstate.h"
   6 #include "qemu/log.h"
   7 #include "qemu/main-loop.h"
   8 #include "qemu/module.h"
   9 #include "qemu/error-report.h"
  10 #include "exec/exec-all.h"
  11 #include "exec/tb-flush.h"
  12 #include "helper_regs.h"
  13 #include "hw/ppc/ppc.h"
  14 #include "hw/ppc/spapr.h"
  15 #include "hw/ppc/spapr_cpu_core.h"
  16 #include "hw/ppc/spapr_nested.h"
  17 #include "mmu-hash64.h"
  18 #include "cpu-models.h"
  19 #include "trace.h"
  20 #include "kvm_ppc.h"
  21 #include "hw/ppc/fdt.h"
  22 #include "hw/ppc/spapr_ovec.h"
  23 #include "hw/ppc/spapr_numa.h"
  24 #include "mmu-book3s-v3.h"
  25 #include "hw/mem/memory-device.h"
  26
  27 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr)
  28 {
  29     MachineState *machine = MACHINE(spapr);
  30     DeviceMemoryState *dms = machine->device_memory;
  31
  32     if (addr < machine->ram_size) {
  33         return true;
  34     }
  35     if ((addr >= dms->base)
  36         && ((addr - dms->base) < memory_region_size(&dms->mr))) {
  37         return true;
  38     }
  39
  40     return false;
  41 }
  42
  43 /* Convert a return code from the KVM ioctl()s implementing resize HPT
  44  * into a PAPR hypercall return code */
  45 static target_ulong resize_hpt_convert_rc(int ret)
  46 {
  47     if (ret >= 100000) {
  48         return H_LONG_BUSY_ORDER_100_SEC;
  49     } else if (ret >= 10000) {
  50         return H_LONG_BUSY_ORDER_10_SEC;
  51     } else if (ret >= 1000) {
  52         return H_LONG_BUSY_ORDER_1_SEC;
  53     } else if (ret >= 100) {
  54         return H_LONG_BUSY_ORDER_100_MSEC;
  55     } else if (ret >= 10) {
  56         return H_LONG_BUSY_ORDER_10_MSEC;
  57     } else if (ret > 0) {
  58         return H_LONG_BUSY_ORDER_1_MSEC;
  59     }
  60
  61     switch (ret) {
  62     case 0:
  63         return H_SUCCESS;
  64     case -EPERM:
  65         return H_AUTHORITY;
  66     case -EINVAL:
  67         return H_PARAMETER;
  68     case -ENXIO:
  69         return H_CLOSED;
  70     case -ENOSPC:
  71         return H_PTEG_FULL;
  72     case -EBUSY:
  73         return H_BUSY;
  74     case -ENOMEM:
  75         return H_NO_MEM;
  76     default:
  77         return H_HARDWARE;
  78     }
  79 }
  80
  81 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu,
  82                                          SpaprMachineState *spapr,
  83                                          target_ulong opcode,
  84                                          target_ulong *args)
  85 {
  86     target_ulong flags = args[0];
  87     int shift = args[1];
  88     uint64_t current_ram_size;
  89     int rc;
  90
  91     if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
  92         return H_AUTHORITY;
  93     }
  94
  95     if (!spapr->htab_shift) {
  96         /* Radix guest, no HPT */
  97         return H_NOT_AVAILABLE;
  98     }
  99
 100     trace_spapr_h_resize_hpt_prepare(flags, shift);
 101
 102     if (flags != 0) {
 103         return H_PARAMETER;
 104     }
 105
 106     if (shift && ((shift < 18) || (shift > 46))) {
 107         return H_PARAMETER;
 108     }
 109
 110     current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
 111
 112     /* We only allow the guest to allocate an HPT one order above what
 113      * we'd normally give them (to stop a small guest claiming a huge
 114      * chunk of resources in the HPT */
 115     if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) {
 116         return H_RESOURCE;
 117     }
 118
 119     rc = kvmppc_resize_hpt_prepare(cpu, flags, shift);
 120     if (rc != -ENOSYS) {
 121         return resize_hpt_convert_rc(rc);
 122     }
 123
 124     if (kvm_enabled()) {
 125         return H_HARDWARE;
 126     }
 127
 128     return softmmu_resize_hpt_prepare(cpu, spapr, shift);
 129 }
 130
 131 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data)
 132 {
 133     int ret;
 134
 135     cpu_synchronize_state(cs);
 136
 137     ret = kvmppc_put_books_sregs(POWERPC_CPU(cs));
 138     if (ret < 0) {
 139         error_report("failed to push sregs to KVM: %s", strerror(-ret));
 140         exit(1);
 141     }
 142 }
 143
 144 void push_sregs_to_kvm_pr(SpaprMachineState *spapr)
 145 {
 146     CPUState *cs;
 147
 148     /*
 149      * This is a hack for the benefit of KVM PR - it abuses the SDR1
 150      * slot in kvm_sregs to communicate the userspace address of the
 151      * HPT
 152      */
 153     if (!kvm_enabled() || !spapr->htab) {
 154         return;
 155     }
 156
 157     CPU_FOREACH(cs) {
 158         run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL);
 159     }
 160 }
 161
 162 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu,
 163                                         SpaprMachineState *spapr,
 164                                         target_ulong opcode,
 165                                         target_ulong *args)
 166 {
 167     target_ulong flags = args[0];
 168     target_ulong shift = args[1];
 169     int rc;
 170
 171     if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
 172         return H_AUTHORITY;
 173     }
 174
 175     if (!spapr->htab_shift) {
 176         /* Radix guest, no HPT */
 177         return H_NOT_AVAILABLE;
 178     }
 179
 180     trace_spapr_h_resize_hpt_commit(flags, shift);
 181
 182     rc = kvmppc_resize_hpt_commit(cpu, flags, shift);
 183     if (rc != -ENOSYS) {
 184         rc = resize_hpt_convert_rc(rc);
 185         if (rc == H_SUCCESS) {
 186             /* Need to set the new htab_shift in the machine state */
 187             spapr->htab_shift = shift;
 188         }
 189         return rc;
 190     }
 191
 192     if (kvm_enabled()) {
 193         return H_HARDWARE;
 194     }
 195
 196     return softmmu_resize_hpt_commit(cpu, spapr, flags, shift);
 197 }
 198
 199
 200
 201 static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr,
 202                                 target_ulong opcode, target_ulong *args)
 203 {
 204     cpu_synchronize_state(CPU(cpu));
 205     cpu->env.spr[SPR_SPRG0] = args[0];
 206
 207     return H_SUCCESS;
 208 }
 209
 210 static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr,
 211                                target_ulong opcode, target_ulong *args)
 212 {
 213     if (!ppc_has_spr(cpu, SPR_DABR)) {
 214         return H_HARDWARE;              /* DABR register not available */
 215     }
 216     cpu_synchronize_state(CPU(cpu));
 217
 218     if (ppc_has_spr(cpu, SPR_DABRX)) {
 219         cpu->env.spr[SPR_DABRX] = 0x3;  /* Use Problem and Privileged state */
 220     } else if (!(args[0] & 0x4)) {      /* Breakpoint Translation set? */
 221         return H_RESERVED_DABR;
 222     }
 223
 224     cpu->env.spr[SPR_DABR] = args[0];
 225     return H_SUCCESS;
 226 }
 227
 228 static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr,
 229                                 target_ulong opcode, target_ulong *args)
 230 {
 231     target_ulong dabrx = args[1];
 232
 233     if (!ppc_has_spr(cpu, SPR_DABR) || !ppc_has_spr(cpu, SPR_DABRX)) {
 234         return H_HARDWARE;
 235     }
 236
 237     if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0
 238         || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) {
 239         return H_PARAMETER;
 240     }
 241
 242     cpu_synchronize_state(CPU(cpu));
 243     cpu->env.spr[SPR_DABRX] = dabrx;
 244     cpu->env.spr[SPR_DABR] = args[0];
 245
 246     return H_SUCCESS;
 247 }
 248
 249 static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr,
 250                                 target_ulong opcode, target_ulong *args)
 251 {
 252     target_ulong flags = args[0];
 253     hwaddr dst = args[1];
 254     hwaddr src = args[2];
 255     hwaddr len = TARGET_PAGE_SIZE;
 256     uint8_t *pdst, *psrc;
 257     target_long ret = H_SUCCESS;
 258
 259     if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE
 260                   | H_COPY_PAGE | H_ZERO_PAGE)) {
 261         qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n",
 262                       flags);
 263         return H_PARAMETER;
 264     }
 265
 266     /* Map-in destination */
 267     if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) {
 268         return H_PARAMETER;
 269     }
 270     pdst = cpu_physical_memory_map(dst, &len, true);
 271     if (!pdst || len != TARGET_PAGE_SIZE) {
 272         return H_PARAMETER;
 273     }
 274
 275     if (flags & H_COPY_PAGE) {
 276         /* Map-in source, copy to destination, and unmap source again */
 277         if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) {
 278             ret = H_PARAMETER;
 279             goto unmap_out;
 280         }
 281         psrc = cpu_physical_memory_map(src, &len, false);
 282         if (!psrc || len != TARGET_PAGE_SIZE) {
 283             ret = H_PARAMETER;
 284             goto unmap_out;
 285         }
 286         memcpy(pdst, psrc, len);
 287         cpu_physical_memory_unmap(psrc, len, 0, len);
 288     } else if (flags & H_ZERO_PAGE) {
 289         memset(pdst, 0, len);          /* Just clear the destination page */
 290     }
 291
 292     if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) {
 293         kvmppc_dcbst_range(cpu, pdst, len);
 294     }
 295     if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) {
 296         if (kvm_enabled()) {
 297             kvmppc_icbi_range(cpu, pdst, len);
 298         } else {
 299             tb_flush(CPU(cpu));
 300         }
 301     }
 302
 303 unmap_out:
 304     cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len);
 305     return ret;
 306 }
 307
 308 #define FLAGS_REGISTER_VPA         0x0000200000000000ULL
 309 #define FLAGS_REGISTER_DTL         0x0000400000000000ULL
 310 #define FLAGS_REGISTER_SLBSHADOW   0x0000600000000000ULL
 311 #define FLAGS_DEREGISTER_VPA       0x0000a00000000000ULL
 312 #define FLAGS_DEREGISTER_DTL       0x0000c00000000000ULL
 313 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL
 314
 315 static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa)
 316 {
 317     CPUState *cs = CPU(cpu);
 318     CPUPPCState *env = &cpu->env;
 319     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 320     uint16_t size;
 321     uint8_t tmp;
 322
 323     if (vpa == 0) {
 324         hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
 325         return H_HARDWARE;
 326     }
 327
 328     if (vpa % env->dcache_line_size) {
 329         return H_PARAMETER;
 330     }
 331     /* FIXME: bounds check the address */
 332
 333     size = lduw_be_phys(cs->as, vpa + 0x4);
 334
 335     if (size < VPA_MIN_SIZE) {
 336         return H_PARAMETER;
 337     }
 338
 339     /* VPA is not allowed to cross a page boundary */
 340     if ((vpa / 4096) != ((vpa + size - 1) / 4096)) {
 341         return H_PARAMETER;
 342     }
 343
 344     spapr_cpu->vpa_addr = vpa;
 345
 346     tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET);
 347     tmp |= VPA_SHARED_PROC_VAL;
 348     stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
 349
 350     return H_SUCCESS;
 351 }
 352
 353 static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa)
 354 {
 355     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 356
 357     if (spapr_cpu->slb_shadow_addr) {
 358         return H_RESOURCE;
 359     }
 360
 361     if (spapr_cpu->dtl_addr) {
 362         return H_RESOURCE;
 363     }
 364
 365     spapr_cpu->vpa_addr = 0;
 366     return H_SUCCESS;
 367 }
 368
 369 static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr)
 370 {
 371     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 372     uint32_t size;
 373
 374     if (addr == 0) {
 375         hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
 376         return H_HARDWARE;
 377     }
 378
 379     size = ldl_be_phys(CPU(cpu)->as, addr + 0x4);
 380     if (size < 0x8) {
 381         return H_PARAMETER;
 382     }
 383
 384     if ((addr / 4096) != ((addr + size - 1) / 4096)) {
 385         return H_PARAMETER;
 386     }
 387
 388     if (!spapr_cpu->vpa_addr) {
 389         return H_RESOURCE;
 390     }
 391
 392     spapr_cpu->slb_shadow_addr = addr;
 393     spapr_cpu->slb_shadow_size = size;
 394
 395     return H_SUCCESS;
 396 }
 397
 398 static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr)
 399 {
 400     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 401
 402     spapr_cpu->slb_shadow_addr = 0;
 403     spapr_cpu->slb_shadow_size = 0;
 404     return H_SUCCESS;
 405 }
 406
 407 static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr)
 408 {
 409     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 410     uint32_t size;
 411
 412     if (addr == 0) {
 413         hcall_dprintf("Can't cope with DTL at logical 0\n");
 414         return H_HARDWARE;
 415     }
 416
 417     size = ldl_be_phys(CPU(cpu)->as, addr + 0x4);
 418
 419     if (size < 48) {
 420         return H_PARAMETER;
 421     }
 422
 423     if (!spapr_cpu->vpa_addr) {
 424         return H_RESOURCE;
 425     }
 426
 427     spapr_cpu->dtl_addr = addr;
 428     spapr_cpu->dtl_size = size;
 429
 430     return H_SUCCESS;
 431 }
 432
 433 static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr)
 434 {
 435     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 436
 437     spapr_cpu->dtl_addr = 0;
 438     spapr_cpu->dtl_size = 0;
 439
 440     return H_SUCCESS;
 441 }
 442
 443 static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr,
 444                                    target_ulong opcode, target_ulong *args)
 445 {
 446     target_ulong flags = args[0];
 447     target_ulong procno = args[1];
 448     target_ulong vpa = args[2];
 449     target_ulong ret = H_PARAMETER;
 450     PowerPCCPU *tcpu;
 451
 452     tcpu = spapr_find_cpu(procno);
 453     if (!tcpu) {
 454         return H_PARAMETER;
 455     }
 456
 457     switch (flags) {
 458     case FLAGS_REGISTER_VPA:
 459         ret = register_vpa(tcpu, vpa);
 460         break;
 461
 462     case FLAGS_DEREGISTER_VPA:
 463         ret = deregister_vpa(tcpu, vpa);
 464         break;
 465
 466     case FLAGS_REGISTER_SLBSHADOW:
 467         ret = register_slb_shadow(tcpu, vpa);
 468         break;
 469
 470     case FLAGS_DEREGISTER_SLBSHADOW:
 471         ret = deregister_slb_shadow(tcpu, vpa);
 472         break;
 473
 474     case FLAGS_REGISTER_DTL:
 475         ret = register_dtl(tcpu, vpa);
 476         break;
 477
 478     case FLAGS_DEREGISTER_DTL:
 479         ret = deregister_dtl(tcpu, vpa);
 480         break;
 481     }
 482
 483     return ret;
 484 }
 485
 486 static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr,
 487                            target_ulong opcode, target_ulong *args)
 488 {
 489     CPUPPCState *env = &cpu->env;
 490     CPUState *cs = CPU(cpu);
 491     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 492
 493     env->msr |= (1ULL << MSR_EE);
 494     hreg_compute_hflags(env);
 495     ppc_maybe_interrupt(env);
 496
 497     if (spapr_cpu->prod) {
 498         spapr_cpu->prod = false;
 499         return H_SUCCESS;
 500     }
 501
 502     if (!cpu_has_work(cs)) {
 503         cs->halted = 1;
 504         cs->exception_index = EXCP_HLT;
 505         cs->exit_request = 1;
 506         ppc_maybe_interrupt(env);
 507     }
 508
 509     return H_SUCCESS;
 510 }
 511
 512 /*
 513  * Confer to self, aka join. Cede could use the same pattern as well, if
 514  * EXCP_HLT can be changed to ECXP_HALTED.
 515  */
 516 static target_ulong h_confer_self(PowerPCCPU *cpu)
 517 {
 518     CPUState *cs = CPU(cpu);
 519     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 520
 521     if (spapr_cpu->prod) {
 522         spapr_cpu->prod = false;
 523         return H_SUCCESS;
 524     }
 525     cs->halted = 1;
 526     cs->exception_index = EXCP_HALTED;
 527     cs->exit_request = 1;
 528     ppc_maybe_interrupt(&cpu->env);
 529
 530     return H_SUCCESS;
 531 }
 532
 533 static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr,
 534                            target_ulong opcode, target_ulong *args)
 535 {
 536     CPUPPCState *env = &cpu->env;
 537     CPUState *cs;
 538     bool last_unjoined = true;
 539
 540     if (env->msr & (1ULL << MSR_EE)) {
 541         return H_BAD_MODE;
 542     }
 543
 544     /*
 545      * Must not join the last CPU running. Interestingly, no such restriction
 546      * for H_CONFER-to-self, but that is probably not intended to be used
 547      * when H_JOIN is available.
 548      */
 549     CPU_FOREACH(cs) {
 550         PowerPCCPU *c = POWERPC_CPU(cs);
 551         CPUPPCState *e = &c->env;
 552         if (c == cpu) {
 553             continue;
 554         }
 555
 556         /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */
 557         if (!cs->halted || (e->msr & (1ULL << MSR_EE))) {
 558             last_unjoined = false;
 559             break;
 560         }
 561     }
 562     if (last_unjoined) {
 563         return H_CONTINUE;
 564     }
 565
 566     return h_confer_self(cpu);
 567 }
 568
 569 static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr,
 570                            target_ulong opcode, target_ulong *args)
 571 {
 572     target_long target = args[0];
 573     uint32_t dispatch = args[1];
 574     CPUState *cs = CPU(cpu);
 575     SpaprCpuState *spapr_cpu;
 576
 577     /*
 578      * -1 means confer to all other CPUs without dispatch counter check,
 579      *  otherwise it's a targeted confer.
 580      */
 581     if (target != -1) {
 582         PowerPCCPU *target_cpu = spapr_find_cpu(target);
 583         uint32_t target_dispatch;
 584
 585         if (!target_cpu) {
 586             return H_PARAMETER;
 587         }
 588
 589         /*
 590          * target == self is a special case, we wait until prodded, without
 591          * dispatch counter check.
 592          */
 593         if (cpu == target_cpu) {
 594             return h_confer_self(cpu);
 595         }
 596
 597         spapr_cpu = spapr_cpu_state(target_cpu);
 598         if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) {
 599             return H_SUCCESS;
 600         }
 601
 602         target_dispatch = ldl_be_phys(cs->as,
 603                                   spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER);
 604         if (target_dispatch != dispatch) {
 605             return H_SUCCESS;
 606         }
 607
 608         /*
 609          * The targeted confer does not do anything special beyond yielding
 610          * the current vCPU, but even this should be better than nothing.
 611          * At least for single-threaded tcg, it gives the target a chance to
 612          * run before we run again. Multi-threaded tcg does not really do
 613          * anything with EXCP_YIELD yet.
 614          */
 615     }
 616
 617     cs->exception_index = EXCP_YIELD;
 618     cs->exit_request = 1;
 619     cpu_loop_exit(cs);
 620
 621     return H_SUCCESS;
 622 }
 623
 624 static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr,
 625                            target_ulong opcode, target_ulong *args)
 626 {
 627     target_long target = args[0];
 628     PowerPCCPU *tcpu;
 629     CPUState *cs;
 630     SpaprCpuState *spapr_cpu;
 631
 632     tcpu = spapr_find_cpu(target);
 633     cs = CPU(tcpu);
 634     if (!cs) {
 635         return H_PARAMETER;
 636     }
 637
 638     spapr_cpu = spapr_cpu_state(tcpu);
 639     spapr_cpu->prod = true;
 640     cs->halted = 0;
 641     ppc_maybe_interrupt(&cpu->env);
 642     qemu_cpu_kick(cs);
 643
 644     return H_SUCCESS;
 645 }
 646
 647 static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr,
 648                            target_ulong opcode, target_ulong *args)
 649 {
 650     target_ulong rtas_r3 = args[0];
 651     uint32_t token = rtas_ld(rtas_r3, 0);
 652     uint32_t nargs = rtas_ld(rtas_r3, 1);
 653     uint32_t nret = rtas_ld(rtas_r3, 2);
 654
 655     return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12,
 656                            nret, rtas_r3 + 12 + 4*nargs);
 657 }
 658
 659 static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr,
 660                                    target_ulong opcode, target_ulong *args)
 661 {
 662     CPUState *cs = CPU(cpu);
 663     target_ulong size = args[0];
 664     target_ulong addr = args[1];
 665
 666     switch (size) {
 667     case 1:
 668         args[0] = ldub_phys(cs->as, addr);
 669         return H_SUCCESS;
 670     case 2:
 671         args[0] = lduw_phys(cs->as, addr);
 672         return H_SUCCESS;
 673     case 4:
 674         args[0] = ldl_phys(cs->as, addr);
 675         return H_SUCCESS;
 676     case 8:
 677         args[0] = ldq_phys(cs->as, addr);
 678         return H_SUCCESS;
 679     }
 680     return H_PARAMETER;
 681 }
 682
 683 static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr,
 684                                     target_ulong opcode, target_ulong *args)
 685 {
 686     CPUState *cs = CPU(cpu);
 687
 688     target_ulong size = args[0];
 689     target_ulong addr = args[1];
 690     target_ulong val  = args[2];
 691
 692     switch (size) {
 693     case 1:
 694         stb_phys(cs->as, addr, val);
 695         return H_SUCCESS;
 696     case 2:
 697         stw_phys(cs->as, addr, val);
 698         return H_SUCCESS;
 699     case 4:
 700         stl_phys(cs->as, addr, val);
 701         return H_SUCCESS;
 702     case 8:
 703         stq_phys(cs->as, addr, val);
 704         return H_SUCCESS;
 705     }
 706     return H_PARAMETER;
 707 }
 708
 709 static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr,
 710                                     target_ulong opcode, target_ulong *args)
 711 {
 712     CPUState *cs = CPU(cpu);
 713
 714     target_ulong dst   = args[0]; /* Destination address */
 715     target_ulong src   = args[1]; /* Source address */
 716     target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */
 717     target_ulong count = args[3]; /* Element count */
 718     target_ulong op    = args[4]; /* 0 = copy, 1 = invert */
 719     uint64_t tmp;
 720     unsigned int mask = (1 << esize) - 1;
 721     int step = 1 << esize;
 722
 723     if (count > 0x80000000) {
 724         return H_PARAMETER;
 725     }
 726
 727     if ((dst & mask) || (src & mask) || (op > 1)) {
 728         return H_PARAMETER;
 729     }
 730
 731     if (dst >= src && dst < (src + (count << esize))) {
 732             dst = dst + ((count - 1) << esize);
 733             src = src + ((count - 1) << esize);
 734             step = -step;
 735     }
 736
 737     while (count--) {
 738         switch (esize) {
 739         case 0:
 740             tmp = ldub_phys(cs->as, src);
 741             break;
 742         case 1:
 743             tmp = lduw_phys(cs->as, src);
 744             break;
 745         case 2:
 746             tmp = ldl_phys(cs->as, src);
 747             break;
 748         case 3:
 749             tmp = ldq_phys(cs->as, src);
 750             break;
 751         default:
 752             return H_PARAMETER;
 753         }
 754         if (op == 1) {
 755             tmp = ~tmp;
 756         }
 757         switch (esize) {
 758         case 0:
 759             stb_phys(cs->as, dst, tmp);
 760             break;
 761         case 1:
 762             stw_phys(cs->as, dst, tmp);
 763             break;
 764         case 2:
 765             stl_phys(cs->as, dst, tmp);
 766             break;
 767         case 3:
 768             stq_phys(cs->as, dst, tmp);
 769             break;
 770         }
 771         dst = dst + step;
 772         src = src + step;
 773     }
 774
 775     return H_SUCCESS;
 776 }
 777
 778 static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr,
 779                                    target_ulong opcode, target_ulong *args)
 780 {
 781     /* Nothing to do on emulation, KVM will trap this in the kernel */
 782     return H_SUCCESS;
 783 }
 784
 785 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr,
 786                                    target_ulong opcode, target_ulong *args)
 787 {
 788     /* Nothing to do on emulation, KVM will trap this in the kernel */
 789     return H_SUCCESS;
 790 }
 791
 792 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu,
 793                                            SpaprMachineState *spapr,
 794                                            target_ulong mflags,
 795                                            target_ulong value1,
 796                                            target_ulong value2)
 797 {
 798     if (value1) {
 799         return H_P3;
 800     }
 801     if (value2) {
 802         return H_P4;
 803     }
 804
 805     switch (mflags) {
 806     case H_SET_MODE_ENDIAN_BIG:
 807         spapr_set_all_lpcrs(0, LPCR_ILE);
 808         spapr_pci_switch_vga(spapr, true);
 809         return H_SUCCESS;
 810
 811     case H_SET_MODE_ENDIAN_LITTLE:
 812         spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE);
 813         spapr_pci_switch_vga(spapr, false);
 814         return H_SUCCESS;
 815     }
 816
 817     return H_UNSUPPORTED_FLAG;
 818 }
 819
 820 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu,
 821                                                         SpaprMachineState *spapr,
 822                                                         target_ulong mflags,
 823                                                         target_ulong value1,
 824                                                         target_ulong value2)
 825 {
 826     if (value1) {
 827         return H_P3;
 828     }
 829
 830     if (value2) {
 831         return H_P4;
 832     }
 833
 834     /*
 835      * AIL-1 is not architected, and AIL-2 is not supported by QEMU spapr.
 836      * It is supported for faithful emulation of bare metal systems, but for
 837      * compatibility concerns we leave it out of the pseries machine.
 838      */
 839     if (mflags != 0 && mflags != 3) {
 840         return H_UNSUPPORTED_FLAG;
 841     }
 842
 843     if (mflags == 3) {
 844         if (!spapr_get_cap(spapr, SPAPR_CAP_AIL_MODE_3)) {
 845             return H_UNSUPPORTED_FLAG;
 846         }
 847     }
 848
 849     spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL);
 850
 851     return H_SUCCESS;
 852 }
 853
 854 static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr,
 855                                target_ulong opcode, target_ulong *args)
 856 {
 857     target_ulong resource = args[1];
 858     target_ulong ret = H_P2;
 859
 860     switch (resource) {
 861     case H_SET_MODE_RESOURCE_LE:
 862         ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]);
 863         break;
 864     case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE:
 865         ret = h_set_mode_resource_addr_trans_mode(cpu, spapr, args[0],
 866                                                   args[2], args[3]);
 867         break;
 868     }
 869
 870     return ret;
 871 }
 872
 873 static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr,
 874                                 target_ulong opcode, target_ulong *args)
 875 {
 876     qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n",
 877                   opcode, " (H_CLEAN_SLB)");
 878     return H_FUNCTION;
 879 }
 880
 881 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr,
 882                                      target_ulong opcode, target_ulong *args)
 883 {
 884     qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n",
 885                   opcode, " (H_INVALIDATE_PID)");
 886     return H_FUNCTION;
 887 }
 888
 889 static void spapr_check_setup_free_hpt(SpaprMachineState *spapr,
 890                                        uint64_t patbe_old, uint64_t patbe_new)
 891 {
 892     /*
 893      * We have 4 Options:
 894      * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing
 895      * HASH->RADIX                                  : Free HPT
 896      * RADIX->HASH                                  : Allocate HPT
 897      * NOTHING->HASH                                : Allocate HPT
 898      * Note: NOTHING implies the case where we said the guest could choose
 899      *       later and so assumed radix and now it's called H_REG_PROC_TBL
 900      */
 901
 902     if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) {
 903         /* We assume RADIX, so this catches all the "Do Nothing" cases */
 904     } else if (!(patbe_old & PATE1_GR)) {
 905         /* HASH->RADIX : Free HPT */
 906         spapr_free_hpt(spapr);
 907     } else if (!(patbe_new & PATE1_GR)) {
 908         /* RADIX->HASH || NOTHING->HASH : Allocate HPT */
 909         spapr_setup_hpt(spapr);
 910     }
 911     return;
 912 }
 913
 914 #define FLAGS_MASK              0x01FULL
 915 #define FLAG_MODIFY             0x10
 916 #define FLAG_REGISTER           0x08
 917 #define FLAG_RADIX              0x04
 918 #define FLAG_HASH_PROC_TBL      0x02
 919 #define FLAG_GTSE               0x01
 920
 921 static target_ulong h_register_process_table(PowerPCCPU *cpu,
 922                                              SpaprMachineState *spapr,
 923                                              target_ulong opcode,
 924                                              target_ulong *args)
 925 {
 926     target_ulong flags = args[0];
 927     target_ulong proc_tbl = args[1];
 928     target_ulong page_size = args[2];
 929     target_ulong table_size = args[3];
 930     target_ulong update_lpcr = 0;
 931     target_ulong table_byte_size;
 932     uint64_t cproc;
 933
 934     if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */
 935         return H_PARAMETER;
 936     }
 937     if (flags & FLAG_MODIFY) {
 938         if (flags & FLAG_REGISTER) {
 939             /* Check process table alignment */
 940             table_byte_size = 1ULL << (table_size + 12);
 941             if (proc_tbl & (table_byte_size - 1)) {
 942                 qemu_log_mask(LOG_GUEST_ERROR,
 943                     "%s: process table not properly aligned: proc_tbl 0x"
 944                     TARGET_FMT_lx" proc_tbl_size 0x"TARGET_FMT_lx"\n",
 945                     __func__, proc_tbl, table_byte_size);
 946             }
 947             if (flags & FLAG_RADIX) { /* Register new RADIX process table */
 948                 if (proc_tbl & 0xfff || proc_tbl >> 60) {
 949                     return H_P2;
 950                 } else if (page_size) {
 951                     return H_P3;
 952                 } else if (table_size > 24) {
 953                     return H_P4;
 954                 }
 955                 cproc = PATE1_GR | proc_tbl | table_size;
 956             } else { /* Register new HPT process table */
 957                 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */
 958                     /* TODO - Not Supported */
 959                     /* Technically caused by flag bits => H_PARAMETER */
 960                     return H_PARAMETER;
 961                 } else { /* Hash with SLB */
 962                     if (proc_tbl >> 38) {
 963                         return H_P2;
 964                     } else if (page_size & ~0x7) {
 965                         return H_P3;
 966                     } else if (table_size > 24) {
 967                         return H_P4;
 968                     }
 969                 }
 970                 cproc = (proc_tbl << 25) | page_size << 5 | table_size;
 971             }
 972
 973         } else { /* Deregister current process table */
 974             /*
 975              * Set to benign value: (current GR) | 0. This allows
 976              * deregistration in KVM to succeed even if the radix bit
 977              * in flags doesn't match the radix bit in the old PATE.
 978              */
 979             cproc = spapr->patb_entry & PATE1_GR;
 980         }
 981     } else { /* Maintain current registration */
 982         if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) {
 983             /* Technically caused by flag bits => H_PARAMETER */
 984             return H_PARAMETER; /* Existing Process Table Mismatch */
 985         }
 986         cproc = spapr->patb_entry;
 987     }
 988
 989     /* Check if we need to setup OR free the hpt */
 990     spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc);
 991
 992     spapr->patb_entry = cproc; /* Save new process table */
 993
 994     /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */
 995     if (flags & FLAG_RADIX)     /* Radix must use process tables, also set HR */
 996         update_lpcr |= (LPCR_UPRT | LPCR_HR);
 997     else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */
 998         update_lpcr |= LPCR_UPRT;
 999     if (flags & FLAG_GTSE)      /* Guest translation shootdown enable */
1000         update_lpcr |= LPCR_GTSE;
1001
1002     spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE);
1003
1004     if (kvm_enabled()) {
1005         return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX,
1006                                        flags & FLAG_GTSE, cproc);
1007     }
1008     return H_SUCCESS;
1009 }
1010
1011 #define H_SIGNAL_SYS_RESET_ALL         -1
1012 #define H_SIGNAL_SYS_RESET_ALLBUTSELF  -2
1013
1014 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu,
1015                                        SpaprMachineState *spapr,
1016                                        target_ulong opcode, target_ulong *args)
1017 {
1018     target_long target = args[0];
1019     CPUState *cs;
1020
1021     if (target < 0) {
1022         /* Broadcast */
1023         if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) {
1024             return H_PARAMETER;
1025         }
1026
1027         CPU_FOREACH(cs) {
1028             PowerPCCPU *c = POWERPC_CPU(cs);
1029
1030             if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) {
1031                 if (c == cpu) {
1032                     continue;
1033                 }
1034             }
1035             run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
1036         }
1037         return H_SUCCESS;
1038
1039     } else {
1040         /* Unicast */
1041         cs = CPU(spapr_find_cpu(target));
1042         if (cs) {
1043             run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
1044             return H_SUCCESS;
1045         }
1046         return H_PARAMETER;
1047     }
1048 }
1049
1050 /* Returns either a logical PVR or zero if none was found */
1051 static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat,
1052                               target_ulong *addr, bool *raw_mode_supported)
1053 {
1054     bool explicit_match = false; /* Matched the CPU's real PVR */
1055     uint32_t best_compat = 0;
1056     int i;
1057
1058     /*
1059      * We scan the supplied table of PVRs looking for two things
1060      *   1. Is our real CPU PVR in the list?
1061      *   2. What's the "best" listed logical PVR
1062      */
1063     for (i = 0; i < 512; ++i) {
1064         uint32_t pvr, pvr_mask;
1065
1066         pvr_mask = ldl_be_phys(&address_space_memory, *addr);
1067         pvr = ldl_be_phys(&address_space_memory, *addr + 4);
1068         *addr += 8;
1069
1070         if (~pvr_mask & pvr) {
1071             break; /* Terminator record */
1072         }
1073
1074         if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) {
1075             explicit_match = true;
1076         } else {
1077             if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) {
1078                 best_compat = pvr;
1079             }
1080         }
1081     }
1082
1083     *raw_mode_supported = explicit_match;
1084
1085     /* Parsing finished */
1086     trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat);
1087
1088     return best_compat;
1089 }
1090
1091 static
1092 target_ulong do_client_architecture_support(PowerPCCPU *cpu,
1093                                             SpaprMachineState *spapr,
1094                                             target_ulong vec,
1095                                             target_ulong fdt_bufsize)
1096 {
1097     target_ulong ov_table; /* Working address in data buffer */
1098     uint32_t cas_pvr;
1099     SpaprOptionVector *ov1_guest, *ov5_guest;
1100     bool guest_radix;
1101     bool raw_mode_supported = false;
1102     bool guest_xive;
1103     CPUState *cs;
1104     void *fdt;
1105     uint32_t max_compat = spapr->max_compat_pvr;
1106
1107     /* CAS is supposed to be called early when only the boot vCPU is active. */
1108     CPU_FOREACH(cs) {
1109         if (cs == CPU(cpu)) {
1110             continue;
1111         }
1112         if (!cs->halted) {
1113             warn_report("guest has multiple active vCPUs at CAS, which is not allowed");
1114             return H_MULTI_THREADS_ACTIVE;
1115         }
1116     }
1117
1118     cas_pvr = cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported);
1119     if (!cas_pvr && (!raw_mode_supported || max_compat)) {
1120         /*
1121          * We couldn't find a suitable compatibility mode, and either
1122          * the guest doesn't support "raw" mode for this CPU, or "raw"
1123          * mode is disabled because a maximum compat mode is set.
1124          */
1125         error_report("Couldn't negotiate a suitable PVR during CAS");
1126         return H_HARDWARE;
1127     }
1128
1129     /* Update CPUs */
1130     if (cpu->compat_pvr != cas_pvr) {
1131         Error *local_err = NULL;
1132
1133         if (ppc_set_compat_all(cas_pvr, &local_err) < 0) {
1134             /* We fail to set compat mode (likely because running with KVM PR),
1135              * but maybe we can fallback to raw mode if the guest supports it.
1136              */
1137             if (!raw_mode_supported) {
1138                 error_report_err(local_err);
1139                 return H_HARDWARE;
1140             }
1141             error_free(local_err);
1142         }
1143     }
1144
1145     /* For the future use: here @ov_table points to the first option vector */
1146     ov_table = vec;
1147
1148     ov1_guest = spapr_ovec_parse_vector(ov_table, 1);
1149     if (!ov1_guest) {
1150         warn_report("guest didn't provide option vector 1");
1151         return H_PARAMETER;
1152     }
1153     ov5_guest = spapr_ovec_parse_vector(ov_table, 5);
1154     if (!ov5_guest) {
1155         spapr_ovec_cleanup(ov1_guest);
1156         warn_report("guest didn't provide option vector 5");
1157         return H_PARAMETER;
1158     }
1159     if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) {
1160         error_report("guest requested hash and radix MMU, which is invalid.");
1161         exit(EXIT_FAILURE);
1162     }
1163     if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) {
1164         error_report("guest requested an invalid interrupt mode");
1165         exit(EXIT_FAILURE);
1166     }
1167
1168     guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300);
1169
1170     guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT);
1171
1172     /*
1173      * HPT resizing is a bit of a special case, because when enabled
1174      * we assume an HPT guest will support it until it says it
1175      * doesn't, instead of assuming it won't support it until it says
1176      * it does.  Strictly speaking that approach could break for
1177      * guests which don't make a CAS call, but those are so old we
1178      * don't care about them.  Without that assumption we'd have to
1179      * make at least a temporary allocation of an HPT sized for max
1180      * memory, which could be impossibly difficult under KVM HV if
1181      * maxram is large.
1182      */
1183     if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) {
1184         int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1185
1186         if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) {
1187             error_report(
1188                 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required");
1189             exit(1);
1190         }
1191
1192         if (spapr->htab_shift < maxshift) {
1193             /* Guest doesn't know about HPT resizing, so we
1194              * pre-emptively resize for the maximum permitted RAM.  At
1195              * the point this is called, nothing should have been
1196              * entered into the existing HPT */
1197             spapr_reallocate_hpt(spapr, maxshift, &error_fatal);
1198             push_sregs_to_kvm_pr(spapr);
1199         }
1200     }
1201
1202     /* NOTE: there are actually a number of ov5 bits where input from the
1203      * guest is always zero, and the platform/QEMU enables them independently
1204      * of guest input. To model these properly we'd want some sort of mask,
1205      * but since they only currently apply to memory migration as defined
1206      * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need
1207      * to worry about this for now.
1208      */
1209
1210     /* full range of negotiated ov5 capabilities */
1211     spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest);
1212     spapr_ovec_cleanup(ov5_guest);
1213
1214     spapr_check_mmu_mode(guest_radix);
1215
1216     spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00);
1217     spapr_ovec_cleanup(ov1_guest);
1218
1219     /*
1220      * Check for NUMA affinity conditions now that we know which NUMA
1221      * affinity the guest will use.
1222      */
1223     spapr_numa_associativity_check(spapr);
1224
1225     /*
1226      * Ensure the guest asks for an interrupt mode we support;
1227      * otherwise terminate the boot.
1228      */
1229     if (guest_xive) {
1230         if (!spapr->irq->xive) {
1231             error_report(
1232 "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property");
1233             exit(EXIT_FAILURE);
1234         }
1235     } else {
1236         if (!spapr->irq->xics) {
1237             error_report(
1238 "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual");
1239             exit(EXIT_FAILURE);
1240         }
1241     }
1242
1243     spapr_irq_update_active_intc(spapr);
1244
1245     /*
1246      * Process all pending hot-plug/unplug requests now. An updated full
1247      * rendered FDT will be returned to the guest.
1248      */
1249     spapr_drc_reset_all(spapr);
1250     spapr_clear_pending_hotplug_events(spapr);
1251
1252     /*
1253      * If spapr_machine_reset() did not set up a HPT but one is necessary
1254      * (because the guest isn't going to use radix) then set it up here.
1255      */
1256     if ((spapr->patb_entry & PATE1_GR) && !guest_radix) {
1257         /* legacy hash or new hash: */
1258         spapr_setup_hpt(spapr);
1259     }
1260
1261     fdt = spapr_build_fdt(spapr, spapr->vof != NULL, fdt_bufsize);
1262     g_free(spapr->fdt_blob);
1263     spapr->fdt_size = fdt_totalsize(fdt);
1264     spapr->fdt_initial_size = spapr->fdt_size;
1265     spapr->fdt_blob = fdt;
1266
1267     /*
1268      * Set the machine->fdt pointer again since we just freed
1269      * it above (by freeing spapr->fdt_blob). We set this
1270      * pointer to enable support for the 'dumpdtb' QMP/HMP
1271      * command.
1272      */
1273     MACHINE(spapr)->fdt = fdt;
1274
1275     return H_SUCCESS;
1276 }
1277
1278 static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
1279                                                   SpaprMachineState *spapr,
1280                                                   target_ulong opcode,
1281                                                   target_ulong *args)
1282 {
1283     target_ulong vec = ppc64_phys_to_real(args[0]);
1284     target_ulong fdt_buf = args[1];
1285     target_ulong fdt_bufsize = args[2];
1286     target_ulong ret;
1287     SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 };
1288
1289     if (fdt_bufsize < sizeof(hdr)) {
1290         error_report("SLOF provided insufficient CAS buffer "
1291                      TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr));
1292         exit(EXIT_FAILURE);
1293     }
1294
1295     fdt_bufsize -= sizeof(hdr);
1296
1297     ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize);
1298     if (ret == H_SUCCESS) {
1299         _FDT((fdt_pack(spapr->fdt_blob)));
1300         spapr->fdt_size = fdt_totalsize(spapr->fdt_blob);
1301         spapr->fdt_initial_size = spapr->fdt_size;
1302
1303         cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr));
1304         cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob,
1305                                   spapr->fdt_size);
1306         trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr));
1307     }
1308
1309     return ret;
1310 }
1311
1312 target_ulong spapr_vof_client_architecture_support(MachineState *ms,
1313                                                    CPUState *cs,
1314                                                    target_ulong ovec_addr)
1315 {
1316     SpaprMachineState *spapr = SPAPR_MACHINE(ms);
1317
1318     target_ulong ret = do_client_architecture_support(POWERPC_CPU(cs), spapr,
1319                                                       ovec_addr, FDT_MAX_SIZE);
1320
1321     /*
1322      * This adds stdout and generates phandles for boottime and CAS FDTs.
1323      * It is alright to update the FDT here as do_client_architecture_support()
1324      * does not pack it.
1325      */
1326     spapr_vof_client_dt_finalize(spapr, spapr->fdt_blob);
1327
1328     return ret;
1329 }
1330
1331 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu,
1332                                               SpaprMachineState *spapr,
1333                                               target_ulong opcode,
1334                                               target_ulong *args)
1335 {
1336     uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS &
1337                                ~H_CPU_CHAR_THR_RECONF_TRIG;
1338     uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY;
1339     uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC);
1340     uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC);
1341     uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS);
1342     uint8_t count_cache_flush_assist = spapr_get_cap(spapr,
1343                                                      SPAPR_CAP_CCF_ASSIST);
1344
1345     switch (safe_cache) {
1346     case SPAPR_CAP_WORKAROUND:
1347         characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30;
1348         characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2;
1349         characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV;
1350         behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR;
1351         break;
1352     case SPAPR_CAP_FIXED:
1353         behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY;
1354         behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS;
1355         break;
1356     default: /* broken */
1357         assert(safe_cache == SPAPR_CAP_BROKEN);
1358         behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR;
1359         break;
1360     }
1361
1362     switch (safe_bounds_check) {
1363     case SPAPR_CAP_WORKAROUND:
1364         characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31;
1365         behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR;
1366         break;
1367     case SPAPR_CAP_FIXED:
1368         break;
1369     default: /* broken */
1370         assert(safe_bounds_check == SPAPR_CAP_BROKEN);
1371         behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR;
1372         break;
1373     }
1374
1375     switch (safe_indirect_branch) {
1376     case SPAPR_CAP_FIXED_NA:
1377         break;
1378     case SPAPR_CAP_FIXED_CCD:
1379         characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS;
1380         break;
1381     case SPAPR_CAP_FIXED_IBS:
1382         characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED;
1383         break;
1384     case SPAPR_CAP_WORKAROUND:
1385         behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE;
1386         if (count_cache_flush_assist) {
1387             characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST;
1388         }
1389         break;
1390     default: /* broken */
1391         assert(safe_indirect_branch == SPAPR_CAP_BROKEN);
1392         break;
1393     }
1394
1395     args[0] = characteristics;
1396     args[1] = behaviour;
1397     return H_SUCCESS;
1398 }
1399
1400 static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr,
1401                                 target_ulong opcode, target_ulong *args)
1402 {
1403     target_ulong dt = ppc64_phys_to_real(args[0]);
1404     struct fdt_header hdr = { 0 };
1405     unsigned cb;
1406     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
1407     void *fdt;
1408
1409     cpu_physical_memory_read(dt, &hdr, sizeof(hdr));
1410     cb = fdt32_to_cpu(hdr.totalsize);
1411
1412     if (!smc->update_dt_enabled) {
1413         return H_SUCCESS;
1414     }
1415
1416     /* Check that the fdt did not grow out of proportion */
1417     if (cb > spapr->fdt_initial_size * 2) {
1418         trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb,
1419                                           fdt32_to_cpu(hdr.magic));
1420         return H_PARAMETER;
1421     }
1422
1423     fdt = g_malloc0(cb);
1424     cpu_physical_memory_read(dt, fdt, cb);
1425
1426     /* Check the fdt consistency */
1427     if (fdt_check_full(fdt, cb)) {
1428         trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb,
1429                                            fdt32_to_cpu(hdr.magic));
1430         return H_PARAMETER;
1431     }
1432
1433     g_free(spapr->fdt_blob);
1434     spapr->fdt_size = cb;
1435     spapr->fdt_blob = fdt;
1436     trace_spapr_update_dt(cb);
1437
1438     return H_SUCCESS;
1439 }
1440
1441 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
1442 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1];
1443 static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1];
1444
1445 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
1446 {
1447     spapr_hcall_fn *slot;
1448
1449     if (opcode <= MAX_HCALL_OPCODE) {
1450         assert((opcode & 0x3) == 0);
1451
1452         slot = &papr_hypercall_table[opcode / 4];
1453     } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) {
1454         /* we only have SVM-related hcall numbers assigned in multiples of 4 */
1455         assert((opcode & 0x3) == 0);
1456
1457         slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4];
1458     } else {
1459         assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
1460
1461         slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
1462     }
1463
1464     assert(!(*slot));
1465     *slot = fn;
1466 }
1467
1468 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
1469                              target_ulong *args)
1470 {
1471     SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1472
1473     if ((opcode <= MAX_HCALL_OPCODE)
1474         && ((opcode & 0x3) == 0)) {
1475         spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
1476
1477         if (fn) {
1478             return fn(cpu, spapr, opcode, args);
1479         }
1480     } else if ((opcode >= SVM_HCALL_BASE) &&
1481                (opcode <= SVM_HCALL_MAX)) {
1482         spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4];
1483
1484         if (fn) {
1485             return fn(cpu, spapr, opcode, args);
1486         }
1487     } else if ((opcode >= KVMPPC_HCALL_BASE) &&
1488                (opcode <= KVMPPC_HCALL_MAX)) {
1489         spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
1490
1491         if (fn) {
1492             return fn(cpu, spapr, opcode, args);
1493         }
1494     }
1495
1496     qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n",
1497                   opcode);
1498     return H_FUNCTION;
1499 }
1500
1501 #ifdef CONFIG_TCG
1502 static void hypercall_register_softmmu(void)
1503 {
1504     /* DO NOTHING */
1505 }
1506 #else
1507 static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr,
1508                             target_ulong opcode, target_ulong *args)
1509 {
1510     g_assert_not_reached();
1511 }
1512
1513 static void hypercall_register_softmmu(void)
1514 {
1515     /* hcall-pft */
1516     spapr_register_hypercall(H_ENTER, h_softmmu);
1517     spapr_register_hypercall(H_REMOVE, h_softmmu);
1518     spapr_register_hypercall(H_PROTECT, h_softmmu);
1519     spapr_register_hypercall(H_READ, h_softmmu);
1520
1521     /* hcall-bulk */
1522     spapr_register_hypercall(H_BULK_REMOVE, h_softmmu);
1523 }
1524 #endif
1525
1526 static void hypercall_register_types(void)
1527 {
1528     hypercall_register_softmmu();
1529
1530     /* hcall-hpt-resize */
1531     spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare);
1532     spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit);
1533
1534     /* hcall-splpar */
1535     spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa);
1536     spapr_register_hypercall(H_CEDE, h_cede);
1537     spapr_register_hypercall(H_CONFER, h_confer);
1538     spapr_register_hypercall(H_PROD, h_prod);
1539
1540     /* hcall-join */
1541     spapr_register_hypercall(H_JOIN, h_join);
1542
1543     spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset);
1544
1545     /* processor register resource access h-calls */
1546     spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0);
1547     spapr_register_hypercall(H_SET_DABR, h_set_dabr);
1548     spapr_register_hypercall(H_SET_XDABR, h_set_xdabr);
1549     spapr_register_hypercall(H_PAGE_INIT, h_page_init);
1550     spapr_register_hypercall(H_SET_MODE, h_set_mode);
1551
1552     /* In Memory Table MMU h-calls */
1553     spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb);
1554     spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid);
1555     spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table);
1556
1557     /* hcall-get-cpu-characteristics */
1558     spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS,
1559                              h_get_cpu_characteristics);
1560
1561     /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
1562      * here between the "CI" and the "CACHE" variants, they will use whatever
1563      * mapping attributes qemu is using. When using KVM, the kernel will
1564      * enforce the attributes more strongly
1565      */
1566     spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load);
1567     spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store);
1568     spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load);
1569     spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store);
1570     spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi);
1571     spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf);
1572     spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop);
1573
1574     /* qemu/KVM-PPC specific hcalls */
1575     spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
1576
1577     /* ibm,client-architecture-support support */
1578     spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support);
1579
1580     spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt);
1581
1582     spapr_register_nested();
1583 }
1584
1585 type_init(hypercall_register_types)