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spapr: Implement H_CONFER
[mirror_qemu.git] / hw / ppc / spapr_hcall.c
1 #include "qemu/osdep.h"
2 #include "qapi/error.h"
3 #include "sysemu/hw_accel.h"
4 #include "sysemu/runstate.h"
5 #include "qemu/log.h"
6 #include "qemu/main-loop.h"
7 #include "qemu/module.h"
8 #include "qemu/error-report.h"
9 #include "cpu.h"
10 #include "exec/exec-all.h"
11 #include "helper_regs.h"
12 #include "hw/ppc/spapr.h"
13 #include "hw/ppc/spapr_cpu_core.h"
14 #include "mmu-hash64.h"
15 #include "cpu-models.h"
16 #include "trace.h"
17 #include "kvm_ppc.h"
18 #include "hw/ppc/spapr_ovec.h"
19 #include "mmu-book3s-v3.h"
20 #include "hw/mem/memory-device.h"
21
22 static bool has_spr(PowerPCCPU *cpu, int spr)
23 {
24 /* We can test whether the SPR is defined by checking for a valid name */
25 return cpu->env.spr_cb[spr].name != NULL;
26 }
27
28 static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex)
29 {
30 /*
31 * hash value/pteg group index is normalized by HPT mask
32 */
33 if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) {
34 return false;
35 }
36 return true;
37 }
38
39 static bool is_ram_address(SpaprMachineState *spapr, hwaddr addr)
40 {
41 MachineState *machine = MACHINE(spapr);
42 DeviceMemoryState *dms = machine->device_memory;
43
44 if (addr < machine->ram_size) {
45 return true;
46 }
47 if ((addr >= dms->base)
48 && ((addr - dms->base) < memory_region_size(&dms->mr))) {
49 return true;
50 }
51
52 return false;
53 }
54
55 static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr,
56 target_ulong opcode, target_ulong *args)
57 {
58 target_ulong flags = args[0];
59 target_ulong ptex = args[1];
60 target_ulong pteh = args[2];
61 target_ulong ptel = args[3];
62 unsigned apshift;
63 target_ulong raddr;
64 target_ulong slot;
65 const ppc_hash_pte64_t *hptes;
66
67 apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel);
68 if (!apshift) {
69 /* Bad page size encoding */
70 return H_PARAMETER;
71 }
72
73 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
74
75 if (is_ram_address(spapr, raddr)) {
76 /* Regular RAM - should have WIMG=0010 */
77 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) {
78 return H_PARAMETER;
79 }
80 } else {
81 target_ulong wimg_flags;
82 /* Looks like an IO address */
83 /* FIXME: What WIMG combinations could be sensible for IO?
84 * For now we allow WIMG=010x, but are there others? */
85 /* FIXME: Should we check against registered IO addresses? */
86 wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M));
87
88 if (wimg_flags != HPTE64_R_I &&
89 wimg_flags != (HPTE64_R_I | HPTE64_R_M)) {
90 return H_PARAMETER;
91 }
92 }
93
94 pteh &= ~0x60ULL;
95
96 if (!valid_ptex(cpu, ptex)) {
97 return H_PARAMETER;
98 }
99
100 slot = ptex & 7ULL;
101 ptex = ptex & ~7ULL;
102
103 if (likely((flags & H_EXACT) == 0)) {
104 hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
105 for (slot = 0; slot < 8; slot++) {
106 if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) {
107 break;
108 }
109 }
110 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
111 if (slot == 8) {
112 return H_PTEG_FULL;
113 }
114 } else {
115 hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1);
116 if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) {
117 ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1);
118 return H_PTEG_FULL;
119 }
120 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
121 }
122
123 spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel);
124
125 args[0] = ptex + slot;
126 return H_SUCCESS;
127 }
128
129 typedef enum {
130 REMOVE_SUCCESS = 0,
131 REMOVE_NOT_FOUND = 1,
132 REMOVE_PARM = 2,
133 REMOVE_HW = 3,
134 } RemoveResult;
135
136 static RemoveResult remove_hpte(PowerPCCPU *cpu
137 , target_ulong ptex,
138 target_ulong avpn,
139 target_ulong flags,
140 target_ulong *vp, target_ulong *rp)
141 {
142 const ppc_hash_pte64_t *hptes;
143 target_ulong v, r;
144
145 if (!valid_ptex(cpu, ptex)) {
146 return REMOVE_PARM;
147 }
148
149 hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
150 v = ppc_hash64_hpte0(cpu, hptes, 0);
151 r = ppc_hash64_hpte1(cpu, hptes, 0);
152 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
153
154 if ((v & HPTE64_V_VALID) == 0 ||
155 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
156 ((flags & H_ANDCOND) && (v & avpn) != 0)) {
157 return REMOVE_NOT_FOUND;
158 }
159 *vp = v;
160 *rp = r;
161 spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0);
162 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
163 return REMOVE_SUCCESS;
164 }
165
166 static target_ulong h_remove(PowerPCCPU *cpu, SpaprMachineState *spapr,
167 target_ulong opcode, target_ulong *args)
168 {
169 CPUPPCState *env = &cpu->env;
170 target_ulong flags = args[0];
171 target_ulong ptex = args[1];
172 target_ulong avpn = args[2];
173 RemoveResult ret;
174
175 ret = remove_hpte(cpu, ptex, avpn, flags,
176 &args[0], &args[1]);
177
178 switch (ret) {
179 case REMOVE_SUCCESS:
180 check_tlb_flush(env, true);
181 return H_SUCCESS;
182
183 case REMOVE_NOT_FOUND:
184 return H_NOT_FOUND;
185
186 case REMOVE_PARM:
187 return H_PARAMETER;
188
189 case REMOVE_HW:
190 return H_HARDWARE;
191 }
192
193 g_assert_not_reached();
194 }
195
196 #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL
197 #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL
198 #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL
199 #define H_BULK_REMOVE_END 0xc000000000000000ULL
200 #define H_BULK_REMOVE_CODE 0x3000000000000000ULL
201 #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL
202 #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL
203 #define H_BULK_REMOVE_PARM 0x2000000000000000ULL
204 #define H_BULK_REMOVE_HW 0x3000000000000000ULL
205 #define H_BULK_REMOVE_RC 0x0c00000000000000ULL
206 #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL
207 #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL
208 #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL
209 #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL
210 #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL
211
212 #define H_BULK_REMOVE_MAX_BATCH 4
213
214 static target_ulong h_bulk_remove(PowerPCCPU *cpu, SpaprMachineState *spapr,
215 target_ulong opcode, target_ulong *args)
216 {
217 CPUPPCState *env = &cpu->env;
218 int i;
219 target_ulong rc = H_SUCCESS;
220
221 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
222 target_ulong *tsh = &args[i*2];
223 target_ulong tsl = args[i*2 + 1];
224 target_ulong v, r, ret;
225
226 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
227 break;
228 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) {
229 return H_PARAMETER;
230 }
231
232 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS;
233 *tsh |= H_BULK_REMOVE_RESPONSE;
234
235 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
236 *tsh |= H_BULK_REMOVE_PARM;
237 return H_PARAMETER;
238 }
239
240 ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl,
241 (*tsh & H_BULK_REMOVE_FLAGS) >> 26,
242 &v, &r);
243
244 *tsh |= ret << 60;
245
246 switch (ret) {
247 case REMOVE_SUCCESS:
248 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43;
249 break;
250
251 case REMOVE_PARM:
252 rc = H_PARAMETER;
253 goto exit;
254
255 case REMOVE_HW:
256 rc = H_HARDWARE;
257 goto exit;
258 }
259 }
260 exit:
261 check_tlb_flush(env, true);
262
263 return rc;
264 }
265
266 static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr,
267 target_ulong opcode, target_ulong *args)
268 {
269 CPUPPCState *env = &cpu->env;
270 target_ulong flags = args[0];
271 target_ulong ptex = args[1];
272 target_ulong avpn = args[2];
273 const ppc_hash_pte64_t *hptes;
274 target_ulong v, r;
275
276 if (!valid_ptex(cpu, ptex)) {
277 return H_PARAMETER;
278 }
279
280 hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
281 v = ppc_hash64_hpte0(cpu, hptes, 0);
282 r = ppc_hash64_hpte1(cpu, hptes, 0);
283 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
284
285 if ((v & HPTE64_V_VALID) == 0 ||
286 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
287 return H_NOT_FOUND;
288 }
289
290 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N |
291 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO);
292 r |= (flags << 55) & HPTE64_R_PP0;
293 r |= (flags << 48) & HPTE64_R_KEY_HI;
294 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
295 spapr_store_hpte(cpu, ptex,
296 (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);
297 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
298 /* Flush the tlb */
299 check_tlb_flush(env, true);
300 /* Don't need a memory barrier, due to qemu's global lock */
301 spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r);
302 return H_SUCCESS;
303 }
304
305 static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr,
306 target_ulong opcode, target_ulong *args)
307 {
308 target_ulong flags = args[0];
309 target_ulong ptex = args[1];
310 int i, ridx, n_entries = 1;
311 const ppc_hash_pte64_t *hptes;
312
313 if (!valid_ptex(cpu, ptex)) {
314 return H_PARAMETER;
315 }
316
317 if (flags & H_READ_4) {
318 /* Clear the two low order bits */
319 ptex &= ~(3ULL);
320 n_entries = 4;
321 }
322
323 hptes = ppc_hash64_map_hptes(cpu, ptex, n_entries);
324 for (i = 0, ridx = 0; i < n_entries; i++) {
325 args[ridx++] = ppc_hash64_hpte0(cpu, hptes, i);
326 args[ridx++] = ppc_hash64_hpte1(cpu, hptes, i);
327 }
328 ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries);
329
330 return H_SUCCESS;
331 }
332
333 struct SpaprPendingHpt {
334 /* These fields are read-only after initialization */
335 int shift;
336 QemuThread thread;
337
338 /* These fields are protected by the BQL */
339 bool complete;
340
341 /* These fields are private to the preparation thread if
342 * !complete, otherwise protected by the BQL */
343 int ret;
344 void *hpt;
345 };
346
347 static void free_pending_hpt(SpaprPendingHpt *pending)
348 {
349 if (pending->hpt) {
350 qemu_vfree(pending->hpt);
351 }
352
353 g_free(pending);
354 }
355
356 static void *hpt_prepare_thread(void *opaque)
357 {
358 SpaprPendingHpt *pending = opaque;
359 size_t size = 1ULL << pending->shift;
360
361 pending->hpt = qemu_memalign(size, size);
362 if (pending->hpt) {
363 memset(pending->hpt, 0, size);
364 pending->ret = H_SUCCESS;
365 } else {
366 pending->ret = H_NO_MEM;
367 }
368
369 qemu_mutex_lock_iothread();
370
371 if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) {
372 /* Ready to go */
373 pending->complete = true;
374 } else {
375 /* We've been cancelled, clean ourselves up */
376 free_pending_hpt(pending);
377 }
378
379 qemu_mutex_unlock_iothread();
380 return NULL;
381 }
382
383 /* Must be called with BQL held */
384 static void cancel_hpt_prepare(SpaprMachineState *spapr)
385 {
386 SpaprPendingHpt *pending = spapr->pending_hpt;
387
388 /* Let the thread know it's cancelled */
389 spapr->pending_hpt = NULL;
390
391 if (!pending) {
392 /* Nothing to do */
393 return;
394 }
395
396 if (!pending->complete) {
397 /* thread will clean itself up */
398 return;
399 }
400
401 free_pending_hpt(pending);
402 }
403
404 /* Convert a return code from the KVM ioctl()s implementing resize HPT
405 * into a PAPR hypercall return code */
406 static target_ulong resize_hpt_convert_rc(int ret)
407 {
408 if (ret >= 100000) {
409 return H_LONG_BUSY_ORDER_100_SEC;
410 } else if (ret >= 10000) {
411 return H_LONG_BUSY_ORDER_10_SEC;
412 } else if (ret >= 1000) {
413 return H_LONG_BUSY_ORDER_1_SEC;
414 } else if (ret >= 100) {
415 return H_LONG_BUSY_ORDER_100_MSEC;
416 } else if (ret >= 10) {
417 return H_LONG_BUSY_ORDER_10_MSEC;
418 } else if (ret > 0) {
419 return H_LONG_BUSY_ORDER_1_MSEC;
420 }
421
422 switch (ret) {
423 case 0:
424 return H_SUCCESS;
425 case -EPERM:
426 return H_AUTHORITY;
427 case -EINVAL:
428 return H_PARAMETER;
429 case -ENXIO:
430 return H_CLOSED;
431 case -ENOSPC:
432 return H_PTEG_FULL;
433 case -EBUSY:
434 return H_BUSY;
435 case -ENOMEM:
436 return H_NO_MEM;
437 default:
438 return H_HARDWARE;
439 }
440 }
441
442 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu,
443 SpaprMachineState *spapr,
444 target_ulong opcode,
445 target_ulong *args)
446 {
447 target_ulong flags = args[0];
448 int shift = args[1];
449 SpaprPendingHpt *pending = spapr->pending_hpt;
450 uint64_t current_ram_size;
451 int rc;
452
453 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
454 return H_AUTHORITY;
455 }
456
457 if (!spapr->htab_shift) {
458 /* Radix guest, no HPT */
459 return H_NOT_AVAILABLE;
460 }
461
462 trace_spapr_h_resize_hpt_prepare(flags, shift);
463
464 if (flags != 0) {
465 return H_PARAMETER;
466 }
467
468 if (shift && ((shift < 18) || (shift > 46))) {
469 return H_PARAMETER;
470 }
471
472 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
473
474 /* We only allow the guest to allocate an HPT one order above what
475 * we'd normally give them (to stop a small guest claiming a huge
476 * chunk of resources in the HPT */
477 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) {
478 return H_RESOURCE;
479 }
480
481 rc = kvmppc_resize_hpt_prepare(cpu, flags, shift);
482 if (rc != -ENOSYS) {
483 return resize_hpt_convert_rc(rc);
484 }
485
486 if (pending) {
487 /* something already in progress */
488 if (pending->shift == shift) {
489 /* and it's suitable */
490 if (pending->complete) {
491 return pending->ret;
492 } else {
493 return H_LONG_BUSY_ORDER_100_MSEC;
494 }
495 }
496
497 /* not suitable, cancel and replace */
498 cancel_hpt_prepare(spapr);
499 }
500
501 if (!shift) {
502 /* nothing to do */
503 return H_SUCCESS;
504 }
505
506 /* start new prepare */
507
508 pending = g_new0(SpaprPendingHpt, 1);
509 pending->shift = shift;
510 pending->ret = H_HARDWARE;
511
512 qemu_thread_create(&pending->thread, "sPAPR HPT prepare",
513 hpt_prepare_thread, pending, QEMU_THREAD_DETACHED);
514
515 spapr->pending_hpt = pending;
516
517 /* In theory we could estimate the time more accurately based on
518 * the new size, but there's not much point */
519 return H_LONG_BUSY_ORDER_100_MSEC;
520 }
521
522 static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot)
523 {
524 uint8_t *addr = htab;
525
526 addr += pteg * HASH_PTEG_SIZE_64;
527 addr += slot * HASH_PTE_SIZE_64;
528 return ldq_p(addr);
529 }
530
531 static void new_hpte_store(void *htab, uint64_t pteg, int slot,
532 uint64_t pte0, uint64_t pte1)
533 {
534 uint8_t *addr = htab;
535
536 addr += pteg * HASH_PTEG_SIZE_64;
537 addr += slot * HASH_PTE_SIZE_64;
538
539 stq_p(addr, pte0);
540 stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1);
541 }
542
543 static int rehash_hpte(PowerPCCPU *cpu,
544 const ppc_hash_pte64_t *hptes,
545 void *old_hpt, uint64_t oldsize,
546 void *new_hpt, uint64_t newsize,
547 uint64_t pteg, int slot)
548 {
549 uint64_t old_hash_mask = (oldsize >> 7) - 1;
550 uint64_t new_hash_mask = (newsize >> 7) - 1;
551 target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot);
552 target_ulong pte1;
553 uint64_t avpn;
554 unsigned base_pg_shift;
555 uint64_t hash, new_pteg, replace_pte0;
556
557 if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) {
558 return H_SUCCESS;
559 }
560
561 pte1 = ppc_hash64_hpte1(cpu, hptes, slot);
562
563 base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1);
564 assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */
565 avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23);
566
567 if (pte0 & HPTE64_V_SECONDARY) {
568 pteg = ~pteg;
569 }
570
571 if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) {
572 uint64_t offset, vsid;
573
574 /* We only have 28 - 23 bits of offset in avpn */
575 offset = (avpn & 0x1f) << 23;
576 vsid = avpn >> 5;
577 /* We can find more bits from the pteg value */
578 if (base_pg_shift < 23) {
579 offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift;
580 }
581
582 hash = vsid ^ (offset >> base_pg_shift);
583 } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) {
584 uint64_t offset, vsid;
585
586 /* We only have 40 - 23 bits of seg_off in avpn */
587 offset = (avpn & 0x1ffff) << 23;
588 vsid = avpn >> 17;
589 if (base_pg_shift < 23) {
590 offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask)
591 << base_pg_shift;
592 }
593
594 hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift);
595 } else {
596 error_report("rehash_pte: Bad segment size in HPTE");
597 return H_HARDWARE;
598 }
599
600 new_pteg = hash & new_hash_mask;
601 if (pte0 & HPTE64_V_SECONDARY) {
602 assert(~pteg == (hash & old_hash_mask));
603 new_pteg = ~new_pteg;
604 } else {
605 assert(pteg == (hash & old_hash_mask));
606 }
607 assert((oldsize != newsize) || (pteg == new_pteg));
608 replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot);
609 /*
610 * Strictly speaking, we don't need all these tests, since we only
611 * ever rehash bolted HPTEs. We might in future handle non-bolted
612 * HPTEs, though so make the logic correct for those cases as
613 * well.
614 */
615 if (replace_pte0 & HPTE64_V_VALID) {
616 assert(newsize < oldsize);
617 if (replace_pte0 & HPTE64_V_BOLTED) {
618 if (pte0 & HPTE64_V_BOLTED) {
619 /* Bolted collision, nothing we can do */
620 return H_PTEG_FULL;
621 } else {
622 /* Discard this hpte */
623 return H_SUCCESS;
624 }
625 }
626 }
627
628 new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1);
629 return H_SUCCESS;
630 }
631
632 static int rehash_hpt(PowerPCCPU *cpu,
633 void *old_hpt, uint64_t oldsize,
634 void *new_hpt, uint64_t newsize)
635 {
636 uint64_t n_ptegs = oldsize >> 7;
637 uint64_t pteg;
638 int slot;
639 int rc;
640
641 for (pteg = 0; pteg < n_ptegs; pteg++) {
642 hwaddr ptex = pteg * HPTES_PER_GROUP;
643 const ppc_hash_pte64_t *hptes
644 = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
645
646 if (!hptes) {
647 return H_HARDWARE;
648 }
649
650 for (slot = 0; slot < HPTES_PER_GROUP; slot++) {
651 rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize,
652 pteg, slot);
653 if (rc != H_SUCCESS) {
654 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
655 return rc;
656 }
657 }
658 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
659 }
660
661 return H_SUCCESS;
662 }
663
664 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data)
665 {
666 int ret;
667
668 cpu_synchronize_state(cs);
669
670 ret = kvmppc_put_books_sregs(POWERPC_CPU(cs));
671 if (ret < 0) {
672 error_report("failed to push sregs to KVM: %s", strerror(-ret));
673 exit(1);
674 }
675 }
676
677 static void push_sregs_to_kvm_pr(SpaprMachineState *spapr)
678 {
679 CPUState *cs;
680
681 /*
682 * This is a hack for the benefit of KVM PR - it abuses the SDR1
683 * slot in kvm_sregs to communicate the userspace address of the
684 * HPT
685 */
686 if (!kvm_enabled() || !spapr->htab) {
687 return;
688 }
689
690 CPU_FOREACH(cs) {
691 run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL);
692 }
693 }
694
695 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu,
696 SpaprMachineState *spapr,
697 target_ulong opcode,
698 target_ulong *args)
699 {
700 target_ulong flags = args[0];
701 target_ulong shift = args[1];
702 SpaprPendingHpt *pending = spapr->pending_hpt;
703 int rc;
704 size_t newsize;
705
706 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
707 return H_AUTHORITY;
708 }
709
710 if (!spapr->htab_shift) {
711 /* Radix guest, no HPT */
712 return H_NOT_AVAILABLE;
713 }
714
715 trace_spapr_h_resize_hpt_commit(flags, shift);
716
717 rc = kvmppc_resize_hpt_commit(cpu, flags, shift);
718 if (rc != -ENOSYS) {
719 rc = resize_hpt_convert_rc(rc);
720 if (rc == H_SUCCESS) {
721 /* Need to set the new htab_shift in the machine state */
722 spapr->htab_shift = shift;
723 }
724 return rc;
725 }
726
727 if (flags != 0) {
728 return H_PARAMETER;
729 }
730
731 if (!pending || (pending->shift != shift)) {
732 /* no matching prepare */
733 return H_CLOSED;
734 }
735
736 if (!pending->complete) {
737 /* prepare has not completed */
738 return H_BUSY;
739 }
740
741 /* Shouldn't have got past PREPARE without an HPT */
742 g_assert(spapr->htab_shift);
743
744 newsize = 1ULL << pending->shift;
745 rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr),
746 pending->hpt, newsize);
747 if (rc == H_SUCCESS) {
748 qemu_vfree(spapr->htab);
749 spapr->htab = pending->hpt;
750 spapr->htab_shift = pending->shift;
751
752 push_sregs_to_kvm_pr(spapr);
753
754 pending->hpt = NULL; /* so it's not free()d */
755 }
756
757 /* Clean up */
758 spapr->pending_hpt = NULL;
759 free_pending_hpt(pending);
760
761 return rc;
762 }
763
764 static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr,
765 target_ulong opcode, target_ulong *args)
766 {
767 cpu_synchronize_state(CPU(cpu));
768 cpu->env.spr[SPR_SPRG0] = args[0];
769
770 return H_SUCCESS;
771 }
772
773 static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr,
774 target_ulong opcode, target_ulong *args)
775 {
776 if (!has_spr(cpu, SPR_DABR)) {
777 return H_HARDWARE; /* DABR register not available */
778 }
779 cpu_synchronize_state(CPU(cpu));
780
781 if (has_spr(cpu, SPR_DABRX)) {
782 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */
783 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */
784 return H_RESERVED_DABR;
785 }
786
787 cpu->env.spr[SPR_DABR] = args[0];
788 return H_SUCCESS;
789 }
790
791 static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr,
792 target_ulong opcode, target_ulong *args)
793 {
794 target_ulong dabrx = args[1];
795
796 if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) {
797 return H_HARDWARE;
798 }
799
800 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0
801 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) {
802 return H_PARAMETER;
803 }
804
805 cpu_synchronize_state(CPU(cpu));
806 cpu->env.spr[SPR_DABRX] = dabrx;
807 cpu->env.spr[SPR_DABR] = args[0];
808
809 return H_SUCCESS;
810 }
811
812 static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr,
813 target_ulong opcode, target_ulong *args)
814 {
815 target_ulong flags = args[0];
816 hwaddr dst = args[1];
817 hwaddr src = args[2];
818 hwaddr len = TARGET_PAGE_SIZE;
819 uint8_t *pdst, *psrc;
820 target_long ret = H_SUCCESS;
821
822 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE
823 | H_COPY_PAGE | H_ZERO_PAGE)) {
824 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n",
825 flags);
826 return H_PARAMETER;
827 }
828
829 /* Map-in destination */
830 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) {
831 return H_PARAMETER;
832 }
833 pdst = cpu_physical_memory_map(dst, &len, 1);
834 if (!pdst || len != TARGET_PAGE_SIZE) {
835 return H_PARAMETER;
836 }
837
838 if (flags & H_COPY_PAGE) {
839 /* Map-in source, copy to destination, and unmap source again */
840 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) {
841 ret = H_PARAMETER;
842 goto unmap_out;
843 }
844 psrc = cpu_physical_memory_map(src, &len, 0);
845 if (!psrc || len != TARGET_PAGE_SIZE) {
846 ret = H_PARAMETER;
847 goto unmap_out;
848 }
849 memcpy(pdst, psrc, len);
850 cpu_physical_memory_unmap(psrc, len, 0, len);
851 } else if (flags & H_ZERO_PAGE) {
852 memset(pdst, 0, len); /* Just clear the destination page */
853 }
854
855 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) {
856 kvmppc_dcbst_range(cpu, pdst, len);
857 }
858 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) {
859 if (kvm_enabled()) {
860 kvmppc_icbi_range(cpu, pdst, len);
861 } else {
862 tb_flush(CPU(cpu));
863 }
864 }
865
866 unmap_out:
867 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len);
868 return ret;
869 }
870
871 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL
872 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL
873 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL
874 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL
875 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL
876 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL
877
878 static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa)
879 {
880 CPUState *cs = CPU(cpu);
881 CPUPPCState *env = &cpu->env;
882 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
883 uint16_t size;
884 uint8_t tmp;
885
886 if (vpa == 0) {
887 hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
888 return H_HARDWARE;
889 }
890
891 if (vpa % env->dcache_line_size) {
892 return H_PARAMETER;
893 }
894 /* FIXME: bounds check the address */
895
896 size = lduw_be_phys(cs->as, vpa + 0x4);
897
898 if (size < VPA_MIN_SIZE) {
899 return H_PARAMETER;
900 }
901
902 /* VPA is not allowed to cross a page boundary */
903 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) {
904 return H_PARAMETER;
905 }
906
907 spapr_cpu->vpa_addr = vpa;
908
909 tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET);
910 tmp |= VPA_SHARED_PROC_VAL;
911 stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
912
913 return H_SUCCESS;
914 }
915
916 static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa)
917 {
918 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
919
920 if (spapr_cpu->slb_shadow_addr) {
921 return H_RESOURCE;
922 }
923
924 if (spapr_cpu->dtl_addr) {
925 return H_RESOURCE;
926 }
927
928 spapr_cpu->vpa_addr = 0;
929 return H_SUCCESS;
930 }
931
932 static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr)
933 {
934 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
935 uint32_t size;
936
937 if (addr == 0) {
938 hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
939 return H_HARDWARE;
940 }
941
942 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4);
943 if (size < 0x8) {
944 return H_PARAMETER;
945 }
946
947 if ((addr / 4096) != ((addr + size - 1) / 4096)) {
948 return H_PARAMETER;
949 }
950
951 if (!spapr_cpu->vpa_addr) {
952 return H_RESOURCE;
953 }
954
955 spapr_cpu->slb_shadow_addr = addr;
956 spapr_cpu->slb_shadow_size = size;
957
958 return H_SUCCESS;
959 }
960
961 static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr)
962 {
963 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
964
965 spapr_cpu->slb_shadow_addr = 0;
966 spapr_cpu->slb_shadow_size = 0;
967 return H_SUCCESS;
968 }
969
970 static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr)
971 {
972 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
973 uint32_t size;
974
975 if (addr == 0) {
976 hcall_dprintf("Can't cope with DTL at logical 0\n");
977 return H_HARDWARE;
978 }
979
980 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4);
981
982 if (size < 48) {
983 return H_PARAMETER;
984 }
985
986 if (!spapr_cpu->vpa_addr) {
987 return H_RESOURCE;
988 }
989
990 spapr_cpu->dtl_addr = addr;
991 spapr_cpu->dtl_size = size;
992
993 return H_SUCCESS;
994 }
995
996 static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr)
997 {
998 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
999
1000 spapr_cpu->dtl_addr = 0;
1001 spapr_cpu->dtl_size = 0;
1002
1003 return H_SUCCESS;
1004 }
1005
1006 static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr,
1007 target_ulong opcode, target_ulong *args)
1008 {
1009 target_ulong flags = args[0];
1010 target_ulong procno = args[1];
1011 target_ulong vpa = args[2];
1012 target_ulong ret = H_PARAMETER;
1013 PowerPCCPU *tcpu;
1014
1015 tcpu = spapr_find_cpu(procno);
1016 if (!tcpu) {
1017 return H_PARAMETER;
1018 }
1019
1020 switch (flags) {
1021 case FLAGS_REGISTER_VPA:
1022 ret = register_vpa(tcpu, vpa);
1023 break;
1024
1025 case FLAGS_DEREGISTER_VPA:
1026 ret = deregister_vpa(tcpu, vpa);
1027 break;
1028
1029 case FLAGS_REGISTER_SLBSHADOW:
1030 ret = register_slb_shadow(tcpu, vpa);
1031 break;
1032
1033 case FLAGS_DEREGISTER_SLBSHADOW:
1034 ret = deregister_slb_shadow(tcpu, vpa);
1035 break;
1036
1037 case FLAGS_REGISTER_DTL:
1038 ret = register_dtl(tcpu, vpa);
1039 break;
1040
1041 case FLAGS_DEREGISTER_DTL:
1042 ret = deregister_dtl(tcpu, vpa);
1043 break;
1044 }
1045
1046 return ret;
1047 }
1048
1049 static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr,
1050 target_ulong opcode, target_ulong *args)
1051 {
1052 CPUPPCState *env = &cpu->env;
1053 CPUState *cs = CPU(cpu);
1054 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
1055
1056 env->msr |= (1ULL << MSR_EE);
1057 hreg_compute_hflags(env);
1058
1059 if (spapr_cpu->prod) {
1060 spapr_cpu->prod = false;
1061 return H_SUCCESS;
1062 }
1063
1064 if (!cpu_has_work(cs)) {
1065 cs->halted = 1;
1066 cs->exception_index = EXCP_HLT;
1067 cs->exit_request = 1;
1068 }
1069
1070 return H_SUCCESS;
1071 }
1072
1073 static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr,
1074 target_ulong opcode, target_ulong *args)
1075 {
1076 target_long target = args[0];
1077 uint32_t dispatch = args[1];
1078 CPUState *cs = CPU(cpu);
1079 SpaprCpuState *spapr_cpu;
1080
1081 /*
1082 * -1 means confer to all other CPUs without dispatch counter check,
1083 * otherwise it's a targeted confer.
1084 */
1085 if (target != -1) {
1086 PowerPCCPU *target_cpu = spapr_find_cpu(target);
1087 uint32_t target_dispatch;
1088
1089 if (!target_cpu) {
1090 return H_PARAMETER;
1091 }
1092
1093 spapr_cpu = spapr_cpu_state(target_cpu);
1094
1095 /*
1096 * target == self is a special case, we wait until prodded, without
1097 * dispatch counter check.
1098 */
1099 if (cpu == target_cpu) {
1100 if (spapr_cpu->prod) {
1101 spapr_cpu->prod = false;
1102
1103 return H_SUCCESS;
1104 }
1105
1106 cs->halted = 1;
1107 cs->exception_index = EXCP_HALTED;
1108 cs->exit_request = 1;
1109
1110 return H_SUCCESS;
1111 }
1112
1113 if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) {
1114 return H_SUCCESS;
1115 }
1116
1117 target_dispatch = ldl_be_phys(cs->as,
1118 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER);
1119 if (target_dispatch != dispatch) {
1120 return H_SUCCESS;
1121 }
1122
1123 /*
1124 * The targeted confer does not do anything special beyond yielding
1125 * the current vCPU, but even this should be better than nothing.
1126 * At least for single-threaded tcg, it gives the target a chance to
1127 * run before we run again. Multi-threaded tcg does not really do
1128 * anything with EXCP_YIELD yet.
1129 */
1130 }
1131
1132 cs->exception_index = EXCP_YIELD;
1133 cs->exit_request = 1;
1134 cpu_loop_exit(cs);
1135
1136 return H_SUCCESS;
1137 }
1138
1139 static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr,
1140 target_ulong opcode, target_ulong *args)
1141 {
1142 target_long target = args[0];
1143 PowerPCCPU *tcpu;
1144 CPUState *cs;
1145 SpaprCpuState *spapr_cpu;
1146
1147 tcpu = spapr_find_cpu(target);
1148 cs = CPU(tcpu);
1149 if (!cs) {
1150 return H_PARAMETER;
1151 }
1152
1153 spapr_cpu = spapr_cpu_state(tcpu);
1154 spapr_cpu->prod = true;
1155 cs->halted = 0;
1156 qemu_cpu_kick(cs);
1157
1158 return H_SUCCESS;
1159 }
1160
1161 static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr,
1162 target_ulong opcode, target_ulong *args)
1163 {
1164 target_ulong rtas_r3 = args[0];
1165 uint32_t token = rtas_ld(rtas_r3, 0);
1166 uint32_t nargs = rtas_ld(rtas_r3, 1);
1167 uint32_t nret = rtas_ld(rtas_r3, 2);
1168
1169 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12,
1170 nret, rtas_r3 + 12 + 4*nargs);
1171 }
1172
1173 static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr,
1174 target_ulong opcode, target_ulong *args)
1175 {
1176 CPUState *cs = CPU(cpu);
1177 target_ulong size = args[0];
1178 target_ulong addr = args[1];
1179
1180 switch (size) {
1181 case 1:
1182 args[0] = ldub_phys(cs->as, addr);
1183 return H_SUCCESS;
1184 case 2:
1185 args[0] = lduw_phys(cs->as, addr);
1186 return H_SUCCESS;
1187 case 4:
1188 args[0] = ldl_phys(cs->as, addr);
1189 return H_SUCCESS;
1190 case 8:
1191 args[0] = ldq_phys(cs->as, addr);
1192 return H_SUCCESS;
1193 }
1194 return H_PARAMETER;
1195 }
1196
1197 static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr,
1198 target_ulong opcode, target_ulong *args)
1199 {
1200 CPUState *cs = CPU(cpu);
1201
1202 target_ulong size = args[0];
1203 target_ulong addr = args[1];
1204 target_ulong val = args[2];
1205
1206 switch (size) {
1207 case 1:
1208 stb_phys(cs->as, addr, val);
1209 return H_SUCCESS;
1210 case 2:
1211 stw_phys(cs->as, addr, val);
1212 return H_SUCCESS;
1213 case 4:
1214 stl_phys(cs->as, addr, val);
1215 return H_SUCCESS;
1216 case 8:
1217 stq_phys(cs->as, addr, val);
1218 return H_SUCCESS;
1219 }
1220 return H_PARAMETER;
1221 }
1222
1223 static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr,
1224 target_ulong opcode, target_ulong *args)
1225 {
1226 CPUState *cs = CPU(cpu);
1227
1228 target_ulong dst = args[0]; /* Destination address */
1229 target_ulong src = args[1]; /* Source address */
1230 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */
1231 target_ulong count = args[3]; /* Element count */
1232 target_ulong op = args[4]; /* 0 = copy, 1 = invert */
1233 uint64_t tmp;
1234 unsigned int mask = (1 << esize) - 1;
1235 int step = 1 << esize;
1236
1237 if (count > 0x80000000) {
1238 return H_PARAMETER;
1239 }
1240
1241 if ((dst & mask) || (src & mask) || (op > 1)) {
1242 return H_PARAMETER;
1243 }
1244
1245 if (dst >= src && dst < (src + (count << esize))) {
1246 dst = dst + ((count - 1) << esize);
1247 src = src + ((count - 1) << esize);
1248 step = -step;
1249 }
1250
1251 while (count--) {
1252 switch (esize) {
1253 case 0:
1254 tmp = ldub_phys(cs->as, src);
1255 break;
1256 case 1:
1257 tmp = lduw_phys(cs->as, src);
1258 break;
1259 case 2:
1260 tmp = ldl_phys(cs->as, src);
1261 break;
1262 case 3:
1263 tmp = ldq_phys(cs->as, src);
1264 break;
1265 default:
1266 return H_PARAMETER;
1267 }
1268 if (op == 1) {
1269 tmp = ~tmp;
1270 }
1271 switch (esize) {
1272 case 0:
1273 stb_phys(cs->as, dst, tmp);
1274 break;
1275 case 1:
1276 stw_phys(cs->as, dst, tmp);
1277 break;
1278 case 2:
1279 stl_phys(cs->as, dst, tmp);
1280 break;
1281 case 3:
1282 stq_phys(cs->as, dst, tmp);
1283 break;
1284 }
1285 dst = dst + step;
1286 src = src + step;
1287 }
1288
1289 return H_SUCCESS;
1290 }
1291
1292 static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr,
1293 target_ulong opcode, target_ulong *args)
1294 {
1295 /* Nothing to do on emulation, KVM will trap this in the kernel */
1296 return H_SUCCESS;
1297 }
1298
1299 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr,
1300 target_ulong opcode, target_ulong *args)
1301 {
1302 /* Nothing to do on emulation, KVM will trap this in the kernel */
1303 return H_SUCCESS;
1304 }
1305
1306 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu,
1307 target_ulong mflags,
1308 target_ulong value1,
1309 target_ulong value2)
1310 {
1311 if (value1) {
1312 return H_P3;
1313 }
1314 if (value2) {
1315 return H_P4;
1316 }
1317
1318 switch (mflags) {
1319 case H_SET_MODE_ENDIAN_BIG:
1320 spapr_set_all_lpcrs(0, LPCR_ILE);
1321 spapr_pci_switch_vga(true);
1322 return H_SUCCESS;
1323
1324 case H_SET_MODE_ENDIAN_LITTLE:
1325 spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE);
1326 spapr_pci_switch_vga(false);
1327 return H_SUCCESS;
1328 }
1329
1330 return H_UNSUPPORTED_FLAG;
1331 }
1332
1333 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu,
1334 target_ulong mflags,
1335 target_ulong value1,
1336 target_ulong value2)
1337 {
1338 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
1339
1340 if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
1341 return H_P2;
1342 }
1343 if (value1) {
1344 return H_P3;
1345 }
1346 if (value2) {
1347 return H_P4;
1348 }
1349
1350 if (mflags == AIL_RESERVED) {
1351 return H_UNSUPPORTED_FLAG;
1352 }
1353
1354 spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL);
1355
1356 return H_SUCCESS;
1357 }
1358
1359 static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr,
1360 target_ulong opcode, target_ulong *args)
1361 {
1362 target_ulong resource = args[1];
1363 target_ulong ret = H_P2;
1364
1365 switch (resource) {
1366 case H_SET_MODE_RESOURCE_LE:
1367 ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]);
1368 break;
1369 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE:
1370 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0],
1371 args[2], args[3]);
1372 break;
1373 }
1374
1375 return ret;
1376 }
1377
1378 static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr,
1379 target_ulong opcode, target_ulong *args)
1380 {
1381 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n",
1382 opcode, " (H_CLEAN_SLB)");
1383 return H_FUNCTION;
1384 }
1385
1386 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr,
1387 target_ulong opcode, target_ulong *args)
1388 {
1389 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n",
1390 opcode, " (H_INVALIDATE_PID)");
1391 return H_FUNCTION;
1392 }
1393
1394 static void spapr_check_setup_free_hpt(SpaprMachineState *spapr,
1395 uint64_t patbe_old, uint64_t patbe_new)
1396 {
1397 /*
1398 * We have 4 Options:
1399 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing
1400 * HASH->RADIX : Free HPT
1401 * RADIX->HASH : Allocate HPT
1402 * NOTHING->HASH : Allocate HPT
1403 * Note: NOTHING implies the case where we said the guest could choose
1404 * later and so assumed radix and now it's called H_REG_PROC_TBL
1405 */
1406
1407 if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) {
1408 /* We assume RADIX, so this catches all the "Do Nothing" cases */
1409 } else if (!(patbe_old & PATE1_GR)) {
1410 /* HASH->RADIX : Free HPT */
1411 spapr_free_hpt(spapr);
1412 } else if (!(patbe_new & PATE1_GR)) {
1413 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */
1414 spapr_setup_hpt_and_vrma(spapr);
1415 }
1416 return;
1417 }
1418
1419 #define FLAGS_MASK 0x01FULL
1420 #define FLAG_MODIFY 0x10
1421 #define FLAG_REGISTER 0x08
1422 #define FLAG_RADIX 0x04
1423 #define FLAG_HASH_PROC_TBL 0x02
1424 #define FLAG_GTSE 0x01
1425
1426 static target_ulong h_register_process_table(PowerPCCPU *cpu,
1427 SpaprMachineState *spapr,
1428 target_ulong opcode,
1429 target_ulong *args)
1430 {
1431 target_ulong flags = args[0];
1432 target_ulong proc_tbl = args[1];
1433 target_ulong page_size = args[2];
1434 target_ulong table_size = args[3];
1435 target_ulong update_lpcr = 0;
1436 uint64_t cproc;
1437
1438 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */
1439 return H_PARAMETER;
1440 }
1441 if (flags & FLAG_MODIFY) {
1442 if (flags & FLAG_REGISTER) {
1443 if (flags & FLAG_RADIX) { /* Register new RADIX process table */
1444 if (proc_tbl & 0xfff || proc_tbl >> 60) {
1445 return H_P2;
1446 } else if (page_size) {
1447 return H_P3;
1448 } else if (table_size > 24) {
1449 return H_P4;
1450 }
1451 cproc = PATE1_GR | proc_tbl | table_size;
1452 } else { /* Register new HPT process table */
1453 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */
1454 /* TODO - Not Supported */
1455 /* Technically caused by flag bits => H_PARAMETER */
1456 return H_PARAMETER;
1457 } else { /* Hash with SLB */
1458 if (proc_tbl >> 38) {
1459 return H_P2;
1460 } else if (page_size & ~0x7) {
1461 return H_P3;
1462 } else if (table_size > 24) {
1463 return H_P4;
1464 }
1465 }
1466 cproc = (proc_tbl << 25) | page_size << 5 | table_size;
1467 }
1468
1469 } else { /* Deregister current process table */
1470 /*
1471 * Set to benign value: (current GR) | 0. This allows
1472 * deregistration in KVM to succeed even if the radix bit
1473 * in flags doesn't match the radix bit in the old PATE.
1474 */
1475 cproc = spapr->patb_entry & PATE1_GR;
1476 }
1477 } else { /* Maintain current registration */
1478 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) {
1479 /* Technically caused by flag bits => H_PARAMETER */
1480 return H_PARAMETER; /* Existing Process Table Mismatch */
1481 }
1482 cproc = spapr->patb_entry;
1483 }
1484
1485 /* Check if we need to setup OR free the hpt */
1486 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc);
1487
1488 spapr->patb_entry = cproc; /* Save new process table */
1489
1490 /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */
1491 if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */
1492 update_lpcr |= (LPCR_UPRT | LPCR_HR);
1493 else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */
1494 update_lpcr |= LPCR_UPRT;
1495 if (flags & FLAG_GTSE) /* Guest translation shootdown enable */
1496 update_lpcr |= LPCR_GTSE;
1497
1498 spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE);
1499
1500 if (kvm_enabled()) {
1501 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX,
1502 flags & FLAG_GTSE, cproc);
1503 }
1504 return H_SUCCESS;
1505 }
1506
1507 #define H_SIGNAL_SYS_RESET_ALL -1
1508 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2
1509
1510 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu,
1511 SpaprMachineState *spapr,
1512 target_ulong opcode, target_ulong *args)
1513 {
1514 target_long target = args[0];
1515 CPUState *cs;
1516
1517 if (target < 0) {
1518 /* Broadcast */
1519 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) {
1520 return H_PARAMETER;
1521 }
1522
1523 CPU_FOREACH(cs) {
1524 PowerPCCPU *c = POWERPC_CPU(cs);
1525
1526 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) {
1527 if (c == cpu) {
1528 continue;
1529 }
1530 }
1531 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
1532 }
1533 return H_SUCCESS;
1534
1535 } else {
1536 /* Unicast */
1537 cs = CPU(spapr_find_cpu(target));
1538 if (cs) {
1539 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
1540 return H_SUCCESS;
1541 }
1542 return H_PARAMETER;
1543 }
1544 }
1545
1546 static uint32_t cas_check_pvr(SpaprMachineState *spapr, PowerPCCPU *cpu,
1547 target_ulong *addr, bool *raw_mode_supported,
1548 Error **errp)
1549 {
1550 bool explicit_match = false; /* Matched the CPU's real PVR */
1551 uint32_t max_compat = spapr->max_compat_pvr;
1552 uint32_t best_compat = 0;
1553 int i;
1554
1555 /*
1556 * We scan the supplied table of PVRs looking for two things
1557 * 1. Is our real CPU PVR in the list?
1558 * 2. What's the "best" listed logical PVR
1559 */
1560 for (i = 0; i < 512; ++i) {
1561 uint32_t pvr, pvr_mask;
1562
1563 pvr_mask = ldl_be_phys(&address_space_memory, *addr);
1564 pvr = ldl_be_phys(&address_space_memory, *addr + 4);
1565 *addr += 8;
1566
1567 if (~pvr_mask & pvr) {
1568 break; /* Terminator record */
1569 }
1570
1571 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) {
1572 explicit_match = true;
1573 } else {
1574 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) {
1575 best_compat = pvr;
1576 }
1577 }
1578 }
1579
1580 if ((best_compat == 0) && (!explicit_match || max_compat)) {
1581 /* We couldn't find a suitable compatibility mode, and either
1582 * the guest doesn't support "raw" mode for this CPU, or raw
1583 * mode is disabled because a maximum compat mode is set */
1584 error_setg(errp, "Couldn't negotiate a suitable PVR during CAS");
1585 return 0;
1586 }
1587
1588 *raw_mode_supported = explicit_match;
1589
1590 /* Parsing finished */
1591 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat);
1592
1593 return best_compat;
1594 }
1595
1596 static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
1597 SpaprMachineState *spapr,
1598 target_ulong opcode,
1599 target_ulong *args)
1600 {
1601 /* Working address in data buffer */
1602 target_ulong addr = ppc64_phys_to_real(args[0]);
1603 target_ulong ov_table;
1604 uint32_t cas_pvr;
1605 SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates;
1606 bool guest_radix;
1607 Error *local_err = NULL;
1608 bool raw_mode_supported = false;
1609 bool guest_xive;
1610
1611 cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err);
1612 if (local_err) {
1613 error_report_err(local_err);
1614 return H_HARDWARE;
1615 }
1616
1617 /* Update CPUs */
1618 if (cpu->compat_pvr != cas_pvr) {
1619 ppc_set_compat_all(cas_pvr, &local_err);
1620 if (local_err) {
1621 /* We fail to set compat mode (likely because running with KVM PR),
1622 * but maybe we can fallback to raw mode if the guest supports it.
1623 */
1624 if (!raw_mode_supported) {
1625 error_report_err(local_err);
1626 return H_HARDWARE;
1627 }
1628 error_free(local_err);
1629 local_err = NULL;
1630 }
1631 }
1632
1633 /* For the future use: here @ov_table points to the first option vector */
1634 ov_table = addr;
1635
1636 ov1_guest = spapr_ovec_parse_vector(ov_table, 1);
1637 ov5_guest = spapr_ovec_parse_vector(ov_table, 5);
1638 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) {
1639 error_report("guest requested hash and radix MMU, which is invalid.");
1640 exit(EXIT_FAILURE);
1641 }
1642 if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) {
1643 error_report("guest requested an invalid interrupt mode");
1644 exit(EXIT_FAILURE);
1645 }
1646
1647 /* The radix/hash bit in byte 24 requires special handling: */
1648 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300);
1649 spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300);
1650
1651 guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT);
1652
1653 /*
1654 * HPT resizing is a bit of a special case, because when enabled
1655 * we assume an HPT guest will support it until it says it
1656 * doesn't, instead of assuming it won't support it until it says
1657 * it does. Strictly speaking that approach could break for
1658 * guests which don't make a CAS call, but those are so old we
1659 * don't care about them. Without that assumption we'd have to
1660 * make at least a temporary allocation of an HPT sized for max
1661 * memory, which could be impossibly difficult under KVM HV if
1662 * maxram is large.
1663 */
1664 if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) {
1665 int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1666
1667 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) {
1668 error_report(
1669 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required");
1670 exit(1);
1671 }
1672
1673 if (spapr->htab_shift < maxshift) {
1674 /* Guest doesn't know about HPT resizing, so we
1675 * pre-emptively resize for the maximum permitted RAM. At
1676 * the point this is called, nothing should have been
1677 * entered into the existing HPT */
1678 spapr_reallocate_hpt(spapr, maxshift, &error_fatal);
1679 push_sregs_to_kvm_pr(spapr);
1680 }
1681 }
1682
1683 /* NOTE: there are actually a number of ov5 bits where input from the
1684 * guest is always zero, and the platform/QEMU enables them independently
1685 * of guest input. To model these properly we'd want some sort of mask,
1686 * but since they only currently apply to memory migration as defined
1687 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need
1688 * to worry about this for now.
1689 */
1690 ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas);
1691
1692 /* also clear the radix/hash bit from the current ov5_cas bits to
1693 * be in sync with the newly ov5 bits. Else the radix bit will be
1694 * seen as being removed and this will generate a reset loop
1695 */
1696 spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300);
1697
1698 /* full range of negotiated ov5 capabilities */
1699 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest);
1700 spapr_ovec_cleanup(ov5_guest);
1701 /* capabilities that have been added since CAS-generated guest reset.
1702 * if capabilities have since been removed, generate another reset
1703 */
1704 ov5_updates = spapr_ovec_new();
1705 spapr->cas_reboot = spapr_ovec_diff(ov5_updates,
1706 ov5_cas_old, spapr->ov5_cas);
1707 spapr_ovec_cleanup(ov5_cas_old);
1708 /* Now that processing is finished, set the radix/hash bit for the
1709 * guest if it requested a valid mode; otherwise terminate the boot. */
1710 if (guest_radix) {
1711 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) {
1712 error_report("Guest requested unavailable MMU mode (radix).");
1713 exit(EXIT_FAILURE);
1714 }
1715 spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300);
1716 } else {
1717 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()
1718 && !kvmppc_has_cap_mmu_hash_v3()) {
1719 error_report("Guest requested unavailable MMU mode (hash).");
1720 exit(EXIT_FAILURE);
1721 }
1722 }
1723 spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest,
1724 OV1_PPC_3_00);
1725 spapr_ovec_cleanup(ov1_guest);
1726 if (!spapr->cas_reboot) {
1727 /* If spapr_machine_reset() did not set up a HPT but one is necessary
1728 * (because the guest isn't going to use radix) then set it up here. */
1729 if ((spapr->patb_entry & PATE1_GR) && !guest_radix) {
1730 /* legacy hash or new hash: */
1731 spapr_setup_hpt_and_vrma(spapr);
1732 }
1733 spapr->cas_reboot =
1734 (spapr_h_cas_compose_response(spapr, args[1], args[2],
1735 ov5_updates) != 0);
1736 }
1737
1738 /*
1739 * Ensure the guest asks for an interrupt mode we support; otherwise
1740 * terminate the boot.
1741 */
1742 if (guest_xive) {
1743 if (spapr->irq->ov5 == SPAPR_OV5_XIVE_LEGACY) {
1744 error_report(
1745 "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property");
1746 exit(EXIT_FAILURE);
1747 }
1748 } else {
1749 if (spapr->irq->ov5 == SPAPR_OV5_XIVE_EXPLOIT) {
1750 error_report(
1751 "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual");
1752 exit(EXIT_FAILURE);
1753 }
1754 }
1755
1756 /*
1757 * Generate a machine reset when we have an update of the
1758 * interrupt mode. Only required when the machine supports both
1759 * modes.
1760 */
1761 if (!spapr->cas_reboot) {
1762 spapr->cas_reboot = spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT)
1763 && spapr->irq->ov5 & SPAPR_OV5_XIVE_BOTH;
1764 }
1765
1766 spapr_ovec_cleanup(ov5_updates);
1767
1768 if (spapr->cas_reboot) {
1769 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1770 }
1771
1772 return H_SUCCESS;
1773 }
1774
1775 static target_ulong h_home_node_associativity(PowerPCCPU *cpu,
1776 SpaprMachineState *spapr,
1777 target_ulong opcode,
1778 target_ulong *args)
1779 {
1780 target_ulong flags = args[0];
1781 target_ulong procno = args[1];
1782 PowerPCCPU *tcpu;
1783 int idx;
1784
1785 /* only support procno from H_REGISTER_VPA */
1786 if (flags != 0x1) {
1787 return H_FUNCTION;
1788 }
1789
1790 tcpu = spapr_find_cpu(procno);
1791 if (tcpu == NULL) {
1792 return H_P2;
1793 }
1794
1795 /* sequence is the same as in the "ibm,associativity" property */
1796
1797 idx = 0;
1798 #define ASSOCIATIVITY(a, b) (((uint64_t)(a) << 32) | \
1799 ((uint64_t)(b) & 0xffffffff))
1800 args[idx++] = ASSOCIATIVITY(0, 0);
1801 args[idx++] = ASSOCIATIVITY(0, tcpu->node_id);
1802 args[idx++] = ASSOCIATIVITY(procno, -1);
1803 for ( ; idx < 6; idx++) {
1804 args[idx] = -1;
1805 }
1806 #undef ASSOCIATIVITY
1807
1808 return H_SUCCESS;
1809 }
1810
1811 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu,
1812 SpaprMachineState *spapr,
1813 target_ulong opcode,
1814 target_ulong *args)
1815 {
1816 uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS &
1817 ~H_CPU_CHAR_THR_RECONF_TRIG;
1818 uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY;
1819 uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC);
1820 uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC);
1821 uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS);
1822 uint8_t count_cache_flush_assist = spapr_get_cap(spapr,
1823 SPAPR_CAP_CCF_ASSIST);
1824
1825 switch (safe_cache) {
1826 case SPAPR_CAP_WORKAROUND:
1827 characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30;
1828 characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2;
1829 characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV;
1830 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR;
1831 break;
1832 case SPAPR_CAP_FIXED:
1833 break;
1834 default: /* broken */
1835 assert(safe_cache == SPAPR_CAP_BROKEN);
1836 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR;
1837 break;
1838 }
1839
1840 switch (safe_bounds_check) {
1841 case SPAPR_CAP_WORKAROUND:
1842 characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31;
1843 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR;
1844 break;
1845 case SPAPR_CAP_FIXED:
1846 break;
1847 default: /* broken */
1848 assert(safe_bounds_check == SPAPR_CAP_BROKEN);
1849 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR;
1850 break;
1851 }
1852
1853 switch (safe_indirect_branch) {
1854 case SPAPR_CAP_FIXED_NA:
1855 break;
1856 case SPAPR_CAP_FIXED_CCD:
1857 characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS;
1858 break;
1859 case SPAPR_CAP_FIXED_IBS:
1860 characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED;
1861 break;
1862 case SPAPR_CAP_WORKAROUND:
1863 behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE;
1864 if (count_cache_flush_assist) {
1865 characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST;
1866 }
1867 break;
1868 default: /* broken */
1869 assert(safe_indirect_branch == SPAPR_CAP_BROKEN);
1870 break;
1871 }
1872
1873 args[0] = characteristics;
1874 args[1] = behaviour;
1875 return H_SUCCESS;
1876 }
1877
1878 static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr,
1879 target_ulong opcode, target_ulong *args)
1880 {
1881 target_ulong dt = ppc64_phys_to_real(args[0]);
1882 struct fdt_header hdr = { 0 };
1883 unsigned cb;
1884 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
1885 void *fdt;
1886
1887 cpu_physical_memory_read(dt, &hdr, sizeof(hdr));
1888 cb = fdt32_to_cpu(hdr.totalsize);
1889
1890 if (!smc->update_dt_enabled) {
1891 return H_SUCCESS;
1892 }
1893
1894 /* Check that the fdt did not grow out of proportion */
1895 if (cb > spapr->fdt_initial_size * 2) {
1896 trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb,
1897 fdt32_to_cpu(hdr.magic));
1898 return H_PARAMETER;
1899 }
1900
1901 fdt = g_malloc0(cb);
1902 cpu_physical_memory_read(dt, fdt, cb);
1903
1904 /* Check the fdt consistency */
1905 if (fdt_check_full(fdt, cb)) {
1906 trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb,
1907 fdt32_to_cpu(hdr.magic));
1908 return H_PARAMETER;
1909 }
1910
1911 g_free(spapr->fdt_blob);
1912 spapr->fdt_size = cb;
1913 spapr->fdt_blob = fdt;
1914 trace_spapr_update_dt(cb);
1915
1916 return H_SUCCESS;
1917 }
1918
1919 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
1920 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1];
1921
1922 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
1923 {
1924 spapr_hcall_fn *slot;
1925
1926 if (opcode <= MAX_HCALL_OPCODE) {
1927 assert((opcode & 0x3) == 0);
1928
1929 slot = &papr_hypercall_table[opcode / 4];
1930 } else {
1931 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
1932
1933 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
1934 }
1935
1936 assert(!(*slot));
1937 *slot = fn;
1938 }
1939
1940 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
1941 target_ulong *args)
1942 {
1943 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1944
1945 if ((opcode <= MAX_HCALL_OPCODE)
1946 && ((opcode & 0x3) == 0)) {
1947 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
1948
1949 if (fn) {
1950 return fn(cpu, spapr, opcode, args);
1951 }
1952 } else if ((opcode >= KVMPPC_HCALL_BASE) &&
1953 (opcode <= KVMPPC_HCALL_MAX)) {
1954 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
1955
1956 if (fn) {
1957 return fn(cpu, spapr, opcode, args);
1958 }
1959 }
1960
1961 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n",
1962 opcode);
1963 return H_FUNCTION;
1964 }
1965
1966 static void hypercall_register_types(void)
1967 {
1968 /* hcall-pft */
1969 spapr_register_hypercall(H_ENTER, h_enter);
1970 spapr_register_hypercall(H_REMOVE, h_remove);
1971 spapr_register_hypercall(H_PROTECT, h_protect);
1972 spapr_register_hypercall(H_READ, h_read);
1973
1974 /* hcall-bulk */
1975 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove);
1976
1977 /* hcall-hpt-resize */
1978 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare);
1979 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit);
1980
1981 /* hcall-splpar */
1982 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa);
1983 spapr_register_hypercall(H_CEDE, h_cede);
1984 spapr_register_hypercall(H_CONFER, h_confer);
1985 spapr_register_hypercall(H_PROD, h_prod);
1986
1987 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset);
1988
1989 /* processor register resource access h-calls */
1990 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0);
1991 spapr_register_hypercall(H_SET_DABR, h_set_dabr);
1992 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr);
1993 spapr_register_hypercall(H_PAGE_INIT, h_page_init);
1994 spapr_register_hypercall(H_SET_MODE, h_set_mode);
1995
1996 /* In Memory Table MMU h-calls */
1997 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb);
1998 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid);
1999 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table);
2000
2001 /* hcall-get-cpu-characteristics */
2002 spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS,
2003 h_get_cpu_characteristics);
2004
2005 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
2006 * here between the "CI" and the "CACHE" variants, they will use whatever
2007 * mapping attributes qemu is using. When using KVM, the kernel will
2008 * enforce the attributes more strongly
2009 */
2010 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load);
2011 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store);
2012 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load);
2013 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store);
2014 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi);
2015 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf);
2016 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop);
2017
2018 /* qemu/KVM-PPC specific hcalls */
2019 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
2020
2021 /* ibm,client-architecture-support support */
2022 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support);
2023
2024 spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt);
2025
2026 /* Virtual Processor Home Node */
2027 spapr_register_hypercall(H_HOME_NODE_ASSOCIATIVITY,
2028 h_home_node_associativity);
2029 }
2030
2031 type_init(hypercall_register_types)
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