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1 /*
2 * QEMU sPAPR IOMMU (TCE) code
3 *
4 * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "hw/hw.h"
20 #include "sysemu/kvm.h"
21 #include "hw/qdev.h"
22 #include "kvm_ppc.h"
23 #include "sysemu/dma.h"
24 #include "exec/address-spaces.h"
25 #include "trace.h"
26
27 #include "hw/ppc/spapr.h"
28
29 #include <libfdt.h>
30
31 enum sPAPRTCEAccess {
32 SPAPR_TCE_FAULT = 0,
33 SPAPR_TCE_RO = 1,
34 SPAPR_TCE_WO = 2,
35 SPAPR_TCE_RW = 3,
36 };
37
38 #define IOMMU_PAGE_SIZE(shift) (1ULL << (shift))
39 #define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1))
40
41 static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables;
42
43 static sPAPRTCETable *spapr_tce_find_by_liobn(uint32_t liobn)
44 {
45 sPAPRTCETable *tcet;
46
47 if (liobn & 0xFFFFFFFF00000000ULL) {
48 hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
49 liobn);
50 return NULL;
51 }
52
53 QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
54 if (tcet->liobn == liobn) {
55 return tcet;
56 }
57 }
58
59 return NULL;
60 }
61
62 /* Called from RCU critical section */
63 static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr addr,
64 bool is_write)
65 {
66 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
67 uint64_t tce;
68 IOMMUTLBEntry ret = {
69 .target_as = &address_space_memory,
70 .iova = 0,
71 .translated_addr = 0,
72 .addr_mask = ~(hwaddr)0,
73 .perm = IOMMU_NONE,
74 };
75
76 if (tcet->bypass) {
77 ret.perm = IOMMU_RW;
78 } else if ((addr >> tcet->page_shift) < tcet->nb_table) {
79 /* Check if we are in bound */
80 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
81
82 tce = tcet->table[addr >> tcet->page_shift];
83 ret.iova = addr & page_mask;
84 ret.translated_addr = tce & page_mask;
85 ret.addr_mask = ~page_mask;
86 ret.perm = tce & IOMMU_RW;
87 }
88 trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm,
89 ret.addr_mask);
90
91 return ret;
92 }
93
94 static const VMStateDescription vmstate_spapr_tce_table = {
95 .name = "spapr_iommu",
96 .version_id = 2,
97 .minimum_version_id = 2,
98 .fields = (VMStateField []) {
99 /* Sanity check */
100 VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable),
101 VMSTATE_UINT32_EQUAL(nb_table, sPAPRTCETable),
102
103 /* IOMMU state */
104 VMSTATE_BOOL(bypass, sPAPRTCETable),
105 VMSTATE_VARRAY_UINT32(table, sPAPRTCETable, nb_table, 0, vmstate_info_uint64, uint64_t),
106
107 VMSTATE_END_OF_LIST()
108 },
109 };
110
111 static MemoryRegionIOMMUOps spapr_iommu_ops = {
112 .translate = spapr_tce_translate_iommu,
113 };
114
115 static int spapr_tce_table_realize(DeviceState *dev)
116 {
117 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
118
119 if (kvm_enabled()) {
120 tcet->table = kvmppc_create_spapr_tce(tcet->liobn,
121 tcet->nb_table <<
122 tcet->page_shift,
123 &tcet->fd,
124 tcet->vfio_accel);
125 }
126
127 if (!tcet->table) {
128 size_t table_size = tcet->nb_table * sizeof(uint64_t);
129 tcet->table = g_malloc0(table_size);
130 }
131
132 trace_spapr_iommu_new_table(tcet->liobn, tcet, tcet->table, tcet->fd);
133
134 memory_region_init_iommu(&tcet->iommu, OBJECT(dev), &spapr_iommu_ops,
135 "iommu-spapr", ram_size);
136
137 QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
138
139 vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table,
140 tcet);
141
142 return 0;
143 }
144
145 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn,
146 uint64_t bus_offset,
147 uint32_t page_shift,
148 uint32_t nb_table,
149 bool vfio_accel)
150 {
151 sPAPRTCETable *tcet;
152
153 if (spapr_tce_find_by_liobn(liobn)) {
154 fprintf(stderr, "Attempted to create TCE table with duplicate"
155 " LIOBN 0x%x\n", liobn);
156 return NULL;
157 }
158
159 if (!nb_table) {
160 return NULL;
161 }
162
163 tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
164 tcet->liobn = liobn;
165 tcet->bus_offset = bus_offset;
166 tcet->page_shift = page_shift;
167 tcet->nb_table = nb_table;
168 tcet->vfio_accel = vfio_accel;
169
170 object_property_add_child(OBJECT(owner), "tce-table", OBJECT(tcet), NULL);
171
172 object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
173
174 return tcet;
175 }
176
177 static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp)
178 {
179 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
180
181 QLIST_REMOVE(tcet, list);
182
183 if (!kvm_enabled() ||
184 (kvmppc_remove_spapr_tce(tcet->table, tcet->fd,
185 tcet->nb_table) != 0)) {
186 g_free(tcet->table);
187 }
188 }
189
190 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet)
191 {
192 return &tcet->iommu;
193 }
194
195 void spapr_tce_set_bypass(sPAPRTCETable *tcet, bool bypass)
196 {
197 tcet->bypass = bypass;
198 }
199
200 static void spapr_tce_reset(DeviceState *dev)
201 {
202 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
203 size_t table_size = tcet->nb_table * sizeof(uint64_t);
204
205 tcet->bypass = false;
206 memset(tcet->table, 0, table_size);
207 }
208
209 static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
210 target_ulong tce)
211 {
212 IOMMUTLBEntry entry;
213 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
214 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
215
216 if (index >= tcet->nb_table) {
217 hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
218 TARGET_FMT_lx "\n", ioba);
219 return H_PARAMETER;
220 }
221
222 tcet->table[index] = tce;
223
224 entry.target_as = &address_space_memory,
225 entry.iova = ioba & page_mask;
226 entry.translated_addr = tce & page_mask;
227 entry.addr_mask = ~page_mask;
228 entry.perm = tce & IOMMU_RW;
229 memory_region_notify_iommu(&tcet->iommu, entry);
230
231 return H_SUCCESS;
232 }
233
234 static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
235 sPAPREnvironment *spapr,
236 target_ulong opcode, target_ulong *args)
237 {
238 int i;
239 target_ulong liobn = args[0];
240 target_ulong ioba = args[1];
241 target_ulong ioba1 = ioba;
242 target_ulong tce_list = args[2];
243 target_ulong npages = args[3];
244 target_ulong ret = H_PARAMETER;
245 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
246 CPUState *cs = CPU(cpu);
247 hwaddr page_mask, page_size;
248
249 if (!tcet) {
250 return H_PARAMETER;
251 }
252
253 if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
254 return H_PARAMETER;
255 }
256
257 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
258 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
259 ioba &= page_mask;
260
261 for (i = 0; i < npages; ++i, ioba += page_size) {
262 target_ulong off = (tce_list & ~SPAPR_TCE_RW) +
263 i * sizeof(target_ulong);
264 target_ulong tce = ldq_phys(cs->as, off);
265
266 ret = put_tce_emu(tcet, ioba, tce);
267 if (ret) {
268 break;
269 }
270 }
271
272 /* Trace last successful or the first problematic entry */
273 i = i ? (i - 1) : 0;
274 trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i,
275 ldq_phys(cs->as,
276 tce_list + i * sizeof(target_ulong)),
277 ret);
278
279 return ret;
280 }
281
282 static target_ulong h_stuff_tce(PowerPCCPU *cpu, sPAPREnvironment *spapr,
283 target_ulong opcode, target_ulong *args)
284 {
285 int i;
286 target_ulong liobn = args[0];
287 target_ulong ioba = args[1];
288 target_ulong tce_value = args[2];
289 target_ulong npages = args[3];
290 target_ulong ret = H_PARAMETER;
291 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
292 hwaddr page_mask, page_size;
293
294 if (!tcet) {
295 return H_PARAMETER;
296 }
297
298 if (npages > tcet->nb_table) {
299 return H_PARAMETER;
300 }
301
302 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
303 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
304 ioba &= page_mask;
305
306 for (i = 0; i < npages; ++i, ioba += page_size) {
307 ret = put_tce_emu(tcet, ioba, tce_value);
308 if (ret) {
309 break;
310 }
311 }
312 trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
313
314 return ret;
315 }
316
317 static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPREnvironment *spapr,
318 target_ulong opcode, target_ulong *args)
319 {
320 target_ulong liobn = args[0];
321 target_ulong ioba = args[1];
322 target_ulong tce = args[2];
323 target_ulong ret = H_PARAMETER;
324 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
325
326 if (tcet) {
327 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
328
329 ioba &= page_mask;
330
331 ret = put_tce_emu(tcet, ioba, tce);
332 }
333 trace_spapr_iommu_put(liobn, ioba, tce, ret);
334
335 return ret;
336 }
337
338 static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
339 target_ulong *tce)
340 {
341 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
342
343 if (index >= tcet->nb_table) {
344 hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
345 TARGET_FMT_lx "\n", ioba);
346 return H_PARAMETER;
347 }
348
349 *tce = tcet->table[index];
350
351 return H_SUCCESS;
352 }
353
354 static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPREnvironment *spapr,
355 target_ulong opcode, target_ulong *args)
356 {
357 target_ulong liobn = args[0];
358 target_ulong ioba = args[1];
359 target_ulong tce = 0;
360 target_ulong ret = H_PARAMETER;
361 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
362
363 if (tcet) {
364 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
365
366 ioba &= page_mask;
367
368 ret = get_tce_emu(tcet, ioba, &tce);
369 if (!ret) {
370 args[0] = tce;
371 }
372 }
373 trace_spapr_iommu_get(liobn, ioba, ret, tce);
374
375 return ret;
376 }
377
378 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
379 uint32_t liobn, uint64_t window, uint32_t size)
380 {
381 uint32_t dma_prop[5];
382 int ret;
383
384 dma_prop[0] = cpu_to_be32(liobn);
385 dma_prop[1] = cpu_to_be32(window >> 32);
386 dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
387 dma_prop[3] = 0; /* window size is 32 bits */
388 dma_prop[4] = cpu_to_be32(size);
389
390 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
391 if (ret < 0) {
392 return ret;
393 }
394
395 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
396 if (ret < 0) {
397 return ret;
398 }
399
400 ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
401 if (ret < 0) {
402 return ret;
403 }
404
405 return 0;
406 }
407
408 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
409 sPAPRTCETable *tcet)
410 {
411 if (!tcet) {
412 return 0;
413 }
414
415 return spapr_dma_dt(fdt, node_off, propname,
416 tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
417 }
418
419 static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
420 {
421 DeviceClass *dc = DEVICE_CLASS(klass);
422 dc->init = spapr_tce_table_realize;
423 dc->reset = spapr_tce_reset;
424 dc->unrealize = spapr_tce_table_unrealize;
425
426 QLIST_INIT(&spapr_tce_tables);
427
428 /* hcall-tce */
429 spapr_register_hypercall(H_PUT_TCE, h_put_tce);
430 spapr_register_hypercall(H_GET_TCE, h_get_tce);
431 spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
432 spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
433 }
434
435 static TypeInfo spapr_tce_table_info = {
436 .name = TYPE_SPAPR_TCE_TABLE,
437 .parent = TYPE_DEVICE,
438 .instance_size = sizeof(sPAPRTCETable),
439 .class_init = spapr_tce_table_class_init,
440 };
441
442 static void register_types(void)
443 {
444 type_register_static(&spapr_tce_table_info);
445 }
446
447 type_init(register_types);