2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
15 #include "hw/ppc/spapr.h"
16 #include "hw/ppc/spapr_cpu_core.h"
17 #include "hw/ppc/spapr_xive.h"
18 #include "hw/ppc/xics.h"
19 #include "hw/ppc/xics_spapr.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
22 #include "sysemu/kvm.h"
26 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
28 spapr
->irq_map_nr
= nr_msis
;
29 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
32 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
38 * The 'align_mask' parameter of bitmap_find_next_zero_area()
39 * should be one less than a power of 2; 0 means no
40 * alignment. Adapt the 'align' value of the former allocator
41 * to fit the requirements of bitmap_find_next_zero_area()
45 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
47 if (irq
== spapr
->irq_map_nr
) {
48 error_setg(errp
, "can't find a free %d-IRQ block", num
);
52 bitmap_set(spapr
->irq_map
, irq
, num
);
54 return irq
+ SPAPR_IRQ_MSI
;
57 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
59 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
62 void spapr_irq_msi_reset(SpaprMachineState
*spapr
)
64 bitmap_clear(spapr
->irq_map
, 0, spapr
->irq_map_nr
);
67 static void spapr_irq_init_kvm(SpaprMachineState
*spapr
,
68 SpaprIrq
*irq
, Error
**errp
)
70 MachineState
*machine
= MACHINE(spapr
);
71 Error
*local_err
= NULL
;
73 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
74 irq
->init_kvm(spapr
, &local_err
);
75 if (local_err
&& machine_kernel_irqchip_required(machine
)) {
76 error_prepend(&local_err
,
77 "kernel_irqchip requested but unavailable: ");
78 error_propagate(errp
, local_err
);
87 * We failed to initialize the KVM device, fallback to
90 error_prepend(&local_err
, "kernel_irqchip allowed but unavailable: ");
91 error_append_hint(&local_err
, "Falling back to kernel-irqchip=off\n");
92 warn_report_err(local_err
);
100 static void spapr_irq_init_xics(SpaprMachineState
*spapr
, int nr_irqs
,
104 Error
*local_err
= NULL
;
106 obj
= object_new(TYPE_ICS_SIMPLE
);
107 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
108 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
110 object_property_set_int(obj
, nr_irqs
, "nr-irqs", &error_fatal
);
111 object_property_set_bool(obj
, true, "realized", &local_err
);
113 error_propagate(errp
, local_err
);
117 spapr
->ics
= ICS_BASE(obj
);
119 xics_spapr_init(spapr
);
122 #define ICS_IRQ_FREE(ics, srcno) \
123 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
125 static int spapr_irq_claim_xics(SpaprMachineState
*spapr
, int irq
, bool lsi
,
128 ICSState
*ics
= spapr
->ics
;
132 if (!ics_valid_irq(ics
, irq
)) {
133 error_setg(errp
, "IRQ %d is invalid", irq
);
137 if (!ICS_IRQ_FREE(ics
, irq
- ics
->offset
)) {
138 error_setg(errp
, "IRQ %d is not free", irq
);
142 ics_set_irq_type(ics
, irq
- ics
->offset
, lsi
);
146 static void spapr_irq_free_xics(SpaprMachineState
*spapr
, int irq
, int num
)
148 ICSState
*ics
= spapr
->ics
;
149 uint32_t srcno
= irq
- ics
->offset
;
152 if (ics_valid_irq(ics
, irq
)) {
153 trace_spapr_irq_free(0, irq
, num
);
154 for (i
= srcno
; i
< srcno
+ num
; ++i
) {
155 if (ICS_IRQ_FREE(ics
, i
)) {
156 trace_spapr_irq_free_warn(0, i
);
158 memset(&ics
->irqs
[i
], 0, sizeof(ICSIRQState
));
163 static qemu_irq
spapr_qirq_xics(SpaprMachineState
*spapr
, int irq
)
165 ICSState
*ics
= spapr
->ics
;
166 uint32_t srcno
= irq
- ics
->offset
;
168 if (ics_valid_irq(ics
, irq
)) {
169 return spapr
->qirqs
[srcno
];
175 static void spapr_irq_print_info_xics(SpaprMachineState
*spapr
, Monitor
*mon
)
180 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
182 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
185 ics_pic_print_info(spapr
->ics
, mon
);
188 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState
*spapr
,
189 PowerPCCPU
*cpu
, Error
**errp
)
191 Error
*local_err
= NULL
;
193 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
195 obj
= icp_create(OBJECT(cpu
), TYPE_ICP
, XICS_FABRIC(spapr
),
198 error_propagate(errp
, local_err
);
202 spapr_cpu
->icp
= ICP(obj
);
205 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
207 if (!kvm_irqchip_in_kernel()) {
210 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
211 icp_resend(spapr_cpu_state(cpu
)->icp
);
217 static void spapr_irq_set_irq_xics(void *opaque
, int srcno
, int val
)
219 SpaprMachineState
*spapr
= opaque
;
221 ics_simple_set_irq(spapr
->ics
, srcno
, val
);
224 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
226 Error
*local_err
= NULL
;
228 spapr_irq_init_kvm(spapr
, &spapr_irq_xics
, &local_err
);
230 error_propagate(errp
, local_err
);
235 static const char *spapr_irq_get_nodename_xics(SpaprMachineState
*spapr
)
237 return XICS_NODENAME
;
240 static void spapr_irq_init_kvm_xics(SpaprMachineState
*spapr
, Error
**errp
)
243 xics_kvm_connect(spapr
, errp
);
247 #define SPAPR_IRQ_XICS_NR_IRQS 0x1000
248 #define SPAPR_IRQ_XICS_NR_MSIS \
249 (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
251 SpaprIrq spapr_irq_xics
= {
252 .nr_irqs
= SPAPR_IRQ_XICS_NR_IRQS
,
253 .nr_msis
= SPAPR_IRQ_XICS_NR_MSIS
,
254 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
256 .init
= spapr_irq_init_xics
,
257 .claim
= spapr_irq_claim_xics
,
258 .free
= spapr_irq_free_xics
,
259 .qirq
= spapr_qirq_xics
,
260 .print_info
= spapr_irq_print_info_xics
,
261 .dt_populate
= spapr_dt_xics
,
262 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
263 .post_load
= spapr_irq_post_load_xics
,
264 .reset
= spapr_irq_reset_xics
,
265 .set_irq
= spapr_irq_set_irq_xics
,
266 .get_nodename
= spapr_irq_get_nodename_xics
,
267 .init_kvm
= spapr_irq_init_kvm_xics
,
273 static void spapr_irq_init_xive(SpaprMachineState
*spapr
, int nr_irqs
,
276 uint32_t nr_servers
= spapr_max_server_number(spapr
);
280 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
281 qdev_prop_set_uint32(dev
, "nr-irqs", nr_irqs
);
283 * 8 XIVE END structures per CPU. One for each available priority
285 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
286 qdev_init_nofail(dev
);
288 spapr
->xive
= SPAPR_XIVE(dev
);
290 /* Enable the CPU IPIs */
291 for (i
= 0; i
< nr_servers
; ++i
) {
292 spapr_xive_irq_claim(spapr
->xive
, SPAPR_IRQ_IPI
+ i
, false);
295 spapr_xive_hcall_init(spapr
);
298 static int spapr_irq_claim_xive(SpaprMachineState
*spapr
, int irq
, bool lsi
,
301 if (!spapr_xive_irq_claim(spapr
->xive
, irq
, lsi
)) {
302 error_setg(errp
, "IRQ %d is invalid", irq
);
308 static void spapr_irq_free_xive(SpaprMachineState
*spapr
, int irq
, int num
)
312 for (i
= irq
; i
< irq
+ num
; ++i
) {
313 spapr_xive_irq_free(spapr
->xive
, i
);
317 static qemu_irq
spapr_qirq_xive(SpaprMachineState
*spapr
, int irq
)
319 SpaprXive
*xive
= spapr
->xive
;
321 if (irq
>= xive
->nr_irqs
) {
325 /* The sPAPR machine/device should have claimed the IRQ before */
326 assert(xive_eas_is_valid(&xive
->eat
[irq
]));
328 return spapr
->qirqs
[irq
];
331 static void spapr_irq_print_info_xive(SpaprMachineState
*spapr
,
337 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
339 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
342 spapr_xive_pic_print_info(spapr
->xive
, mon
);
345 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState
*spapr
,
346 PowerPCCPU
*cpu
, Error
**errp
)
348 Error
*local_err
= NULL
;
350 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
352 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(spapr
->xive
), &local_err
);
354 error_propagate(errp
, local_err
);
358 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
361 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
362 * don't beneficiate from the reset of the XIVE IRQ backend
364 spapr_xive_set_tctx_os_cam(spapr_cpu
->tctx
);
367 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
369 return spapr_xive_post_load(spapr
->xive
, version_id
);
372 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
375 Error
*local_err
= NULL
;
378 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
380 /* (TCG) Set the OS CAM line of the thread interrupt context. */
381 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
384 spapr_irq_init_kvm(spapr
, &spapr_irq_xive
, &local_err
);
386 error_propagate(errp
, local_err
);
390 /* Activate the XIVE MMIOs */
391 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
394 static void spapr_irq_set_irq_xive(void *opaque
, int srcno
, int val
)
396 SpaprMachineState
*spapr
= opaque
;
398 if (kvm_irqchip_in_kernel()) {
399 kvmppc_xive_source_set_irq(&spapr
->xive
->source
, srcno
, val
);
401 xive_source_set_irq(&spapr
->xive
->source
, srcno
, val
);
405 static const char *spapr_irq_get_nodename_xive(SpaprMachineState
*spapr
)
407 return spapr
->xive
->nodename
;
410 static void spapr_irq_init_kvm_xive(SpaprMachineState
*spapr
, Error
**errp
)
413 kvmppc_xive_connect(spapr
->xive
, errp
);
418 * XIVE uses the full IRQ number space. Set it to 8K to be compatible
422 #define SPAPR_IRQ_XIVE_NR_IRQS 0x2000
423 #define SPAPR_IRQ_XIVE_NR_MSIS (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
425 SpaprIrq spapr_irq_xive
= {
426 .nr_irqs
= SPAPR_IRQ_XIVE_NR_IRQS
,
427 .nr_msis
= SPAPR_IRQ_XIVE_NR_MSIS
,
428 .ov5
= SPAPR_OV5_XIVE_EXPLOIT
,
430 .init
= spapr_irq_init_xive
,
431 .claim
= spapr_irq_claim_xive
,
432 .free
= spapr_irq_free_xive
,
433 .qirq
= spapr_qirq_xive
,
434 .print_info
= spapr_irq_print_info_xive
,
435 .dt_populate
= spapr_dt_xive
,
436 .cpu_intc_create
= spapr_irq_cpu_intc_create_xive
,
437 .post_load
= spapr_irq_post_load_xive
,
438 .reset
= spapr_irq_reset_xive
,
439 .set_irq
= spapr_irq_set_irq_xive
,
440 .get_nodename
= spapr_irq_get_nodename_xive
,
441 .init_kvm
= spapr_irq_init_kvm_xive
,
445 * Dual XIVE and XICS IRQ backend.
447 * Both interrupt mode, XIVE and XICS, objects are created but the
448 * machine starts in legacy interrupt mode (XICS). It can be changed
449 * by the CAS negotiation process and, in that case, the new mode is
450 * activated after an extra machine reset.
454 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
457 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
459 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
460 &spapr_irq_xive
: &spapr_irq_xics
;
463 static void spapr_irq_init_dual(SpaprMachineState
*spapr
, int nr_irqs
,
466 Error
*local_err
= NULL
;
468 spapr_irq_xics
.init(spapr
, spapr_irq_xics
.nr_irqs
, &local_err
);
470 error_propagate(errp
, local_err
);
474 spapr_irq_xive
.init(spapr
, spapr_irq_xive
.nr_irqs
, &local_err
);
476 error_propagate(errp
, local_err
);
481 static int spapr_irq_claim_dual(SpaprMachineState
*spapr
, int irq
, bool lsi
,
484 Error
*local_err
= NULL
;
487 ret
= spapr_irq_xics
.claim(spapr
, irq
, lsi
, &local_err
);
489 error_propagate(errp
, local_err
);
493 ret
= spapr_irq_xive
.claim(spapr
, irq
, lsi
, &local_err
);
495 error_propagate(errp
, local_err
);
502 static void spapr_irq_free_dual(SpaprMachineState
*spapr
, int irq
, int num
)
504 spapr_irq_xics
.free(spapr
, irq
, num
);
505 spapr_irq_xive
.free(spapr
, irq
, num
);
508 static qemu_irq
spapr_qirq_dual(SpaprMachineState
*spapr
, int irq
)
510 return spapr_irq_current(spapr
)->qirq(spapr
, irq
);
513 static void spapr_irq_print_info_dual(SpaprMachineState
*spapr
, Monitor
*mon
)
515 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
518 static void spapr_irq_dt_populate_dual(SpaprMachineState
*spapr
,
519 uint32_t nr_servers
, void *fdt
,
522 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
525 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState
*spapr
,
526 PowerPCCPU
*cpu
, Error
**errp
)
528 Error
*local_err
= NULL
;
530 spapr_irq_xive
.cpu_intc_create(spapr
, cpu
, &local_err
);
532 error_propagate(errp
, local_err
);
536 spapr_irq_xics
.cpu_intc_create(spapr
, cpu
, errp
);
539 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
542 * Force a reset of the XIVE backend after migration. The machine
543 * defaults to XICS at startup.
545 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
546 if (kvm_irqchip_in_kernel()) {
547 xics_kvm_disconnect(spapr
, &error_fatal
);
549 spapr_irq_xive
.reset(spapr
, &error_fatal
);
552 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
555 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
557 Error
*local_err
= NULL
;
560 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
563 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
565 /* Destroy all KVM devices */
566 if (kvm_irqchip_in_kernel()) {
567 xics_kvm_disconnect(spapr
, &local_err
);
569 error_propagate(errp
, local_err
);
570 error_prepend(errp
, "KVM XICS disconnect failed: ");
573 kvmppc_xive_disconnect(spapr
->xive
, &local_err
);
575 error_propagate(errp
, local_err
);
576 error_prepend(errp
, "KVM XIVE disconnect failed: ");
581 spapr_irq_current(spapr
)->reset(spapr
, errp
);
584 static void spapr_irq_set_irq_dual(void *opaque
, int srcno
, int val
)
586 SpaprMachineState
*spapr
= opaque
;
588 spapr_irq_current(spapr
)->set_irq(spapr
, srcno
, val
);
591 static const char *spapr_irq_get_nodename_dual(SpaprMachineState
*spapr
)
593 return spapr_irq_current(spapr
)->get_nodename(spapr
);
597 * Define values in sync with the XIVE and XICS backend
599 #define SPAPR_IRQ_DUAL_NR_IRQS 0x2000
600 #define SPAPR_IRQ_DUAL_NR_MSIS (SPAPR_IRQ_DUAL_NR_IRQS - SPAPR_IRQ_MSI)
602 SpaprIrq spapr_irq_dual
= {
603 .nr_irqs
= SPAPR_IRQ_DUAL_NR_IRQS
,
604 .nr_msis
= SPAPR_IRQ_DUAL_NR_MSIS
,
605 .ov5
= SPAPR_OV5_XIVE_BOTH
,
607 .init
= spapr_irq_init_dual
,
608 .claim
= spapr_irq_claim_dual
,
609 .free
= spapr_irq_free_dual
,
610 .qirq
= spapr_qirq_dual
,
611 .print_info
= spapr_irq_print_info_dual
,
612 .dt_populate
= spapr_irq_dt_populate_dual
,
613 .cpu_intc_create
= spapr_irq_cpu_intc_create_dual
,
614 .post_load
= spapr_irq_post_load_dual
,
615 .reset
= spapr_irq_reset_dual
,
616 .set_irq
= spapr_irq_set_irq_dual
,
617 .get_nodename
= spapr_irq_get_nodename_dual
,
618 .init_kvm
= NULL
, /* should not be used */
622 static void spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
624 MachineState
*machine
= MACHINE(spapr
);
627 * Sanity checks on non-P9 machines. On these, XIVE is not
628 * advertised, see spapr_dt_ov5_platform_support()
630 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
631 0, spapr
->max_compat_pvr
)) {
633 * If the 'dual' interrupt mode is selected, force XICS as CAS
634 * negotiation is useless.
636 if (spapr
->irq
== &spapr_irq_dual
) {
637 spapr
->irq
= &spapr_irq_xics
;
642 * Non-P9 machines using only XIVE is a bogus setup. We have two
643 * scenarios to take into account because of the compat mode:
645 * 1. POWER7/8 machines should fail to init later on when creating
646 * the XIVE interrupt presenters because a POWER9 exception
649 * 2. POWER9 machines using the POWER8 compat mode won't fail and
650 * will let the OS boot with a partial XIVE setup : DT
651 * properties but no hcalls.
653 * To cover both and not confuse the OS, add an early failure in
656 if (spapr
->irq
== &spapr_irq_xive
) {
657 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
663 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
664 * re-created. Detect that early to avoid QEMU to exit later when the
668 spapr
->irq
== &spapr_irq_dual
&&
669 machine_kernel_irqchip_required(machine
) &&
670 xics_kvm_has_broken_disconnect(spapr
)) {
671 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
677 * sPAPR IRQ frontend routines for devices
679 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
681 MachineState
*machine
= MACHINE(spapr
);
682 Error
*local_err
= NULL
;
684 if (machine_kernel_irqchip_split(machine
)) {
685 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
689 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
691 "kernel_irqchip requested but only available with KVM");
695 spapr_irq_check(spapr
, &local_err
);
697 error_propagate(errp
, local_err
);
701 /* Initialize the MSI IRQ allocator. */
702 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
703 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
706 spapr
->irq
->init(spapr
, spapr
->irq
->nr_irqs
, errp
);
708 spapr
->qirqs
= qemu_allocate_irqs(spapr
->irq
->set_irq
, spapr
,
709 spapr
->irq
->nr_irqs
);
712 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
714 return spapr
->irq
->claim(spapr
, irq
, lsi
, errp
);
717 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
719 spapr
->irq
->free(spapr
, irq
, num
);
722 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
724 return spapr
->irq
->qirq(spapr
, irq
);
727 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
729 return spapr
->irq
->post_load(spapr
, version_id
);
732 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
734 if (spapr
->irq
->reset
) {
735 spapr
->irq
->reset(spapr
, errp
);
739 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
741 const char *nodename
= spapr
->irq
->get_nodename(spapr
);
744 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
746 error_setg(errp
, "Can't find node \"%s\": %s", nodename
,
747 fdt_strerror(offset
));
751 phandle
= fdt_get_phandle(fdt
, offset
);
753 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
761 * XICS legacy routines - to deprecate one day
764 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
768 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
769 if (num
> (ics
->nr_irqs
- first
)) {
772 for (i
= first
; i
< first
+ num
; ++i
) {
773 if (!ICS_IRQ_FREE(ics
, i
)) {
777 if (i
== (first
+ num
)) {
785 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
787 ICSState
*ics
= spapr
->ics
;
793 * MSIMesage::data is used for storing VIRQ so
794 * it has to be aligned to num to support multiple
795 * MSI vectors. MSI-X is not affected by this.
796 * The hint is used for the first IRQ, the rest should
797 * be allocated continuously.
800 assert((num
== 1) || (num
== 2) || (num
== 4) ||
801 (num
== 8) || (num
== 16) || (num
== 32));
802 first
= ics_find_free_block(ics
, num
, num
);
804 first
= ics_find_free_block(ics
, num
, 1);
808 error_setg(errp
, "can't find a free %d-IRQ block", num
);
812 return first
+ ics
->offset
;
815 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS 0x400
817 SpaprIrq spapr_irq_xics_legacy
= {
818 .nr_irqs
= SPAPR_IRQ_XICS_LEGACY_NR_IRQS
,
819 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_IRQS
,
820 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
822 .init
= spapr_irq_init_xics
,
823 .claim
= spapr_irq_claim_xics
,
824 .free
= spapr_irq_free_xics
,
825 .qirq
= spapr_qirq_xics
,
826 .print_info
= spapr_irq_print_info_xics
,
827 .dt_populate
= spapr_dt_xics
,
828 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
829 .post_load
= spapr_irq_post_load_xics
,
830 .reset
= spapr_irq_reset_xics
,
831 .set_irq
= spapr_irq_set_irq_xics
,
832 .get_nodename
= spapr_irq_get_nodename_xics
,
833 .init_kvm
= spapr_irq_init_kvm_xics
,