2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
15 #include "hw/ppc/spapr.h"
16 #include "hw/ppc/spapr_cpu_core.h"
17 #include "hw/ppc/spapr_xive.h"
18 #include "hw/ppc/xics.h"
19 #include "hw/ppc/xics_spapr.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
22 #include "sysemu/kvm.h"
26 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
28 spapr
->irq_map_nr
= nr_msis
;
29 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
32 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
38 * The 'align_mask' parameter of bitmap_find_next_zero_area()
39 * should be one less than a power of 2; 0 means no
40 * alignment. Adapt the 'align' value of the former allocator
41 * to fit the requirements of bitmap_find_next_zero_area()
45 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
47 if (irq
== spapr
->irq_map_nr
) {
48 error_setg(errp
, "can't find a free %d-IRQ block", num
);
52 bitmap_set(spapr
->irq_map
, irq
, num
);
54 return irq
+ SPAPR_IRQ_MSI
;
57 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
59 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
62 static void spapr_irq_init_kvm(SpaprMachineState
*spapr
,
63 SpaprIrq
*irq
, Error
**errp
)
65 MachineState
*machine
= MACHINE(spapr
);
66 Error
*local_err
= NULL
;
68 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
69 irq
->init_kvm(spapr
, &local_err
);
70 if (local_err
&& machine_kernel_irqchip_required(machine
)) {
71 error_prepend(&local_err
,
72 "kernel_irqchip requested but unavailable: ");
73 error_propagate(errp
, local_err
);
82 * We failed to initialize the KVM device, fallback to
85 error_prepend(&local_err
, "kernel_irqchip allowed but unavailable: ");
86 error_append_hint(&local_err
, "Falling back to kernel-irqchip=off\n");
87 warn_report_err(local_err
);
95 static void spapr_irq_init_xics(SpaprMachineState
*spapr
, Error
**errp
)
98 Error
*local_err
= NULL
;
100 obj
= object_new(TYPE_ICS_SPAPR
);
101 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
102 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
104 object_property_set_int(obj
, spapr
->irq
->nr_xirqs
,
105 "nr-irqs", &error_fatal
);
106 object_property_set_bool(obj
, true, "realized", &local_err
);
108 error_propagate(errp
, local_err
);
112 spapr
->ics
= ICS_SPAPR(obj
);
115 static int spapr_irq_claim_xics(SpaprMachineState
*spapr
, int irq
, bool lsi
,
118 ICSState
*ics
= spapr
->ics
;
122 if (!ics_valid_irq(ics
, irq
)) {
123 error_setg(errp
, "IRQ %d is invalid", irq
);
127 if (!ics_irq_free(ics
, irq
- ics
->offset
)) {
128 error_setg(errp
, "IRQ %d is not free", irq
);
132 ics_set_irq_type(ics
, irq
- ics
->offset
, lsi
);
136 static void spapr_irq_free_xics(SpaprMachineState
*spapr
, int irq
)
138 ICSState
*ics
= spapr
->ics
;
139 uint32_t srcno
= irq
- ics
->offset
;
141 if (ics_valid_irq(ics
, irq
)) {
142 memset(&ics
->irqs
[srcno
], 0, sizeof(ICSIRQState
));
146 static void spapr_irq_print_info_xics(SpaprMachineState
*spapr
, Monitor
*mon
)
151 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
153 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
156 ics_pic_print_info(spapr
->ics
, mon
);
159 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState
*spapr
,
160 PowerPCCPU
*cpu
, Error
**errp
)
162 Error
*local_err
= NULL
;
164 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
166 obj
= icp_create(OBJECT(cpu
), TYPE_ICP
, XICS_FABRIC(spapr
),
169 error_propagate(errp
, local_err
);
173 spapr_cpu
->icp
= ICP(obj
);
176 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
178 if (!kvm_irqchip_in_kernel()) {
181 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
182 icp_resend(spapr_cpu_state(cpu
)->icp
);
188 static void spapr_irq_set_irq_xics(void *opaque
, int irq
, int val
)
190 SpaprMachineState
*spapr
= opaque
;
191 uint32_t srcno
= irq
- spapr
->ics
->offset
;
193 ics_set_irq(spapr
->ics
, srcno
, val
);
196 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
198 Error
*local_err
= NULL
;
200 spapr_irq_init_kvm(spapr
, &spapr_irq_xics
, &local_err
);
202 error_propagate(errp
, local_err
);
207 static void spapr_irq_init_kvm_xics(SpaprMachineState
*spapr
, Error
**errp
)
210 xics_kvm_connect(spapr
, errp
);
214 SpaprIrq spapr_irq_xics
= {
215 .nr_xirqs
= SPAPR_NR_XIRQS
,
216 .nr_msis
= SPAPR_NR_MSIS
,
217 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
219 .init
= spapr_irq_init_xics
,
220 .claim
= spapr_irq_claim_xics
,
221 .free
= spapr_irq_free_xics
,
222 .print_info
= spapr_irq_print_info_xics
,
223 .dt_populate
= spapr_dt_xics
,
224 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
225 .post_load
= spapr_irq_post_load_xics
,
226 .reset
= spapr_irq_reset_xics
,
227 .set_irq
= spapr_irq_set_irq_xics
,
228 .init_kvm
= spapr_irq_init_kvm_xics
,
234 static void spapr_irq_init_xive(SpaprMachineState
*spapr
, Error
**errp
)
236 uint32_t nr_servers
= spapr_max_server_number(spapr
);
240 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
241 qdev_prop_set_uint32(dev
, "nr-irqs",
242 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
244 * 8 XIVE END structures per CPU. One for each available priority
246 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
247 qdev_init_nofail(dev
);
249 spapr
->xive
= SPAPR_XIVE(dev
);
251 /* Enable the CPU IPIs */
252 for (i
= 0; i
< nr_servers
; ++i
) {
253 spapr_xive_irq_claim(spapr
->xive
, SPAPR_IRQ_IPI
+ i
, false);
256 spapr_xive_hcall_init(spapr
);
259 static int spapr_irq_claim_xive(SpaprMachineState
*spapr
, int irq
, bool lsi
,
262 if (!spapr_xive_irq_claim(spapr
->xive
, irq
, lsi
)) {
263 error_setg(errp
, "IRQ %d is invalid", irq
);
269 static void spapr_irq_free_xive(SpaprMachineState
*spapr
, int irq
)
271 spapr_xive_irq_free(spapr
->xive
, irq
);
274 static void spapr_irq_print_info_xive(SpaprMachineState
*spapr
,
280 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
282 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
285 spapr_xive_pic_print_info(spapr
->xive
, mon
);
288 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState
*spapr
,
289 PowerPCCPU
*cpu
, Error
**errp
)
291 Error
*local_err
= NULL
;
293 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
295 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(spapr
->xive
), &local_err
);
297 error_propagate(errp
, local_err
);
301 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
304 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
305 * don't beneficiate from the reset of the XIVE IRQ backend
307 spapr_xive_set_tctx_os_cam(spapr_cpu
->tctx
);
310 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
312 return spapr_xive_post_load(spapr
->xive
, version_id
);
315 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
318 Error
*local_err
= NULL
;
321 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
323 /* (TCG) Set the OS CAM line of the thread interrupt context. */
324 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
327 spapr_irq_init_kvm(spapr
, &spapr_irq_xive
, &local_err
);
329 error_propagate(errp
, local_err
);
333 /* Activate the XIVE MMIOs */
334 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
337 static void spapr_irq_set_irq_xive(void *opaque
, int irq
, int val
)
339 SpaprMachineState
*spapr
= opaque
;
341 if (kvm_irqchip_in_kernel()) {
342 kvmppc_xive_source_set_irq(&spapr
->xive
->source
, irq
, val
);
344 xive_source_set_irq(&spapr
->xive
->source
, irq
, val
);
348 static void spapr_irq_init_kvm_xive(SpaprMachineState
*spapr
, Error
**errp
)
351 kvmppc_xive_connect(spapr
->xive
, errp
);
355 SpaprIrq spapr_irq_xive
= {
356 .nr_xirqs
= SPAPR_NR_XIRQS
,
357 .nr_msis
= SPAPR_NR_MSIS
,
358 .ov5
= SPAPR_OV5_XIVE_EXPLOIT
,
360 .init
= spapr_irq_init_xive
,
361 .claim
= spapr_irq_claim_xive
,
362 .free
= spapr_irq_free_xive
,
363 .print_info
= spapr_irq_print_info_xive
,
364 .dt_populate
= spapr_dt_xive
,
365 .cpu_intc_create
= spapr_irq_cpu_intc_create_xive
,
366 .post_load
= spapr_irq_post_load_xive
,
367 .reset
= spapr_irq_reset_xive
,
368 .set_irq
= spapr_irq_set_irq_xive
,
369 .init_kvm
= spapr_irq_init_kvm_xive
,
373 * Dual XIVE and XICS IRQ backend.
375 * Both interrupt mode, XIVE and XICS, objects are created but the
376 * machine starts in legacy interrupt mode (XICS). It can be changed
377 * by the CAS negotiation process and, in that case, the new mode is
378 * activated after an extra machine reset.
382 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
385 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
387 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
388 &spapr_irq_xive
: &spapr_irq_xics
;
391 static void spapr_irq_init_dual(SpaprMachineState
*spapr
, Error
**errp
)
393 Error
*local_err
= NULL
;
395 spapr_irq_xics
.init(spapr
, &local_err
);
397 error_propagate(errp
, local_err
);
401 spapr_irq_xive
.init(spapr
, &local_err
);
403 error_propagate(errp
, local_err
);
408 static int spapr_irq_claim_dual(SpaprMachineState
*spapr
, int irq
, bool lsi
,
411 Error
*local_err
= NULL
;
414 ret
= spapr_irq_xics
.claim(spapr
, irq
, lsi
, &local_err
);
416 error_propagate(errp
, local_err
);
420 ret
= spapr_irq_xive
.claim(spapr
, irq
, lsi
, &local_err
);
422 error_propagate(errp
, local_err
);
429 static void spapr_irq_free_dual(SpaprMachineState
*spapr
, int irq
)
431 spapr_irq_xics
.free(spapr
, irq
);
432 spapr_irq_xive
.free(spapr
, irq
);
435 static void spapr_irq_print_info_dual(SpaprMachineState
*spapr
, Monitor
*mon
)
437 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
440 static void spapr_irq_dt_populate_dual(SpaprMachineState
*spapr
,
441 uint32_t nr_servers
, void *fdt
,
444 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
447 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState
*spapr
,
448 PowerPCCPU
*cpu
, Error
**errp
)
450 Error
*local_err
= NULL
;
452 spapr_irq_xive
.cpu_intc_create(spapr
, cpu
, &local_err
);
454 error_propagate(errp
, local_err
);
458 spapr_irq_xics
.cpu_intc_create(spapr
, cpu
, errp
);
461 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
464 * Force a reset of the XIVE backend after migration. The machine
465 * defaults to XICS at startup.
467 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
468 if (kvm_irqchip_in_kernel()) {
469 xics_kvm_disconnect(spapr
, &error_fatal
);
471 spapr_irq_xive
.reset(spapr
, &error_fatal
);
474 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
477 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
479 Error
*local_err
= NULL
;
482 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
485 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
487 /* Destroy all KVM devices */
488 if (kvm_irqchip_in_kernel()) {
489 xics_kvm_disconnect(spapr
, &local_err
);
491 error_propagate(errp
, local_err
);
492 error_prepend(errp
, "KVM XICS disconnect failed: ");
495 kvmppc_xive_disconnect(spapr
->xive
, &local_err
);
497 error_propagate(errp
, local_err
);
498 error_prepend(errp
, "KVM XIVE disconnect failed: ");
503 spapr_irq_current(spapr
)->reset(spapr
, errp
);
506 static void spapr_irq_set_irq_dual(void *opaque
, int irq
, int val
)
508 SpaprMachineState
*spapr
= opaque
;
510 spapr_irq_current(spapr
)->set_irq(spapr
, irq
, val
);
514 * Define values in sync with the XIVE and XICS backend
516 SpaprIrq spapr_irq_dual
= {
517 .nr_xirqs
= SPAPR_NR_XIRQS
,
518 .nr_msis
= SPAPR_NR_MSIS
,
519 .ov5
= SPAPR_OV5_XIVE_BOTH
,
521 .init
= spapr_irq_init_dual
,
522 .claim
= spapr_irq_claim_dual
,
523 .free
= spapr_irq_free_dual
,
524 .print_info
= spapr_irq_print_info_dual
,
525 .dt_populate
= spapr_irq_dt_populate_dual
,
526 .cpu_intc_create
= spapr_irq_cpu_intc_create_dual
,
527 .post_load
= spapr_irq_post_load_dual
,
528 .reset
= spapr_irq_reset_dual
,
529 .set_irq
= spapr_irq_set_irq_dual
,
530 .init_kvm
= NULL
, /* should not be used */
534 static void spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
536 MachineState
*machine
= MACHINE(spapr
);
539 * Sanity checks on non-P9 machines. On these, XIVE is not
540 * advertised, see spapr_dt_ov5_platform_support()
542 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
543 0, spapr
->max_compat_pvr
)) {
545 * If the 'dual' interrupt mode is selected, force XICS as CAS
546 * negotiation is useless.
548 if (spapr
->irq
== &spapr_irq_dual
) {
549 spapr
->irq
= &spapr_irq_xics
;
554 * Non-P9 machines using only XIVE is a bogus setup. We have two
555 * scenarios to take into account because of the compat mode:
557 * 1. POWER7/8 machines should fail to init later on when creating
558 * the XIVE interrupt presenters because a POWER9 exception
561 * 2. POWER9 machines using the POWER8 compat mode won't fail and
562 * will let the OS boot with a partial XIVE setup : DT
563 * properties but no hcalls.
565 * To cover both and not confuse the OS, add an early failure in
568 if (spapr
->irq
== &spapr_irq_xive
) {
569 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
575 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
576 * re-created. Detect that early to avoid QEMU to exit later when the
580 spapr
->irq
== &spapr_irq_dual
&&
581 machine_kernel_irqchip_required(machine
) &&
582 xics_kvm_has_broken_disconnect(spapr
)) {
583 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
589 * sPAPR IRQ frontend routines for devices
591 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
593 MachineState
*machine
= MACHINE(spapr
);
594 Error
*local_err
= NULL
;
596 if (machine_kernel_irqchip_split(machine
)) {
597 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
601 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
603 "kernel_irqchip requested but only available with KVM");
607 spapr_irq_check(spapr
, &local_err
);
609 error_propagate(errp
, local_err
);
613 /* Initialize the MSI IRQ allocator. */
614 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
615 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
618 spapr
->irq
->init(spapr
, errp
);
620 spapr
->qirqs
= qemu_allocate_irqs(spapr
->irq
->set_irq
, spapr
,
621 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
624 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
626 return spapr
->irq
->claim(spapr
, irq
, lsi
, errp
);
629 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
633 for (i
= irq
; i
< (irq
+ num
); i
++) {
634 spapr
->irq
->free(spapr
, i
);
638 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
641 * This interface is basically for VIO and PHB devices to find the
642 * right qemu_irq to manipulate, so we only allow access to the
643 * external irqs for now. Currently anything which needs to
644 * access the IPIs most naturally gets there via the guest side
645 * interfaces, we can change this if we need to in future.
647 assert(irq
>= SPAPR_XIRQ_BASE
);
648 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
651 assert(ics_valid_irq(spapr
->ics
, irq
));
654 assert(irq
< spapr
->xive
->nr_irqs
);
655 assert(xive_eas_is_valid(&spapr
->xive
->eat
[irq
]));
658 return spapr
->qirqs
[irq
];
661 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
663 return spapr
->irq
->post_load(spapr
, version_id
);
666 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
668 assert(!spapr
->irq_map
|| bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
));
670 if (spapr
->irq
->reset
) {
671 spapr
->irq
->reset(spapr
, errp
);
675 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
677 const char *nodename
= "interrupt-controller";
680 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
682 error_setg(errp
, "Can't find node \"%s\": %s",
683 nodename
, fdt_strerror(offset
));
687 phandle
= fdt_get_phandle(fdt
, offset
);
689 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
697 * XICS legacy routines - to deprecate one day
700 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
704 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
705 if (num
> (ics
->nr_irqs
- first
)) {
708 for (i
= first
; i
< first
+ num
; ++i
) {
709 if (!ics_irq_free(ics
, i
)) {
713 if (i
== (first
+ num
)) {
721 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
723 ICSState
*ics
= spapr
->ics
;
729 * MSIMesage::data is used for storing VIRQ so
730 * it has to be aligned to num to support multiple
731 * MSI vectors. MSI-X is not affected by this.
732 * The hint is used for the first IRQ, the rest should
733 * be allocated continuously.
736 assert((num
== 1) || (num
== 2) || (num
== 4) ||
737 (num
== 8) || (num
== 16) || (num
== 32));
738 first
= ics_find_free_block(ics
, num
, num
);
740 first
= ics_find_free_block(ics
, num
, 1);
744 error_setg(errp
, "can't find a free %d-IRQ block", num
);
748 return first
+ ics
->offset
;
751 #define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400
753 SpaprIrq spapr_irq_xics_legacy
= {
754 .nr_xirqs
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
755 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
756 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
758 .init
= spapr_irq_init_xics
,
759 .claim
= spapr_irq_claim_xics
,
760 .free
= spapr_irq_free_xics
,
761 .print_info
= spapr_irq_print_info_xics
,
762 .dt_populate
= spapr_dt_xics
,
763 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
764 .post_load
= spapr_irq_post_load_xics
,
765 .reset
= spapr_irq_reset_xics
,
766 .set_irq
= spapr_irq_set_irq_xics
,
767 .init_kvm
= spapr_irq_init_kvm_xics
,