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Merge remote-tracking branch 'remotes/kraxel/tags/ipxe-pull-request' into staging
[mirror_qemu.git] / hw / ppc / spapr_pci.c
1 /*
2 * QEMU sPAPR PCI host originated from Uninorth PCI host
3 *
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "cpu.h"
29 #include "hw/hw.h"
30 #include "hw/sysbus.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/msi.h"
33 #include "hw/pci/msix.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/ppc/spapr.h"
36 #include "hw/pci-host/spapr.h"
37 #include "exec/address-spaces.h"
38 #include "exec/ram_addr.h"
39 #include <libfdt.h>
40 #include "trace.h"
41 #include "qemu/error-report.h"
42 #include "qapi/qmp/qerror.h"
43
44 #include "hw/pci/pci_bridge.h"
45 #include "hw/pci/pci_bus.h"
46 #include "hw/pci/pci_ids.h"
47 #include "hw/ppc/spapr_drc.h"
48 #include "sysemu/device_tree.h"
49 #include "sysemu/kvm.h"
50 #include "sysemu/hostmem.h"
51 #include "sysemu/numa.h"
52
53 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
54 #define RTAS_QUERY_FN 0
55 #define RTAS_CHANGE_FN 1
56 #define RTAS_RESET_FN 2
57 #define RTAS_CHANGE_MSI_FN 3
58 #define RTAS_CHANGE_MSIX_FN 4
59
60 /* Interrupt types to return on RTAS_CHANGE_* */
61 #define RTAS_TYPE_MSI 1
62 #define RTAS_TYPE_MSIX 2
63
64 #define FDT_NAME_MAX 128
65
66 #define _FDT(exp) \
67 do { \
68 int ret = (exp); \
69 if (ret < 0) { \
70 return ret; \
71 } \
72 } while (0)
73
74 sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid)
75 {
76 sPAPRPHBState *sphb;
77
78 QLIST_FOREACH(sphb, &spapr->phbs, list) {
79 if (sphb->buid != buid) {
80 continue;
81 }
82 return sphb;
83 }
84
85 return NULL;
86 }
87
88 PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
89 uint32_t config_addr)
90 {
91 sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
92 PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
93 int bus_num = (config_addr >> 16) & 0xFF;
94 int devfn = (config_addr >> 8) & 0xFF;
95
96 if (!phb) {
97 return NULL;
98 }
99
100 return pci_find_device(phb->bus, bus_num, devfn);
101 }
102
103 static uint32_t rtas_pci_cfgaddr(uint32_t arg)
104 {
105 /* This handles the encoding of extended config space addresses */
106 return ((arg >> 20) & 0xf00) | (arg & 0xff);
107 }
108
109 static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid,
110 uint32_t addr, uint32_t size,
111 target_ulong rets)
112 {
113 PCIDevice *pci_dev;
114 uint32_t val;
115
116 if ((size != 1) && (size != 2) && (size != 4)) {
117 /* access must be 1, 2 or 4 bytes */
118 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
119 return;
120 }
121
122 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
123 addr = rtas_pci_cfgaddr(addr);
124
125 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
126 /* Access must be to a valid device, within bounds and
127 * naturally aligned */
128 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
129 return;
130 }
131
132 val = pci_host_config_read_common(pci_dev, addr,
133 pci_config_size(pci_dev), size);
134
135 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
136 rtas_st(rets, 1, val);
137 }
138
139 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
140 uint32_t token, uint32_t nargs,
141 target_ulong args,
142 uint32_t nret, target_ulong rets)
143 {
144 uint64_t buid;
145 uint32_t size, addr;
146
147 if ((nargs != 4) || (nret != 2)) {
148 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
149 return;
150 }
151
152 buid = rtas_ldq(args, 1);
153 size = rtas_ld(args, 3);
154 addr = rtas_ld(args, 0);
155
156 finish_read_pci_config(spapr, buid, addr, size, rets);
157 }
158
159 static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
160 uint32_t token, uint32_t nargs,
161 target_ulong args,
162 uint32_t nret, target_ulong rets)
163 {
164 uint32_t size, addr;
165
166 if ((nargs != 2) || (nret != 2)) {
167 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
168 return;
169 }
170
171 size = rtas_ld(args, 1);
172 addr = rtas_ld(args, 0);
173
174 finish_read_pci_config(spapr, 0, addr, size, rets);
175 }
176
177 static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid,
178 uint32_t addr, uint32_t size,
179 uint32_t val, target_ulong rets)
180 {
181 PCIDevice *pci_dev;
182
183 if ((size != 1) && (size != 2) && (size != 4)) {
184 /* access must be 1, 2 or 4 bytes */
185 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
186 return;
187 }
188
189 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
190 addr = rtas_pci_cfgaddr(addr);
191
192 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
193 /* Access must be to a valid device, within bounds and
194 * naturally aligned */
195 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
196 return;
197 }
198
199 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
200 val, size);
201
202 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
203 }
204
205 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
206 uint32_t token, uint32_t nargs,
207 target_ulong args,
208 uint32_t nret, target_ulong rets)
209 {
210 uint64_t buid;
211 uint32_t val, size, addr;
212
213 if ((nargs != 5) || (nret != 1)) {
214 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
215 return;
216 }
217
218 buid = rtas_ldq(args, 1);
219 val = rtas_ld(args, 4);
220 size = rtas_ld(args, 3);
221 addr = rtas_ld(args, 0);
222
223 finish_write_pci_config(spapr, buid, addr, size, val, rets);
224 }
225
226 static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
227 uint32_t token, uint32_t nargs,
228 target_ulong args,
229 uint32_t nret, target_ulong rets)
230 {
231 uint32_t val, size, addr;
232
233 if ((nargs != 3) || (nret != 1)) {
234 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
235 return;
236 }
237
238
239 val = rtas_ld(args, 2);
240 size = rtas_ld(args, 1);
241 addr = rtas_ld(args, 0);
242
243 finish_write_pci_config(spapr, 0, addr, size, val, rets);
244 }
245
246 /*
247 * Set MSI/MSIX message data.
248 * This is required for msi_notify()/msix_notify() which
249 * will write at the addresses via spapr_msi_write().
250 *
251 * If hwaddr == 0, all entries will have .data == first_irq i.e.
252 * table will be reset.
253 */
254 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix,
255 unsigned first_irq, unsigned req_num)
256 {
257 unsigned i;
258 MSIMessage msg = { .address = addr, .data = first_irq };
259
260 if (!msix) {
261 msi_set_message(pdev, msg);
262 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
263 return;
264 }
265
266 for (i = 0; i < req_num; ++i) {
267 msix_set_message(pdev, i, msg);
268 trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
269 if (addr) {
270 ++msg.data;
271 }
272 }
273 }
274
275 static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
276 uint32_t token, uint32_t nargs,
277 target_ulong args, uint32_t nret,
278 target_ulong rets)
279 {
280 uint32_t config_addr = rtas_ld(args, 0);
281 uint64_t buid = rtas_ldq(args, 1);
282 unsigned int func = rtas_ld(args, 3);
283 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */
284 unsigned int seq_num = rtas_ld(args, 5);
285 unsigned int ret_intr_type;
286 unsigned int irq, max_irqs = 0;
287 sPAPRPHBState *phb = NULL;
288 PCIDevice *pdev = NULL;
289 spapr_pci_msi *msi;
290 int *config_addr_key;
291 Error *err = NULL;
292
293 switch (func) {
294 case RTAS_CHANGE_MSI_FN:
295 case RTAS_CHANGE_FN:
296 ret_intr_type = RTAS_TYPE_MSI;
297 break;
298 case RTAS_CHANGE_MSIX_FN:
299 ret_intr_type = RTAS_TYPE_MSIX;
300 break;
301 default:
302 error_report("rtas_ibm_change_msi(%u) is not implemented", func);
303 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
304 return;
305 }
306
307 /* Fins sPAPRPHBState */
308 phb = spapr_pci_find_phb(spapr, buid);
309 if (phb) {
310 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
311 }
312 if (!phb || !pdev) {
313 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
314 return;
315 }
316
317 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
318
319 /* Releasing MSIs */
320 if (!req_num) {
321 if (!msi) {
322 trace_spapr_pci_msi("Releasing wrong config", config_addr);
323 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
324 return;
325 }
326
327 spapr_ics_free(spapr->ics, msi->first_irq, msi->num);
328 if (msi_present(pdev)) {
329 spapr_msi_setmsg(pdev, 0, false, 0, 0);
330 }
331 if (msix_present(pdev)) {
332 spapr_msi_setmsg(pdev, 0, true, 0, 0);
333 }
334 g_hash_table_remove(phb->msi, &config_addr);
335
336 trace_spapr_pci_msi("Released MSIs", config_addr);
337 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
338 rtas_st(rets, 1, 0);
339 return;
340 }
341
342 /* Enabling MSI */
343
344 /* Check if the device supports as many IRQs as requested */
345 if (ret_intr_type == RTAS_TYPE_MSI) {
346 max_irqs = msi_nr_vectors_allocated(pdev);
347 } else if (ret_intr_type == RTAS_TYPE_MSIX) {
348 max_irqs = pdev->msix_entries_nr;
349 }
350 if (!max_irqs) {
351 error_report("Requested interrupt type %d is not enabled for device %x",
352 ret_intr_type, config_addr);
353 rtas_st(rets, 0, -1); /* Hardware error */
354 return;
355 }
356 /* Correct the number if the guest asked for too many */
357 if (req_num > max_irqs) {
358 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs);
359 req_num = max_irqs;
360 irq = 0; /* to avoid misleading trace */
361 goto out;
362 }
363
364 /* Allocate MSIs */
365 irq = spapr_ics_alloc_block(spapr->ics, req_num, false,
366 ret_intr_type == RTAS_TYPE_MSI, &err);
367 if (err) {
368 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
369 config_addr);
370 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
371 return;
372 }
373
374 /* Release previous MSIs */
375 if (msi) {
376 spapr_ics_free(spapr->ics, msi->first_irq, msi->num);
377 g_hash_table_remove(phb->msi, &config_addr);
378 }
379
380 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
381 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
382 irq, req_num);
383
384 /* Add MSI device to cache */
385 msi = g_new(spapr_pci_msi, 1);
386 msi->first_irq = irq;
387 msi->num = req_num;
388 config_addr_key = g_new(int, 1);
389 *config_addr_key = config_addr;
390 g_hash_table_insert(phb->msi, config_addr_key, msi);
391
392 out:
393 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
394 rtas_st(rets, 1, req_num);
395 rtas_st(rets, 2, ++seq_num);
396 if (nret > 3) {
397 rtas_st(rets, 3, ret_intr_type);
398 }
399
400 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq);
401 }
402
403 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
404 sPAPRMachineState *spapr,
405 uint32_t token,
406 uint32_t nargs,
407 target_ulong args,
408 uint32_t nret,
409 target_ulong rets)
410 {
411 uint32_t config_addr = rtas_ld(args, 0);
412 uint64_t buid = rtas_ldq(args, 1);
413 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
414 sPAPRPHBState *phb = NULL;
415 PCIDevice *pdev = NULL;
416 spapr_pci_msi *msi;
417
418 /* Find sPAPRPHBState */
419 phb = spapr_pci_find_phb(spapr, buid);
420 if (phb) {
421 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
422 }
423 if (!phb || !pdev) {
424 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
425 return;
426 }
427
428 /* Find device descriptor and start IRQ */
429 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
430 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
431 trace_spapr_pci_msi("Failed to return vector", config_addr);
432 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
433 return;
434 }
435 intr_src_num = msi->first_irq + ioa_intr_num;
436 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
437 intr_src_num);
438
439 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
440 rtas_st(rets, 1, intr_src_num);
441 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
442 }
443
444 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
445 sPAPRMachineState *spapr,
446 uint32_t token, uint32_t nargs,
447 target_ulong args, uint32_t nret,
448 target_ulong rets)
449 {
450 sPAPRPHBState *sphb;
451 uint32_t addr, option;
452 uint64_t buid;
453 int ret;
454
455 if ((nargs != 4) || (nret != 1)) {
456 goto param_error_exit;
457 }
458
459 buid = rtas_ldq(args, 1);
460 addr = rtas_ld(args, 0);
461 option = rtas_ld(args, 3);
462
463 sphb = spapr_pci_find_phb(spapr, buid);
464 if (!sphb) {
465 goto param_error_exit;
466 }
467
468 if (!spapr_phb_eeh_available(sphb)) {
469 goto param_error_exit;
470 }
471
472 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option);
473 rtas_st(rets, 0, ret);
474 return;
475
476 param_error_exit:
477 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
478 }
479
480 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
481 sPAPRMachineState *spapr,
482 uint32_t token, uint32_t nargs,
483 target_ulong args, uint32_t nret,
484 target_ulong rets)
485 {
486 sPAPRPHBState *sphb;
487 PCIDevice *pdev;
488 uint32_t addr, option;
489 uint64_t buid;
490
491 if ((nargs != 4) || (nret != 2)) {
492 goto param_error_exit;
493 }
494
495 buid = rtas_ldq(args, 1);
496 sphb = spapr_pci_find_phb(spapr, buid);
497 if (!sphb) {
498 goto param_error_exit;
499 }
500
501 if (!spapr_phb_eeh_available(sphb)) {
502 goto param_error_exit;
503 }
504
505 /*
506 * We always have PE address of form "00BB0001". "BB"
507 * represents the bus number of PE's primary bus.
508 */
509 option = rtas_ld(args, 3);
510 switch (option) {
511 case RTAS_GET_PE_ADDR:
512 addr = rtas_ld(args, 0);
513 pdev = spapr_pci_find_dev(spapr, buid, addr);
514 if (!pdev) {
515 goto param_error_exit;
516 }
517
518 rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1);
519 break;
520 case RTAS_GET_PE_MODE:
521 rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
522 break;
523 default:
524 goto param_error_exit;
525 }
526
527 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
528 return;
529
530 param_error_exit:
531 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
532 }
533
534 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
535 sPAPRMachineState *spapr,
536 uint32_t token, uint32_t nargs,
537 target_ulong args, uint32_t nret,
538 target_ulong rets)
539 {
540 sPAPRPHBState *sphb;
541 uint64_t buid;
542 int state, ret;
543
544 if ((nargs != 3) || (nret != 4 && nret != 5)) {
545 goto param_error_exit;
546 }
547
548 buid = rtas_ldq(args, 1);
549 sphb = spapr_pci_find_phb(spapr, buid);
550 if (!sphb) {
551 goto param_error_exit;
552 }
553
554 if (!spapr_phb_eeh_available(sphb)) {
555 goto param_error_exit;
556 }
557
558 ret = spapr_phb_vfio_eeh_get_state(sphb, &state);
559 rtas_st(rets, 0, ret);
560 if (ret != RTAS_OUT_SUCCESS) {
561 return;
562 }
563
564 rtas_st(rets, 1, state);
565 rtas_st(rets, 2, RTAS_EEH_SUPPORT);
566 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
567 if (nret >= 5) {
568 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
569 }
570 return;
571
572 param_error_exit:
573 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
574 }
575
576 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
577 sPAPRMachineState *spapr,
578 uint32_t token, uint32_t nargs,
579 target_ulong args, uint32_t nret,
580 target_ulong rets)
581 {
582 sPAPRPHBState *sphb;
583 uint32_t option;
584 uint64_t buid;
585 int ret;
586
587 if ((nargs != 4) || (nret != 1)) {
588 goto param_error_exit;
589 }
590
591 buid = rtas_ldq(args, 1);
592 option = rtas_ld(args, 3);
593 sphb = spapr_pci_find_phb(spapr, buid);
594 if (!sphb) {
595 goto param_error_exit;
596 }
597
598 if (!spapr_phb_eeh_available(sphb)) {
599 goto param_error_exit;
600 }
601
602 ret = spapr_phb_vfio_eeh_reset(sphb, option);
603 rtas_st(rets, 0, ret);
604 return;
605
606 param_error_exit:
607 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
608 }
609
610 static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
611 sPAPRMachineState *spapr,
612 uint32_t token, uint32_t nargs,
613 target_ulong args, uint32_t nret,
614 target_ulong rets)
615 {
616 sPAPRPHBState *sphb;
617 uint64_t buid;
618 int ret;
619
620 if ((nargs != 3) || (nret != 1)) {
621 goto param_error_exit;
622 }
623
624 buid = rtas_ldq(args, 1);
625 sphb = spapr_pci_find_phb(spapr, buid);
626 if (!sphb) {
627 goto param_error_exit;
628 }
629
630 if (!spapr_phb_eeh_available(sphb)) {
631 goto param_error_exit;
632 }
633
634 ret = spapr_phb_vfio_eeh_configure(sphb);
635 rtas_st(rets, 0, ret);
636 return;
637
638 param_error_exit:
639 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
640 }
641
642 /* To support it later */
643 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
644 sPAPRMachineState *spapr,
645 uint32_t token, uint32_t nargs,
646 target_ulong args, uint32_t nret,
647 target_ulong rets)
648 {
649 sPAPRPHBState *sphb;
650 int option;
651 uint64_t buid;
652
653 if ((nargs != 8) || (nret != 1)) {
654 goto param_error_exit;
655 }
656
657 buid = rtas_ldq(args, 1);
658 sphb = spapr_pci_find_phb(spapr, buid);
659 if (!sphb) {
660 goto param_error_exit;
661 }
662
663 if (!spapr_phb_eeh_available(sphb)) {
664 goto param_error_exit;
665 }
666
667 option = rtas_ld(args, 7);
668 switch (option) {
669 case RTAS_SLOT_TEMP_ERR_LOG:
670 case RTAS_SLOT_PERM_ERR_LOG:
671 break;
672 default:
673 goto param_error_exit;
674 }
675
676 /* We don't have error log yet */
677 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
678 return;
679
680 param_error_exit:
681 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
682 }
683
684 static int pci_spapr_swizzle(int slot, int pin)
685 {
686 return (slot + pin) % PCI_NUM_PINS;
687 }
688
689 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
690 {
691 /*
692 * Here we need to convert pci_dev + irq_num to some unique value
693 * which is less than number of IRQs on the specific bus (4). We
694 * use standard PCI swizzling, that is (slot number + pin number)
695 * % 4.
696 */
697 return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
698 }
699
700 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
701 {
702 /*
703 * Here we use the number returned by pci_spapr_map_irq to find a
704 * corresponding qemu_irq.
705 */
706 sPAPRPHBState *phb = opaque;
707
708 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq);
709 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
710 }
711
712 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
713 {
714 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
715 PCIINTxRoute route;
716
717 route.mode = PCI_INTX_ENABLED;
718 route.irq = sphb->lsi_table[pin].irq;
719
720 return route;
721 }
722
723 /*
724 * MSI/MSIX memory region implementation.
725 * The handler handles both MSI and MSIX.
726 * For MSI-X, the vector number is encoded as a part of the address,
727 * data is set to 0.
728 * For MSI, the vector number is encoded in least bits in data.
729 */
730 static void spapr_msi_write(void *opaque, hwaddr addr,
731 uint64_t data, unsigned size)
732 {
733 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
734 uint32_t irq = data;
735
736 trace_spapr_pci_msi_write(addr, data, irq);
737
738 qemu_irq_pulse(xics_get_qirq(XICS_FABRIC(spapr), irq));
739 }
740
741 static const MemoryRegionOps spapr_msi_ops = {
742 /* There is no .read as the read result is undefined by PCI spec */
743 .read = NULL,
744 .write = spapr_msi_write,
745 .endianness = DEVICE_LITTLE_ENDIAN
746 };
747
748 /*
749 * PHB PCI device
750 */
751 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
752 {
753 sPAPRPHBState *phb = opaque;
754
755 return &phb->iommu_as;
756 }
757
758 static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev)
759 {
760 char *path = NULL, *buf = NULL, *host = NULL;
761
762 /* Get the PCI VFIO host id */
763 host = object_property_get_str(OBJECT(pdev), "host", NULL);
764 if (!host) {
765 goto err_out;
766 }
767
768 /* Construct the path of the file that will give us the DT location */
769 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host);
770 g_free(host);
771 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) {
772 goto err_out;
773 }
774 g_free(path);
775
776 /* Construct and read from host device tree the loc-code */
777 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf);
778 g_free(buf);
779 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) {
780 goto err_out;
781 }
782 return buf;
783
784 err_out:
785 g_free(path);
786 return NULL;
787 }
788
789 static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev)
790 {
791 char *buf;
792 const char *devtype = "qemu";
793 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
794
795 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
796 buf = spapr_phb_vfio_get_loc_code(sphb, pdev);
797 if (buf) {
798 return buf;
799 }
800 devtype = "vfio";
801 }
802 /*
803 * For emulated devices and VFIO-failure case, make up
804 * the loc-code.
805 */
806 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
807 devtype, pdev->name, sphb->index, busnr,
808 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
809 return buf;
810 }
811
812 /* Macros to operate with address in OF binding to PCI */
813 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
814 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
815 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
816 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
817 #define b_ss(x) b_x((x), 24, 2) /* the space code */
818 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
819 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
820 #define b_fff(x) b_x((x), 8, 3) /* function number */
821 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
822
823 /* for 'reg'/'assigned-addresses' OF properties */
824 #define RESOURCE_CELLS_SIZE 2
825 #define RESOURCE_CELLS_ADDRESS 3
826
827 typedef struct ResourceFields {
828 uint32_t phys_hi;
829 uint32_t phys_mid;
830 uint32_t phys_lo;
831 uint32_t size_hi;
832 uint32_t size_lo;
833 } QEMU_PACKED ResourceFields;
834
835 typedef struct ResourceProps {
836 ResourceFields reg[8];
837 ResourceFields assigned[7];
838 uint32_t reg_len;
839 uint32_t assigned_len;
840 } ResourceProps;
841
842 /* fill in the 'reg'/'assigned-resources' OF properties for
843 * a PCI device. 'reg' describes resource requirements for a
844 * device's IO/MEM regions, 'assigned-addresses' describes the
845 * actual resource assignments.
846 *
847 * the properties are arrays of ('phys-addr', 'size') pairs describing
848 * the addressable regions of the PCI device, where 'phys-addr' is a
849 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
850 * (phys.hi, phys.mid, phys.lo), and 'size' is a
851 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
852 *
853 * phys.hi = 0xYYXXXXZZ, where:
854 * 0xYY = npt000ss
855 * ||| |
856 * ||| +-- space code
857 * ||| |
858 * ||| + 00 if configuration space
859 * ||| + 01 if IO region,
860 * ||| + 10 if 32-bit MEM region
861 * ||| + 11 if 64-bit MEM region
862 * |||
863 * ||+------ for non-relocatable IO: 1 if aliased
864 * || for relocatable IO: 1 if below 64KB
865 * || for MEM: 1 if below 1MB
866 * |+------- 1 if region is prefetchable
867 * +-------- 1 if region is non-relocatable
868 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
869 * bits respectively
870 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding
871 * to the region
872 *
873 * phys.mid and phys.lo correspond respectively to the hi/lo portions
874 * of the actual address of the region.
875 *
876 * how the phys-addr/size values are used differ slightly between
877 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has
878 * an additional description for the config space region of the
879 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0
880 * to describe the region as relocatable, with an address-mapping
881 * that corresponds directly to the PHB's address space for the
882 * resource. 'assigned-addresses' always has n=1 set with an absolute
883 * address assigned for the resource. in general, 'assigned-addresses'
884 * won't be populated, since addresses for PCI devices are generally
885 * unmapped initially and left to the guest to assign.
886 *
887 * note also that addresses defined in these properties are, at least
888 * for PAPR guests, relative to the PHBs IO/MEM windows, and
889 * correspond directly to the addresses in the BARs.
890 *
891 * in accordance with PCI Bus Binding to Open Firmware,
892 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
893 * Appendix C.
894 */
895 static void populate_resource_props(PCIDevice *d, ResourceProps *rp)
896 {
897 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d))));
898 uint32_t dev_id = (b_bbbbbbbb(bus_num) |
899 b_ddddd(PCI_SLOT(d->devfn)) |
900 b_fff(PCI_FUNC(d->devfn)));
901 ResourceFields *reg, *assigned;
902 int i, reg_idx = 0, assigned_idx = 0;
903
904 /* config space region */
905 reg = &rp->reg[reg_idx++];
906 reg->phys_hi = cpu_to_be32(dev_id);
907 reg->phys_mid = 0;
908 reg->phys_lo = 0;
909 reg->size_hi = 0;
910 reg->size_lo = 0;
911
912 for (i = 0; i < PCI_NUM_REGIONS; i++) {
913 if (!d->io_regions[i].size) {
914 continue;
915 }
916
917 reg = &rp->reg[reg_idx++];
918
919 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i)));
920 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
921 reg->phys_hi |= cpu_to_be32(b_ss(1));
922 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
923 reg->phys_hi |= cpu_to_be32(b_ss(3));
924 } else {
925 reg->phys_hi |= cpu_to_be32(b_ss(2));
926 }
927 reg->phys_mid = 0;
928 reg->phys_lo = 0;
929 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32);
930 reg->size_lo = cpu_to_be32(d->io_regions[i].size);
931
932 if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) {
933 continue;
934 }
935
936 assigned = &rp->assigned[assigned_idx++];
937 assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1));
938 assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32);
939 assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr);
940 assigned->size_hi = reg->size_hi;
941 assigned->size_lo = reg->size_lo;
942 }
943
944 rp->reg_len = reg_idx * sizeof(ResourceFields);
945 rp->assigned_len = assigned_idx * sizeof(ResourceFields);
946 }
947
948 typedef struct PCIClass PCIClass;
949 typedef struct PCISubClass PCISubClass;
950 typedef struct PCIIFace PCIIFace;
951
952 struct PCIIFace {
953 int iface;
954 const char *name;
955 };
956
957 struct PCISubClass {
958 int subclass;
959 const char *name;
960 const PCIIFace *iface;
961 };
962
963 struct PCIClass {
964 const char *name;
965 const PCISubClass *subc;
966 };
967
968 static const PCISubClass undef_subclass[] = {
969 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL },
970 { 0xFF, NULL, NULL },
971 };
972
973 static const PCISubClass mass_subclass[] = {
974 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL },
975 { PCI_CLASS_STORAGE_IDE, "ide", NULL },
976 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL },
977 { PCI_CLASS_STORAGE_IPI, "ipi", NULL },
978 { PCI_CLASS_STORAGE_RAID, "raid", NULL },
979 { PCI_CLASS_STORAGE_ATA, "ata", NULL },
980 { PCI_CLASS_STORAGE_SATA, "sata", NULL },
981 { PCI_CLASS_STORAGE_SAS, "sas", NULL },
982 { 0xFF, NULL, NULL },
983 };
984
985 static const PCISubClass net_subclass[] = {
986 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL },
987 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL },
988 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL },
989 { PCI_CLASS_NETWORK_ATM, "atm", NULL },
990 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL },
991 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL },
992 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL },
993 { 0xFF, NULL, NULL },
994 };
995
996 static const PCISubClass displ_subclass[] = {
997 { PCI_CLASS_DISPLAY_VGA, "vga", NULL },
998 { PCI_CLASS_DISPLAY_XGA, "xga", NULL },
999 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL },
1000 { 0xFF, NULL, NULL },
1001 };
1002
1003 static const PCISubClass media_subclass[] = {
1004 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL },
1005 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL },
1006 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL },
1007 { 0xFF, NULL, NULL },
1008 };
1009
1010 static const PCISubClass mem_subclass[] = {
1011 { PCI_CLASS_MEMORY_RAM, "memory", NULL },
1012 { PCI_CLASS_MEMORY_FLASH, "flash", NULL },
1013 { 0xFF, NULL, NULL },
1014 };
1015
1016 static const PCISubClass bridg_subclass[] = {
1017 { PCI_CLASS_BRIDGE_HOST, "host", NULL },
1018 { PCI_CLASS_BRIDGE_ISA, "isa", NULL },
1019 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL },
1020 { PCI_CLASS_BRIDGE_MC, "mca", NULL },
1021 { PCI_CLASS_BRIDGE_PCI, "pci", NULL },
1022 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL },
1023 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL },
1024 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL },
1025 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL },
1026 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL },
1027 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL },
1028 { 0xFF, NULL, NULL },
1029 };
1030
1031 static const PCISubClass comm_subclass[] = {
1032 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL },
1033 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL },
1034 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL },
1035 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL },
1036 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL },
1037 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL },
1038 { 0xFF, NULL, NULL, },
1039 };
1040
1041 static const PCIIFace pic_iface[] = {
1042 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" },
1043 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" },
1044 { 0xFF, NULL },
1045 };
1046
1047 static const PCISubClass sys_subclass[] = {
1048 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface },
1049 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL },
1050 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL },
1051 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL },
1052 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL },
1053 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL },
1054 { 0xFF, NULL, NULL },
1055 };
1056
1057 static const PCISubClass inp_subclass[] = {
1058 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL },
1059 { PCI_CLASS_INPUT_PEN, "pen", NULL },
1060 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL },
1061 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL },
1062 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL },
1063 { 0xFF, NULL, NULL },
1064 };
1065
1066 static const PCISubClass dock_subclass[] = {
1067 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL },
1068 { 0xFF, NULL, NULL },
1069 };
1070
1071 static const PCISubClass cpu_subclass[] = {
1072 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL },
1073 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL },
1074 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL },
1075 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL },
1076 { 0xFF, NULL, NULL },
1077 };
1078
1079 static const PCIIFace usb_iface[] = {
1080 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" },
1081 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", },
1082 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" },
1083 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" },
1084 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" },
1085 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" },
1086 { 0xFF, NULL },
1087 };
1088
1089 static const PCISubClass ser_subclass[] = {
1090 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL },
1091 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL },
1092 { PCI_CLASS_SERIAL_SSA, "ssa", NULL },
1093 { PCI_CLASS_SERIAL_USB, "usb", usb_iface },
1094 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL },
1095 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL },
1096 { PCI_CLASS_SERIAL_IB, "infiniband", NULL },
1097 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL },
1098 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL },
1099 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL },
1100 { 0xFF, NULL, NULL },
1101 };
1102
1103 static const PCISubClass wrl_subclass[] = {
1104 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL },
1105 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL },
1106 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL },
1107 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL },
1108 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL },
1109 { 0xFF, NULL, NULL },
1110 };
1111
1112 static const PCISubClass sat_subclass[] = {
1113 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL },
1114 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL },
1115 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL },
1116 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL },
1117 { 0xFF, NULL, NULL },
1118 };
1119
1120 static const PCISubClass crypt_subclass[] = {
1121 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL },
1122 { PCI_CLASS_CRYPT_ENTERTAINMENT,
1123 "entertainment-encryption", NULL },
1124 { 0xFF, NULL, NULL },
1125 };
1126
1127 static const PCISubClass spc_subclass[] = {
1128 { PCI_CLASS_SP_DPIO, "dpio", NULL },
1129 { PCI_CLASS_SP_PERF, "counter", NULL },
1130 { PCI_CLASS_SP_SYNCH, "measurement", NULL },
1131 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL },
1132 { 0xFF, NULL, NULL },
1133 };
1134
1135 static const PCIClass pci_classes[] = {
1136 { "legacy-device", undef_subclass },
1137 { "mass-storage", mass_subclass },
1138 { "network", net_subclass },
1139 { "display", displ_subclass, },
1140 { "multimedia-device", media_subclass },
1141 { "memory-controller", mem_subclass },
1142 { "unknown-bridge", bridg_subclass },
1143 { "communication-controller", comm_subclass},
1144 { "system-peripheral", sys_subclass },
1145 { "input-controller", inp_subclass },
1146 { "docking-station", dock_subclass },
1147 { "cpu", cpu_subclass },
1148 { "serial-bus", ser_subclass },
1149 { "wireless-controller", wrl_subclass },
1150 { "intelligent-io", NULL },
1151 { "satellite-device", sat_subclass },
1152 { "encryption", crypt_subclass },
1153 { "data-processing-controller", spc_subclass },
1154 };
1155
1156 static const char *pci_find_device_name(uint8_t class, uint8_t subclass,
1157 uint8_t iface)
1158 {
1159 const PCIClass *pclass;
1160 const PCISubClass *psubclass;
1161 const PCIIFace *piface;
1162 const char *name;
1163
1164 if (class >= ARRAY_SIZE(pci_classes)) {
1165 return "pci";
1166 }
1167
1168 pclass = pci_classes + class;
1169 name = pclass->name;
1170
1171 if (pclass->subc == NULL) {
1172 return name;
1173 }
1174
1175 psubclass = pclass->subc;
1176 while ((psubclass->subclass & 0xff) != 0xff) {
1177 if ((psubclass->subclass & 0xff) == subclass) {
1178 name = psubclass->name;
1179 break;
1180 }
1181 psubclass++;
1182 }
1183
1184 piface = psubclass->iface;
1185 if (piface == NULL) {
1186 return name;
1187 }
1188 while ((piface->iface & 0xff) != 0xff) {
1189 if ((piface->iface & 0xff) == iface) {
1190 name = piface->name;
1191 break;
1192 }
1193 piface++;
1194 }
1195
1196 return name;
1197 }
1198
1199 static void pci_get_node_name(char *nodename, int len, PCIDevice *dev)
1200 {
1201 int slot = PCI_SLOT(dev->devfn);
1202 int func = PCI_FUNC(dev->devfn);
1203 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1204 const char *name;
1205
1206 name = pci_find_device_name((ccode >> 16) & 0xff, (ccode >> 8) & 0xff,
1207 ccode & 0xff);
1208
1209 if (func != 0) {
1210 snprintf(nodename, len, "%s@%x,%x", name, slot, func);
1211 } else {
1212 snprintf(nodename, len, "%s@%x", name, slot);
1213 }
1214 }
1215
1216 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb,
1217 PCIDevice *pdev);
1218
1219 static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset,
1220 sPAPRPHBState *sphb)
1221 {
1222 ResourceProps rp;
1223 bool is_bridge = false;
1224 int pci_status, err;
1225 char *buf = NULL;
1226 uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev);
1227 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1228 uint32_t max_msi, max_msix;
1229
1230 if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) ==
1231 PCI_HEADER_TYPE_BRIDGE) {
1232 is_bridge = true;
1233 }
1234
1235 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
1236 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id",
1237 pci_default_read_config(dev, PCI_VENDOR_ID, 2)));
1238 _FDT(fdt_setprop_cell(fdt, offset, "device-id",
1239 pci_default_read_config(dev, PCI_DEVICE_ID, 2)));
1240 _FDT(fdt_setprop_cell(fdt, offset, "revision-id",
1241 pci_default_read_config(dev, PCI_REVISION_ID, 1)));
1242 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode));
1243 if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) {
1244 _FDT(fdt_setprop_cell(fdt, offset, "interrupts",
1245 pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)));
1246 }
1247
1248 if (!is_bridge) {
1249 _FDT(fdt_setprop_cell(fdt, offset, "min-grant",
1250 pci_default_read_config(dev, PCI_MIN_GNT, 1)));
1251 _FDT(fdt_setprop_cell(fdt, offset, "max-latency",
1252 pci_default_read_config(dev, PCI_MAX_LAT, 1)));
1253 }
1254
1255 if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) {
1256 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id",
1257 pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)));
1258 }
1259
1260 if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) {
1261 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id",
1262 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)));
1263 }
1264
1265 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size",
1266 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1)));
1267
1268 /* the following fdt cells are masked off the pci status register */
1269 pci_status = pci_default_read_config(dev, PCI_STATUS, 2);
1270 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed",
1271 PCI_STATUS_DEVSEL_MASK & pci_status));
1272
1273 if (pci_status & PCI_STATUS_FAST_BACK) {
1274 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0));
1275 }
1276 if (pci_status & PCI_STATUS_66MHZ) {
1277 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0));
1278 }
1279 if (pci_status & PCI_STATUS_UDF) {
1280 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0));
1281 }
1282
1283 _FDT(fdt_setprop_string(fdt, offset, "name",
1284 pci_find_device_name((ccode >> 16) & 0xff,
1285 (ccode >> 8) & 0xff,
1286 ccode & 0xff)));
1287 buf = spapr_phb_get_loc_code(sphb, dev);
1288 if (!buf) {
1289 error_report("Failed setting the ibm,loc-code");
1290 return -1;
1291 }
1292
1293 err = fdt_setprop_string(fdt, offset, "ibm,loc-code", buf);
1294 g_free(buf);
1295 if (err < 0) {
1296 return err;
1297 }
1298
1299 if (drc_index) {
1300 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index));
1301 }
1302
1303 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells",
1304 RESOURCE_CELLS_ADDRESS));
1305 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells",
1306 RESOURCE_CELLS_SIZE));
1307
1308 max_msi = msi_nr_vectors_allocated(dev);
1309 if (max_msi) {
1310 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi));
1311 }
1312 max_msix = dev->msix_entries_nr;
1313 if (max_msix) {
1314 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix));
1315 }
1316
1317 populate_resource_props(dev, &rp);
1318 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len));
1319 _FDT(fdt_setprop(fdt, offset, "assigned-addresses",
1320 (uint8_t *)rp.assigned, rp.assigned_len));
1321
1322 if (sphb->pcie_ecs && pci_is_express(dev)) {
1323 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
1324 }
1325
1326 return 0;
1327 }
1328
1329 /* create OF node for pci device and required OF DT properties */
1330 static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev,
1331 void *fdt, int node_offset)
1332 {
1333 int offset, ret;
1334 char nodename[FDT_NAME_MAX];
1335
1336 pci_get_node_name(nodename, FDT_NAME_MAX, dev);
1337 offset = fdt_add_subnode(fdt, node_offset, nodename);
1338 ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb);
1339
1340 g_assert(!ret);
1341 if (ret) {
1342 return 0;
1343 }
1344 return offset;
1345 }
1346
1347 /* Callback to be called during DRC release. */
1348 void spapr_phb_remove_pci_device_cb(DeviceState *dev)
1349 {
1350 /* some version guests do not wait for completion of a device
1351 * cleanup (generally done asynchronously by the kernel) before
1352 * signaling to QEMU that the device is safe, but instead sleep
1353 * for some 'safe' period of time. unfortunately on a busy host
1354 * this sleep isn't guaranteed to be long enough, resulting in
1355 * bad things like IRQ lines being left asserted during final
1356 * device removal. to deal with this we call reset just prior
1357 * to finalizing the device, which will put the device back into
1358 * an 'idle' state, as the device cleanup code expects.
1359 */
1360 pci_device_reset(PCI_DEVICE(dev));
1361 object_unparent(OBJECT(dev));
1362 }
1363
1364 static sPAPRDRConnector *spapr_phb_get_pci_func_drc(sPAPRPHBState *phb,
1365 uint32_t busnr,
1366 int32_t devfn)
1367 {
1368 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI,
1369 (phb->index << 16) | (busnr << 8) | devfn);
1370 }
1371
1372 static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb,
1373 PCIDevice *pdev)
1374 {
1375 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
1376 return spapr_phb_get_pci_func_drc(phb, busnr, pdev->devfn);
1377 }
1378
1379 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb,
1380 PCIDevice *pdev)
1381 {
1382 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1383
1384 if (!drc) {
1385 return 0;
1386 }
1387
1388 return spapr_drc_index(drc);
1389 }
1390
1391 static void spapr_pci_plug(HotplugHandler *plug_handler,
1392 DeviceState *plugged_dev, Error **errp)
1393 {
1394 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1395 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1396 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1397 Error *local_err = NULL;
1398 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1399 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1400 void *fdt = NULL;
1401 int fdt_start_offset, fdt_size;
1402
1403 /* if DR is disabled we don't need to do anything in the case of
1404 * hotplug or coldplug callbacks
1405 */
1406 if (!phb->dr_enabled) {
1407 /* if this is a hotplug operation initiated by the user
1408 * we need to let them know it's not enabled
1409 */
1410 if (plugged_dev->hotplugged) {
1411 error_setg(&local_err, QERR_BUS_NO_HOTPLUG,
1412 object_get_typename(OBJECT(phb)));
1413 }
1414 goto out;
1415 }
1416
1417 g_assert(drc);
1418
1419 /* Following the QEMU convention used for PCIe multifunction
1420 * hotplug, we do not allow functions to be hotplugged to a
1421 * slot that already has function 0 present
1422 */
1423 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] &&
1424 PCI_FUNC(pdev->devfn) != 0) {
1425 error_setg(&local_err, "PCI: slot %d function 0 already ocuppied by %s,"
1426 " additional functions can no longer be exposed to guest.",
1427 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name);
1428 goto out;
1429 }
1430
1431 fdt = create_device_tree(&fdt_size);
1432 fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0);
1433 if (!fdt_start_offset) {
1434 error_setg(&local_err, "Failed to create pci child device tree node");
1435 goto out;
1436 }
1437
1438 spapr_drc_attach(drc, DEVICE(pdev), fdt, fdt_start_offset, &local_err);
1439 if (local_err) {
1440 goto out;
1441 }
1442
1443 /* If this is function 0, signal hotplug for all the device functions.
1444 * Otherwise defer sending the hotplug event.
1445 */
1446 if (!spapr_drc_hotplugged(plugged_dev)) {
1447 spapr_drc_reset(drc);
1448 } else if (PCI_FUNC(pdev->devfn) == 0) {
1449 int i;
1450
1451 for (i = 0; i < 8; i++) {
1452 sPAPRDRConnector *func_drc;
1453 sPAPRDRConnectorClass *func_drck;
1454 sPAPRDREntitySense state;
1455
1456 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1457 PCI_DEVFN(slotnr, i));
1458 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1459 state = func_drck->dr_entity_sense(func_drc);
1460
1461 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1462 spapr_hotplug_req_add_by_index(func_drc);
1463 }
1464 }
1465 }
1466
1467 out:
1468 if (local_err) {
1469 error_propagate(errp, local_err);
1470 g_free(fdt);
1471 }
1472 }
1473
1474 static void spapr_pci_unplug_request(HotplugHandler *plug_handler,
1475 DeviceState *plugged_dev, Error **errp)
1476 {
1477 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1478 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1479 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1480
1481 if (!phb->dr_enabled) {
1482 error_setg(errp, QERR_BUS_NO_HOTPLUG,
1483 object_get_typename(OBJECT(phb)));
1484 return;
1485 }
1486
1487 g_assert(drc);
1488 g_assert(drc->dev == plugged_dev);
1489
1490 if (!spapr_drc_unplug_requested(drc)) {
1491 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1492 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1493 sPAPRDRConnector *func_drc;
1494 sPAPRDRConnectorClass *func_drck;
1495 sPAPRDREntitySense state;
1496 int i;
1497
1498 /* ensure any other present functions are pending unplug */
1499 if (PCI_FUNC(pdev->devfn) == 0) {
1500 for (i = 1; i < 8; i++) {
1501 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1502 PCI_DEVFN(slotnr, i));
1503 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1504 state = func_drck->dr_entity_sense(func_drc);
1505 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT
1506 && !spapr_drc_unplug_requested(func_drc)) {
1507 error_setg(errp,
1508 "PCI: slot %d, function %d still present. "
1509 "Must unplug all non-0 functions first.",
1510 slotnr, i);
1511 return;
1512 }
1513 }
1514 }
1515
1516 spapr_drc_detach(drc);
1517
1518 /* if this isn't func 0, defer unplug event. otherwise signal removal
1519 * for all present functions
1520 */
1521 if (PCI_FUNC(pdev->devfn) == 0) {
1522 for (i = 7; i >= 0; i--) {
1523 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1524 PCI_DEVFN(slotnr, i));
1525 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1526 state = func_drck->dr_entity_sense(func_drc);
1527 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1528 spapr_hotplug_req_remove_by_index(func_drc);
1529 }
1530 }
1531 }
1532 }
1533 }
1534
1535 static void spapr_phb_realize(DeviceState *dev, Error **errp)
1536 {
1537 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1538 SysBusDevice *s = SYS_BUS_DEVICE(dev);
1539 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
1540 PCIHostState *phb = PCI_HOST_BRIDGE(s);
1541 char *namebuf;
1542 int i;
1543 PCIBus *bus;
1544 uint64_t msi_window_size = 4096;
1545 sPAPRTCETable *tcet;
1546 const unsigned windows_supported =
1547 sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1;
1548
1549 if (sphb->index != (uint32_t)-1) {
1550 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
1551 Error *local_err = NULL;
1552
1553 if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn[0] != (uint32_t)-1)
1554 || (sphb->dma_liobn[1] != (uint32_t)-1 && windows_supported == 2)
1555 || (sphb->mem_win_addr != (hwaddr)-1)
1556 || (sphb->mem64_win_addr != (hwaddr)-1)
1557 || (sphb->io_win_addr != (hwaddr)-1)) {
1558 error_setg(errp, "Either \"index\" or other parameters must"
1559 " be specified for PAPR PHB, not both");
1560 return;
1561 }
1562
1563 smc->phb_placement(spapr, sphb->index,
1564 &sphb->buid, &sphb->io_win_addr,
1565 &sphb->mem_win_addr, &sphb->mem64_win_addr,
1566 windows_supported, sphb->dma_liobn, &local_err);
1567 if (local_err) {
1568 error_propagate(errp, local_err);
1569 return;
1570 }
1571 }
1572
1573 if (sphb->buid == (uint64_t)-1) {
1574 error_setg(errp, "BUID not specified for PHB");
1575 return;
1576 }
1577
1578 if ((sphb->dma_liobn[0] == (uint32_t)-1) ||
1579 ((sphb->dma_liobn[1] == (uint32_t)-1) && (windows_supported > 1))) {
1580 error_setg(errp, "LIOBN(s) not specified for PHB");
1581 return;
1582 }
1583
1584 if (sphb->mem_win_addr == (hwaddr)-1) {
1585 error_setg(errp, "Memory window address not specified for PHB");
1586 return;
1587 }
1588
1589 if (sphb->io_win_addr == (hwaddr)-1) {
1590 error_setg(errp, "IO window address not specified for PHB");
1591 return;
1592 }
1593
1594 if (sphb->mem64_win_size != 0) {
1595 if (sphb->mem64_win_addr == (hwaddr)-1) {
1596 error_setg(errp,
1597 "64-bit memory window address not specified for PHB");
1598 return;
1599 }
1600
1601 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1602 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx
1603 " (max 2 GiB)", sphb->mem_win_size);
1604 return;
1605 }
1606
1607 if (sphb->mem64_win_pciaddr == (hwaddr)-1) {
1608 /* 64-bit window defaults to identity mapping */
1609 sphb->mem64_win_pciaddr = sphb->mem64_win_addr;
1610 }
1611 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1612 /*
1613 * For compatibility with old configuration, if no 64-bit MMIO
1614 * window is specified, but the ordinary (32-bit) memory
1615 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit
1616 * window, with a 64-bit MMIO window following on immediately
1617 * afterwards
1618 */
1619 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE;
1620 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE;
1621 sphb->mem64_win_pciaddr =
1622 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE;
1623 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE;
1624 }
1625
1626 if (spapr_pci_find_phb(spapr, sphb->buid)) {
1627 error_setg(errp, "PCI host bridges must have unique BUIDs");
1628 return;
1629 }
1630
1631 if (sphb->numa_node != -1 &&
1632 (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) {
1633 error_setg(errp, "Invalid NUMA node ID for PCI host bridge");
1634 return;
1635 }
1636
1637 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
1638
1639 namebuf = alloca(strlen(sphb->dtbusname) + 32);
1640
1641 /* Initialize memory regions */
1642 sprintf(namebuf, "%s.mmio", sphb->dtbusname);
1643 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX);
1644
1645 sprintf(namebuf, "%s.mmio32-alias", sphb->dtbusname);
1646 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb),
1647 namebuf, &sphb->memspace,
1648 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
1649 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
1650 &sphb->mem32window);
1651
1652 sprintf(namebuf, "%s.mmio64-alias", sphb->dtbusname);
1653 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb),
1654 namebuf, &sphb->memspace,
1655 sphb->mem64_win_pciaddr, sphb->mem64_win_size);
1656 memory_region_add_subregion(get_system_memory(), sphb->mem64_win_addr,
1657 &sphb->mem64window);
1658
1659 /* Initialize IO regions */
1660 sprintf(namebuf, "%s.io", sphb->dtbusname);
1661 memory_region_init(&sphb->iospace, OBJECT(sphb),
1662 namebuf, SPAPR_PCI_IO_WIN_SIZE);
1663
1664 sprintf(namebuf, "%s.io-alias", sphb->dtbusname);
1665 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
1666 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE);
1667 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
1668 &sphb->iowindow);
1669
1670 bus = pci_register_bus(dev, NULL,
1671 pci_spapr_set_irq, pci_spapr_map_irq, sphb,
1672 &sphb->memspace, &sphb->iospace,
1673 PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
1674 phb->bus = bus;
1675 qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL);
1676
1677 /*
1678 * Initialize PHB address space.
1679 * By default there will be at least one subregion for default
1680 * 32bit DMA window.
1681 * Later the guest might want to create another DMA window
1682 * which will become another memory subregion.
1683 */
1684 sprintf(namebuf, "%s.iommu-root", sphb->dtbusname);
1685
1686 memory_region_init(&sphb->iommu_root, OBJECT(sphb),
1687 namebuf, UINT64_MAX);
1688 address_space_init(&sphb->iommu_as, &sphb->iommu_root,
1689 sphb->dtbusname);
1690
1691 /*
1692 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1693 * we need to allocate some memory to catch those writes coming
1694 * from msi_notify()/msix_notify().
1695 * As MSIMessage:addr is going to be the same and MSIMessage:data
1696 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1697 * be used.
1698 *
1699 * For KVM we want to ensure that this memory is a full page so that
1700 * our memory slot is of page size granularity.
1701 */
1702 #ifdef CONFIG_KVM
1703 if (kvm_enabled()) {
1704 msi_window_size = getpagesize();
1705 }
1706 #endif
1707
1708 memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr,
1709 "msi", msi_window_size);
1710 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
1711 &sphb->msiwindow);
1712
1713 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
1714
1715 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
1716
1717 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
1718
1719 /* Initialize the LSI table */
1720 for (i = 0; i < PCI_NUM_PINS; i++) {
1721 uint32_t irq;
1722 Error *local_err = NULL;
1723
1724 irq = spapr_ics_alloc_block(spapr->ics, 1, true, false, &local_err);
1725 if (local_err) {
1726 error_propagate(errp, local_err);
1727 error_prepend(errp, "can't allocate LSIs: ");
1728 return;
1729 }
1730
1731 sphb->lsi_table[i].irq = irq;
1732 }
1733
1734 /* allocate connectors for child PCI devices */
1735 if (sphb->dr_enabled) {
1736 for (i = 0; i < PCI_SLOT_MAX * 8; i++) {
1737 spapr_dr_connector_new(OBJECT(phb), TYPE_SPAPR_DRC_PCI,
1738 (sphb->index << 16) | i);
1739 }
1740 }
1741
1742 /* DMA setup */
1743 if (((sphb->page_size_mask & qemu_getrampagesize()) == 0)
1744 && kvm_enabled()) {
1745 error_report("System page size 0x%lx is not enabled in page_size_mask "
1746 "(0x%"PRIx64"). Performance may be slow",
1747 qemu_getrampagesize(), sphb->page_size_mask);
1748 }
1749
1750 for (i = 0; i < windows_supported; ++i) {
1751 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]);
1752 if (!tcet) {
1753 error_setg(errp, "Creating window#%d failed for %s",
1754 i, sphb->dtbusname);
1755 return;
1756 }
1757 memory_region_add_subregion_overlap(&sphb->iommu_root, 0,
1758 spapr_tce_get_iommu(tcet), 0);
1759 }
1760
1761 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free);
1762 }
1763
1764 static int spapr_phb_children_reset(Object *child, void *opaque)
1765 {
1766 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
1767
1768 if (dev) {
1769 device_reset(dev);
1770 }
1771
1772 return 0;
1773 }
1774
1775 void spapr_phb_dma_reset(sPAPRPHBState *sphb)
1776 {
1777 int i;
1778 sPAPRTCETable *tcet;
1779
1780 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) {
1781 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
1782
1783 if (tcet && tcet->nb_table) {
1784 spapr_tce_table_disable(tcet);
1785 }
1786 }
1787
1788 /* Register default 32bit DMA window */
1789 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]);
1790 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr,
1791 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT);
1792 }
1793
1794 static void spapr_phb_reset(DeviceState *qdev)
1795 {
1796 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev);
1797
1798 spapr_phb_dma_reset(sphb);
1799
1800 /* Reset the IOMMU state */
1801 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
1802
1803 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) {
1804 spapr_phb_vfio_reset(qdev);
1805 }
1806 }
1807
1808 static Property spapr_phb_properties[] = {
1809 DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1),
1810 DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1),
1811 DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn[0], -1),
1812 DEFINE_PROP_UINT32("liobn64", sPAPRPHBState, dma_liobn[1], -1),
1813 DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1),
1814 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size,
1815 SPAPR_PCI_MEM32_WIN_SIZE),
1816 DEFINE_PROP_UINT64("mem64_win_addr", sPAPRPHBState, mem64_win_addr, -1),
1817 DEFINE_PROP_UINT64("mem64_win_size", sPAPRPHBState, mem64_win_size,
1818 SPAPR_PCI_MEM64_WIN_SIZE),
1819 DEFINE_PROP_UINT64("mem64_win_pciaddr", sPAPRPHBState, mem64_win_pciaddr,
1820 -1),
1821 DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1),
1822 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size,
1823 SPAPR_PCI_IO_WIN_SIZE),
1824 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled,
1825 true),
1826 /* Default DMA window is 0..1GB */
1827 DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState, dma_win_addr, 0),
1828 DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState, dma_win_size, 0x40000000),
1829 DEFINE_PROP_UINT64("dma64_win_addr", sPAPRPHBState, dma64_win_addr,
1830 0x800000000000000ULL),
1831 DEFINE_PROP_BOOL("ddw", sPAPRPHBState, ddw_enabled, true),
1832 DEFINE_PROP_UINT64("pgsz", sPAPRPHBState, page_size_mask,
1833 (1ULL << 12) | (1ULL << 16)),
1834 DEFINE_PROP_UINT32("numa_node", sPAPRPHBState, numa_node, -1),
1835 DEFINE_PROP_BOOL("pre-2.8-migration", sPAPRPHBState,
1836 pre_2_8_migration, false),
1837 DEFINE_PROP_BOOL("pcie-extended-configuration-space", sPAPRPHBState,
1838 pcie_ecs, true),
1839 DEFINE_PROP_END_OF_LIST(),
1840 };
1841
1842 static const VMStateDescription vmstate_spapr_pci_lsi = {
1843 .name = "spapr_pci/lsi",
1844 .version_id = 1,
1845 .minimum_version_id = 1,
1846 .fields = (VMStateField[]) {
1847 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi, NULL),
1848
1849 VMSTATE_END_OF_LIST()
1850 },
1851 };
1852
1853 static const VMStateDescription vmstate_spapr_pci_msi = {
1854 .name = "spapr_pci/msi",
1855 .version_id = 1,
1856 .minimum_version_id = 1,
1857 .fields = (VMStateField []) {
1858 VMSTATE_UINT32(key, spapr_pci_msi_mig),
1859 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig),
1860 VMSTATE_UINT32(value.num, spapr_pci_msi_mig),
1861 VMSTATE_END_OF_LIST()
1862 },
1863 };
1864
1865 static void spapr_pci_pre_save(void *opaque)
1866 {
1867 sPAPRPHBState *sphb = opaque;
1868 GHashTableIter iter;
1869 gpointer key, value;
1870 int i;
1871
1872 if (sphb->pre_2_8_migration) {
1873 sphb->mig_liobn = sphb->dma_liobn[0];
1874 sphb->mig_mem_win_addr = sphb->mem_win_addr;
1875 sphb->mig_mem_win_size = sphb->mem_win_size;
1876 sphb->mig_io_win_addr = sphb->io_win_addr;
1877 sphb->mig_io_win_size = sphb->io_win_size;
1878
1879 if ((sphb->mem64_win_size != 0)
1880 && (sphb->mem64_win_addr
1881 == (sphb->mem_win_addr + sphb->mem_win_size))) {
1882 sphb->mig_mem_win_size += sphb->mem64_win_size;
1883 }
1884 }
1885
1886 g_free(sphb->msi_devs);
1887 sphb->msi_devs = NULL;
1888 sphb->msi_devs_num = g_hash_table_size(sphb->msi);
1889 if (!sphb->msi_devs_num) {
1890 return;
1891 }
1892 sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig));
1893
1894 g_hash_table_iter_init(&iter, sphb->msi);
1895 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) {
1896 sphb->msi_devs[i].key = *(uint32_t *) key;
1897 sphb->msi_devs[i].value = *(spapr_pci_msi *) value;
1898 }
1899 }
1900
1901 static int spapr_pci_post_load(void *opaque, int version_id)
1902 {
1903 sPAPRPHBState *sphb = opaque;
1904 gpointer key, value;
1905 int i;
1906
1907 for (i = 0; i < sphb->msi_devs_num; ++i) {
1908 key = g_memdup(&sphb->msi_devs[i].key,
1909 sizeof(sphb->msi_devs[i].key));
1910 value = g_memdup(&sphb->msi_devs[i].value,
1911 sizeof(sphb->msi_devs[i].value));
1912 g_hash_table_insert(sphb->msi, key, value);
1913 }
1914 g_free(sphb->msi_devs);
1915 sphb->msi_devs = NULL;
1916 sphb->msi_devs_num = 0;
1917
1918 return 0;
1919 }
1920
1921 static bool pre_2_8_migration(void *opaque, int version_id)
1922 {
1923 sPAPRPHBState *sphb = opaque;
1924
1925 return sphb->pre_2_8_migration;
1926 }
1927
1928 static const VMStateDescription vmstate_spapr_pci = {
1929 .name = "spapr_pci",
1930 .version_id = 2,
1931 .minimum_version_id = 2,
1932 .pre_save = spapr_pci_pre_save,
1933 .post_load = spapr_pci_post_load,
1934 .fields = (VMStateField[]) {
1935 VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState, NULL),
1936 VMSTATE_UINT32_TEST(mig_liobn, sPAPRPHBState, pre_2_8_migration),
1937 VMSTATE_UINT64_TEST(mig_mem_win_addr, sPAPRPHBState, pre_2_8_migration),
1938 VMSTATE_UINT64_TEST(mig_mem_win_size, sPAPRPHBState, pre_2_8_migration),
1939 VMSTATE_UINT64_TEST(mig_io_win_addr, sPAPRPHBState, pre_2_8_migration),
1940 VMSTATE_UINT64_TEST(mig_io_win_size, sPAPRPHBState, pre_2_8_migration),
1941 VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0,
1942 vmstate_spapr_pci_lsi, struct spapr_pci_lsi),
1943 VMSTATE_INT32(msi_devs_num, sPAPRPHBState),
1944 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0,
1945 vmstate_spapr_pci_msi, spapr_pci_msi_mig),
1946 VMSTATE_END_OF_LIST()
1947 },
1948 };
1949
1950 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
1951 PCIBus *rootbus)
1952 {
1953 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
1954
1955 return sphb->dtbusname;
1956 }
1957
1958 static void spapr_phb_class_init(ObjectClass *klass, void *data)
1959 {
1960 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
1961 DeviceClass *dc = DEVICE_CLASS(klass);
1962 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass);
1963
1964 hc->root_bus_path = spapr_phb_root_bus_path;
1965 dc->realize = spapr_phb_realize;
1966 dc->props = spapr_phb_properties;
1967 dc->reset = spapr_phb_reset;
1968 dc->vmsd = &vmstate_spapr_pci;
1969 /* Supported by TYPE_SPAPR_MACHINE */
1970 dc->user_creatable = true;
1971 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1972 hp->plug = spapr_pci_plug;
1973 hp->unplug_request = spapr_pci_unplug_request;
1974 }
1975
1976 static const TypeInfo spapr_phb_info = {
1977 .name = TYPE_SPAPR_PCI_HOST_BRIDGE,
1978 .parent = TYPE_PCI_HOST_BRIDGE,
1979 .instance_size = sizeof(sPAPRPHBState),
1980 .class_init = spapr_phb_class_init,
1981 .interfaces = (InterfaceInfo[]) {
1982 { TYPE_HOTPLUG_HANDLER },
1983 { }
1984 }
1985 };
1986
1987 PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index)
1988 {
1989 DeviceState *dev;
1990
1991 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
1992 qdev_prop_set_uint32(dev, "index", index);
1993 qdev_init_nofail(dev);
1994
1995 return PCI_HOST_BRIDGE(dev);
1996 }
1997
1998 typedef struct sPAPRFDT {
1999 void *fdt;
2000 int node_off;
2001 sPAPRPHBState *sphb;
2002 } sPAPRFDT;
2003
2004 static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev,
2005 void *opaque)
2006 {
2007 PCIBus *sec_bus;
2008 sPAPRFDT *p = opaque;
2009 int offset;
2010 sPAPRFDT s_fdt;
2011
2012 offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off);
2013 if (!offset) {
2014 error_report("Failed to create pci child device tree node");
2015 return;
2016 }
2017
2018 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2019 PCI_HEADER_TYPE_BRIDGE)) {
2020 return;
2021 }
2022
2023 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2024 if (!sec_bus) {
2025 return;
2026 }
2027
2028 s_fdt.fdt = p->fdt;
2029 s_fdt.node_off = offset;
2030 s_fdt.sphb = p->sphb;
2031 pci_for_each_device_reverse(sec_bus, pci_bus_num(sec_bus),
2032 spapr_populate_pci_devices_dt,
2033 &s_fdt);
2034 }
2035
2036 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev,
2037 void *opaque)
2038 {
2039 unsigned int *bus_no = opaque;
2040 unsigned int primary = *bus_no;
2041 unsigned int subordinate = 0xff;
2042 PCIBus *sec_bus = NULL;
2043
2044 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2045 PCI_HEADER_TYPE_BRIDGE)) {
2046 return;
2047 }
2048
2049 (*bus_no)++;
2050 pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1);
2051 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1);
2052 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2053
2054 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2055 if (!sec_bus) {
2056 return;
2057 }
2058
2059 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1);
2060 pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
2061 spapr_phb_pci_enumerate_bridge, bus_no);
2062 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2063 }
2064
2065 static void spapr_phb_pci_enumerate(sPAPRPHBState *phb)
2066 {
2067 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2068 unsigned int bus_no = 0;
2069
2070 pci_for_each_device(bus, pci_bus_num(bus),
2071 spapr_phb_pci_enumerate_bridge,
2072 &bus_no);
2073
2074 }
2075
2076 int spapr_populate_pci_dt(sPAPRPHBState *phb,
2077 uint32_t xics_phandle,
2078 void *fdt)
2079 {
2080 int bus_off, i, j, ret;
2081 char nodename[FDT_NAME_MAX];
2082 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2083 struct {
2084 uint32_t hi;
2085 uint64_t child;
2086 uint64_t parent;
2087 uint64_t size;
2088 } QEMU_PACKED ranges[] = {
2089 {
2090 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2091 cpu_to_be64(phb->io_win_addr),
2092 cpu_to_be64(memory_region_size(&phb->iospace)),
2093 },
2094 {
2095 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
2096 cpu_to_be64(phb->mem_win_addr),
2097 cpu_to_be64(phb->mem_win_size),
2098 },
2099 {
2100 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr),
2101 cpu_to_be64(phb->mem64_win_addr),
2102 cpu_to_be64(phb->mem64_win_size),
2103 },
2104 };
2105 const unsigned sizeof_ranges =
2106 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]);
2107 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
2108 uint32_t interrupt_map_mask[] = {
2109 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2110 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
2111 uint32_t ddw_applicable[] = {
2112 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW),
2113 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW),
2114 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW)
2115 };
2116 uint32_t ddw_extensions[] = {
2117 cpu_to_be32(1),
2118 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW)
2119 };
2120 uint32_t associativity[] = {cpu_to_be32(0x4),
2121 cpu_to_be32(0x0),
2122 cpu_to_be32(0x0),
2123 cpu_to_be32(0x0),
2124 cpu_to_be32(phb->numa_node)};
2125 sPAPRTCETable *tcet;
2126 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2127 sPAPRFDT s_fdt;
2128
2129 /* Start populating the FDT */
2130 snprintf(nodename, FDT_NAME_MAX, "pci@%" PRIx64, phb->buid);
2131 bus_off = fdt_add_subnode(fdt, 0, nodename);
2132 if (bus_off < 0) {
2133 return bus_off;
2134 }
2135
2136 /* Write PHB properties */
2137 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
2138 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
2139 _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
2140 _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
2141 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
2142 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
2143 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
2144 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
2145 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
2146 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
2147 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS_SPAPR));
2148
2149 /* Dynamic DMA window */
2150 if (phb->ddw_enabled) {
2151 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable,
2152 sizeof(ddw_applicable)));
2153 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions",
2154 &ddw_extensions, sizeof(ddw_extensions)));
2155 }
2156
2157 /* Advertise NUMA via ibm,associativity */
2158 if (phb->numa_node != -1) {
2159 _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity,
2160 sizeof(associativity)));
2161 }
2162
2163 /* Build the interrupt-map, this must matches what is done
2164 * in pci_spapr_map_irq
2165 */
2166 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
2167 &interrupt_map_mask, sizeof(interrupt_map_mask)));
2168 for (i = 0; i < PCI_SLOT_MAX; i++) {
2169 for (j = 0; j < PCI_NUM_PINS; j++) {
2170 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
2171 int lsi_num = pci_spapr_swizzle(i, j);
2172
2173 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
2174 irqmap[1] = 0;
2175 irqmap[2] = 0;
2176 irqmap[3] = cpu_to_be32(j+1);
2177 irqmap[4] = cpu_to_be32(xics_phandle);
2178 irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq);
2179 irqmap[6] = cpu_to_be32(0x8);
2180 }
2181 }
2182 /* Write interrupt map */
2183 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
2184 sizeof(interrupt_map)));
2185
2186 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]);
2187 if (!tcet) {
2188 return -1;
2189 }
2190 spapr_dma_dt(fdt, bus_off, "ibm,dma-window",
2191 tcet->liobn, tcet->bus_offset,
2192 tcet->nb_table << tcet->page_shift);
2193
2194 /* Walk the bridges and program the bus numbers*/
2195 spapr_phb_pci_enumerate(phb);
2196 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1));
2197
2198 /* Populate tree nodes with PCI devices attached */
2199 s_fdt.fdt = fdt;
2200 s_fdt.node_off = bus_off;
2201 s_fdt.sphb = phb;
2202 pci_for_each_device_reverse(bus, pci_bus_num(bus),
2203 spapr_populate_pci_devices_dt,
2204 &s_fdt);
2205
2206 ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb),
2207 SPAPR_DR_CONNECTOR_TYPE_PCI);
2208 if (ret) {
2209 return ret;
2210 }
2211
2212 return 0;
2213 }
2214
2215 void spapr_pci_rtas_init(void)
2216 {
2217 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config",
2218 rtas_read_pci_config);
2219 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config",
2220 rtas_write_pci_config);
2221 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config",
2222 rtas_ibm_read_pci_config);
2223 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config",
2224 rtas_ibm_write_pci_config);
2225 if (msi_nonbroken) {
2226 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER,
2227 "ibm,query-interrupt-source-number",
2228 rtas_ibm_query_interrupt_source_number);
2229 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
2230 rtas_ibm_change_msi);
2231 }
2232
2233 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
2234 "ibm,set-eeh-option",
2235 rtas_ibm_set_eeh_option);
2236 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
2237 "ibm,get-config-addr-info2",
2238 rtas_ibm_get_config_addr_info2);
2239 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
2240 "ibm,read-slot-reset-state2",
2241 rtas_ibm_read_slot_reset_state2);
2242 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
2243 "ibm,set-slot-reset",
2244 rtas_ibm_set_slot_reset);
2245 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
2246 "ibm,configure-pe",
2247 rtas_ibm_configure_pe);
2248 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
2249 "ibm,slot-error-detail",
2250 rtas_ibm_slot_error_detail);
2251 }
2252
2253 static void spapr_pci_register_types(void)
2254 {
2255 type_register_static(&spapr_phb_info);
2256 }
2257
2258 type_init(spapr_pci_register_types)
2259
2260 static int spapr_switch_one_vga(DeviceState *dev, void *opaque)
2261 {
2262 bool be = *(bool *)opaque;
2263
2264 if (object_dynamic_cast(OBJECT(dev), "VGA")
2265 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) {
2266 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer",
2267 &error_abort);
2268 }
2269 return 0;
2270 }
2271
2272 void spapr_pci_switch_vga(bool big_endian)
2273 {
2274 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
2275 sPAPRPHBState *sphb;
2276
2277 /*
2278 * For backward compatibility with existing guests, we switch
2279 * the endianness of the VGA controller when changing the guest
2280 * interrupt mode
2281 */
2282 QLIST_FOREACH(sphb, &spapr->phbs, list) {
2283 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus;
2284 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL,
2285 &big_endian);
2286 }
2287 }
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