hw/ppc/spapr_pci.c

   1 /*
   2  * QEMU sPAPR PCI host originated from Uninorth PCI host
   3  *
   4  * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
   5  * Copyright (C) 2011 David Gibson, IBM Corporation.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw/hw.h"
  26 #include "hw/pci/pci.h"
  27 #include "hw/pci/msi.h"
  28 #include "hw/pci/msix.h"
  29 #include "hw/pci/pci_host.h"
  30 #include "hw/ppc/spapr.h"
  31 #include "hw/pci-host/spapr.h"
  32 #include "exec/address-spaces.h"
  33 #include <libfdt.h>
  34 #include "trace.h"
  35 #include "qemu/error-report.h"
  36
  37 #include "hw/pci/pci_bus.h"
  38
  39 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
  40 #define RTAS_QUERY_FN           0
  41 #define RTAS_CHANGE_FN          1
  42 #define RTAS_RESET_FN           2
  43 #define RTAS_CHANGE_MSI_FN      3
  44 #define RTAS_CHANGE_MSIX_FN     4
  45
  46 /* Interrupt types to return on RTAS_CHANGE_* */
  47 #define RTAS_TYPE_MSI           1
  48 #define RTAS_TYPE_MSIX          2
  49
  50 static sPAPRPHBState *find_phb(sPAPREnvironment *spapr, uint64_t buid)
  51 {
  52     sPAPRPHBState *sphb;
  53
  54     QLIST_FOREACH(sphb, &spapr->phbs, list) {
  55         if (sphb->buid != buid) {
  56             continue;
  57         }
  58         return sphb;
  59     }
  60
  61     return NULL;
  62 }
  63
  64 static PCIDevice *find_dev(sPAPREnvironment *spapr, uint64_t buid,
  65                            uint32_t config_addr)
  66 {
  67     sPAPRPHBState *sphb = find_phb(spapr, buid);
  68     PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
  69     int bus_num = (config_addr >> 16) & 0xFF;
  70     int devfn = (config_addr >> 8) & 0xFF;
  71
  72     if (!phb) {
  73         return NULL;
  74     }
  75
  76     return pci_find_device(phb->bus, bus_num, devfn);
  77 }
  78
  79 static uint32_t rtas_pci_cfgaddr(uint32_t arg)
  80 {
  81     /* This handles the encoding of extended config space addresses */
  82     return ((arg >> 20) & 0xf00) | (arg & 0xff);
  83 }
  84
  85 static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid,
  86                                    uint32_t addr, uint32_t size,
  87                                    target_ulong rets)
  88 {
  89     PCIDevice *pci_dev;
  90     uint32_t val;
  91
  92     if ((size != 1) && (size != 2) && (size != 4)) {
  93         /* access must be 1, 2 or 4 bytes */
  94         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
  95         return;
  96     }
  97
  98     pci_dev = find_dev(spapr, buid, addr);
  99     addr = rtas_pci_cfgaddr(addr);
 100
 101     if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
 102         /* Access must be to a valid device, within bounds and
 103          * naturally aligned */
 104         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 105         return;
 106     }
 107
 108     val = pci_host_config_read_common(pci_dev, addr,
 109                                       pci_config_size(pci_dev), size);
 110
 111     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 112     rtas_st(rets, 1, val);
 113 }
 114
 115 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 116                                      uint32_t token, uint32_t nargs,
 117                                      target_ulong args,
 118                                      uint32_t nret, target_ulong rets)
 119 {
 120     uint64_t buid;
 121     uint32_t size, addr;
 122
 123     if ((nargs != 4) || (nret != 2)) {
 124         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 125         return;
 126     }
 127
 128     buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
 129     size = rtas_ld(args, 3);
 130     addr = rtas_ld(args, 0);
 131
 132     finish_read_pci_config(spapr, buid, addr, size, rets);
 133 }
 134
 135 static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 136                                  uint32_t token, uint32_t nargs,
 137                                  target_ulong args,
 138                                  uint32_t nret, target_ulong rets)
 139 {
 140     uint32_t size, addr;
 141
 142     if ((nargs != 2) || (nret != 2)) {
 143         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 144         return;
 145     }
 146
 147     size = rtas_ld(args, 1);
 148     addr = rtas_ld(args, 0);
 149
 150     finish_read_pci_config(spapr, 0, addr, size, rets);
 151 }
 152
 153 static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid,
 154                                     uint32_t addr, uint32_t size,
 155                                     uint32_t val, target_ulong rets)
 156 {
 157     PCIDevice *pci_dev;
 158
 159     if ((size != 1) && (size != 2) && (size != 4)) {
 160         /* access must be 1, 2 or 4 bytes */
 161         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 162         return;
 163     }
 164
 165     pci_dev = find_dev(spapr, buid, addr);
 166     addr = rtas_pci_cfgaddr(addr);
 167
 168     if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
 169         /* Access must be to a valid device, within bounds and
 170          * naturally aligned */
 171         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 172         return;
 173     }
 174
 175     pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
 176                                  val, size);
 177
 178     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 179 }
 180
 181 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 182                                       uint32_t token, uint32_t nargs,
 183                                       target_ulong args,
 184                                       uint32_t nret, target_ulong rets)
 185 {
 186     uint64_t buid;
 187     uint32_t val, size, addr;
 188
 189     if ((nargs != 5) || (nret != 1)) {
 190         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 191         return;
 192     }
 193
 194     buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
 195     val = rtas_ld(args, 4);
 196     size = rtas_ld(args, 3);
 197     addr = rtas_ld(args, 0);
 198
 199     finish_write_pci_config(spapr, buid, addr, size, val, rets);
 200 }
 201
 202 static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 203                                   uint32_t token, uint32_t nargs,
 204                                   target_ulong args,
 205                                   uint32_t nret, target_ulong rets)
 206 {
 207     uint32_t val, size, addr;
 208
 209     if ((nargs != 3) || (nret != 1)) {
 210         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 211         return;
 212     }
 213
 214
 215     val = rtas_ld(args, 2);
 216     size = rtas_ld(args, 1);
 217     addr = rtas_ld(args, 0);
 218
 219     finish_write_pci_config(spapr, 0, addr, size, val, rets);
 220 }
 221
 222 /*
 223  * Set MSI/MSIX message data.
 224  * This is required for msi_notify()/msix_notify() which
 225  * will write at the addresses via spapr_msi_write().
 226  *
 227  * If hwaddr == 0, all entries will have .data == first_irq i.e.
 228  * table will be reset.
 229  */
 230 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix,
 231                              unsigned first_irq, unsigned req_num)
 232 {
 233     unsigned i;
 234     MSIMessage msg = { .address = addr, .data = first_irq };
 235
 236     if (!msix) {
 237         msi_set_message(pdev, msg);
 238         trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
 239         return;
 240     }
 241
 242     for (i = 0; i < req_num; ++i) {
 243         msix_set_message(pdev, i, msg);
 244         trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
 245         if (addr) {
 246             ++msg.data;
 247         }
 248     }
 249 }
 250
 251 static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 252                                 uint32_t token, uint32_t nargs,
 253                                 target_ulong args, uint32_t nret,
 254                                 target_ulong rets)
 255 {
 256     uint32_t config_addr = rtas_ld(args, 0);
 257     uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
 258     unsigned int func = rtas_ld(args, 3);
 259     unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */
 260     unsigned int seq_num = rtas_ld(args, 5);
 261     unsigned int ret_intr_type;
 262     unsigned int irq, max_irqs = 0, num = 0;
 263     sPAPRPHBState *phb = NULL;
 264     PCIDevice *pdev = NULL;
 265     spapr_pci_msi *msi;
 266     int *config_addr_key;
 267
 268     switch (func) {
 269     case RTAS_CHANGE_MSI_FN:
 270     case RTAS_CHANGE_FN:
 271         ret_intr_type = RTAS_TYPE_MSI;
 272         break;
 273     case RTAS_CHANGE_MSIX_FN:
 274         ret_intr_type = RTAS_TYPE_MSIX;
 275         break;
 276     default:
 277         error_report("rtas_ibm_change_msi(%u) is not implemented", func);
 278         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 279         return;
 280     }
 281
 282     /* Fins sPAPRPHBState */
 283     phb = find_phb(spapr, buid);
 284     if (phb) {
 285         pdev = find_dev(spapr, buid, config_addr);
 286     }
 287     if (!phb || !pdev) {
 288         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 289         return;
 290     }
 291
 292     /* Releasing MSIs */
 293     if (!req_num) {
 294         msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
 295         if (!msi) {
 296             trace_spapr_pci_msi("Releasing wrong config", config_addr);
 297             rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 298             return;
 299         }
 300
 301         xics_free(spapr->icp, msi->first_irq, msi->num);
 302         if (msi_present(pdev)) {
 303             spapr_msi_setmsg(pdev, 0, false, 0, num);
 304         }
 305         if (msix_present(pdev)) {
 306             spapr_msi_setmsg(pdev, 0, true, 0, num);
 307         }
 308         g_hash_table_remove(phb->msi, &config_addr);
 309
 310         trace_spapr_pci_msi("Released MSIs", config_addr);
 311         rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 312         rtas_st(rets, 1, 0);
 313         return;
 314     }
 315
 316     /* Enabling MSI */
 317
 318     /* Check if the device supports as many IRQs as requested */
 319     if (ret_intr_type == RTAS_TYPE_MSI) {
 320         max_irqs = msi_nr_vectors_allocated(pdev);
 321     } else if (ret_intr_type == RTAS_TYPE_MSIX) {
 322         max_irqs = pdev->msix_entries_nr;
 323     }
 324     if (!max_irqs) {
 325         error_report("Requested interrupt type %d is not enabled for device %x",
 326                      ret_intr_type, config_addr);
 327         rtas_st(rets, 0, -1); /* Hardware error */
 328         return;
 329     }
 330     /* Correct the number if the guest asked for too many */
 331     if (req_num > max_irqs) {
 332         trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs);
 333         req_num = max_irqs;
 334         irq = 0; /* to avoid misleading trace */
 335         goto out;
 336     }
 337
 338     /* Allocate MSIs */
 339     irq = xics_alloc_block(spapr->icp, 0, req_num, false,
 340                            ret_intr_type == RTAS_TYPE_MSI);
 341     if (!irq) {
 342         error_report("Cannot allocate MSIs for device %x", config_addr);
 343         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 344         return;
 345     }
 346
 347     /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
 348     spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
 349                      irq, req_num);
 350
 351     /* Add MSI device to cache */
 352     msi = g_new(spapr_pci_msi, 1);
 353     msi->first_irq = irq;
 354     msi->num = req_num;
 355     config_addr_key = g_new(int, 1);
 356     *config_addr_key = config_addr;
 357     g_hash_table_insert(phb->msi, config_addr_key, msi);
 358
 359 out:
 360     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 361     rtas_st(rets, 1, req_num);
 362     rtas_st(rets, 2, ++seq_num);
 363     rtas_st(rets, 3, ret_intr_type);
 364
 365     trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq);
 366 }
 367
 368 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
 369                                                    sPAPREnvironment *spapr,
 370                                                    uint32_t token,
 371                                                    uint32_t nargs,
 372                                                    target_ulong args,
 373                                                    uint32_t nret,
 374                                                    target_ulong rets)
 375 {
 376     uint32_t config_addr = rtas_ld(args, 0);
 377     uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
 378     unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
 379     sPAPRPHBState *phb = NULL;
 380     PCIDevice *pdev = NULL;
 381     spapr_pci_msi *msi;
 382
 383     /* Find sPAPRPHBState */
 384     phb = find_phb(spapr, buid);
 385     if (phb) {
 386         pdev = find_dev(spapr, buid, config_addr);
 387     }
 388     if (!phb || !pdev) {
 389         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 390         return;
 391     }
 392
 393     /* Find device descriptor and start IRQ */
 394     msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
 395     if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
 396         trace_spapr_pci_msi("Failed to return vector", config_addr);
 397         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 398         return;
 399     }
 400     intr_src_num = msi->first_irq + ioa_intr_num;
 401     trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
 402                                                            intr_src_num);
 403
 404     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 405     rtas_st(rets, 1, intr_src_num);
 406     rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
 407 }
 408
 409 static int pci_spapr_swizzle(int slot, int pin)
 410 {
 411     return (slot + pin) % PCI_NUM_PINS;
 412 }
 413
 414 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
 415 {
 416     /*
 417      * Here we need to convert pci_dev + irq_num to some unique value
 418      * which is less than number of IRQs on the specific bus (4).  We
 419      * use standard PCI swizzling, that is (slot number + pin number)
 420      * % 4.
 421      */
 422     return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
 423 }
 424
 425 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
 426 {
 427     /*
 428      * Here we use the number returned by pci_spapr_map_irq to find a
 429      * corresponding qemu_irq.
 430      */
 431     sPAPRPHBState *phb = opaque;
 432
 433     trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq);
 434     qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
 435 }
 436
 437 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
 438 {
 439     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
 440     PCIINTxRoute route;
 441
 442     route.mode = PCI_INTX_ENABLED;
 443     route.irq = sphb->lsi_table[pin].irq;
 444
 445     return route;
 446 }
 447
 448 /*
 449  * MSI/MSIX memory region implementation.
 450  * The handler handles both MSI and MSIX.
 451  * For MSI-X, the vector number is encoded as a part of the address,
 452  * data is set to 0.
 453  * For MSI, the vector number is encoded in least bits in data.
 454  */
 455 static void spapr_msi_write(void *opaque, hwaddr addr,
 456                             uint64_t data, unsigned size)
 457 {
 458     uint32_t irq = data;
 459
 460     trace_spapr_pci_msi_write(addr, data, irq);
 461
 462     qemu_irq_pulse(xics_get_qirq(spapr->icp, irq));
 463 }
 464
 465 static const MemoryRegionOps spapr_msi_ops = {
 466     /* There is no .read as the read result is undefined by PCI spec */
 467     .read = NULL,
 468     .write = spapr_msi_write,
 469     .endianness = DEVICE_LITTLE_ENDIAN
 470 };
 471
 472 /*
 473  * PHB PCI device
 474  */
 475 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
 476 {
 477     sPAPRPHBState *phb = opaque;
 478
 479     return &phb->iommu_as;
 480 }
 481
 482 static void spapr_phb_realize(DeviceState *dev, Error **errp)
 483 {
 484     SysBusDevice *s = SYS_BUS_DEVICE(dev);
 485     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
 486     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 487     sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s);
 488     char *namebuf;
 489     int i;
 490     PCIBus *bus;
 491     uint64_t msi_window_size = 4096;
 492
 493     if (sphb->index != -1) {
 494         hwaddr windows_base;
 495
 496         if ((sphb->buid != -1) || (sphb->dma_liobn != -1)
 497             || (sphb->mem_win_addr != -1)
 498             || (sphb->io_win_addr != -1)) {
 499             error_setg(errp, "Either \"index\" or other parameters must"
 500                        " be specified for PAPR PHB, not both");
 501             return;
 502         }
 503
 504         if (sphb->index > SPAPR_PCI_MAX_INDEX) {
 505             error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
 506                        SPAPR_PCI_MAX_INDEX);
 507             return;
 508         }
 509
 510         sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index;
 511         sphb->dma_liobn = SPAPR_PCI_BASE_LIOBN + sphb->index;
 512
 513         windows_base = SPAPR_PCI_WINDOW_BASE
 514             + sphb->index * SPAPR_PCI_WINDOW_SPACING;
 515         sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF;
 516         sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF;
 517     }
 518
 519     if (sphb->buid == -1) {
 520         error_setg(errp, "BUID not specified for PHB");
 521         return;
 522     }
 523
 524     if (sphb->dma_liobn == -1) {
 525         error_setg(errp, "LIOBN not specified for PHB");
 526         return;
 527     }
 528
 529     if (sphb->mem_win_addr == -1) {
 530         error_setg(errp, "Memory window address not specified for PHB");
 531         return;
 532     }
 533
 534     if (sphb->io_win_addr == -1) {
 535         error_setg(errp, "IO window address not specified for PHB");
 536         return;
 537     }
 538
 539     if (find_phb(spapr, sphb->buid)) {
 540         error_setg(errp, "PCI host bridges must have unique BUIDs");
 541         return;
 542     }
 543
 544     sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
 545
 546     namebuf = alloca(strlen(sphb->dtbusname) + 32);
 547
 548     /* Initialize memory regions */
 549     sprintf(namebuf, "%s.mmio", sphb->dtbusname);
 550     memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX);
 551
 552     sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname);
 553     memory_region_init_alias(&sphb->memwindow, OBJECT(sphb),
 554                              namebuf, &sphb->memspace,
 555                              SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
 556     memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
 557                                 &sphb->memwindow);
 558
 559     /* Initialize IO regions */
 560     sprintf(namebuf, "%s.io", sphb->dtbusname);
 561     memory_region_init(&sphb->iospace, OBJECT(sphb),
 562                        namebuf, SPAPR_PCI_IO_WIN_SIZE);
 563
 564     sprintf(namebuf, "%s.io-alias", sphb->dtbusname);
 565     memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
 566                              &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE);
 567     memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
 568                                 &sphb->iowindow);
 569
 570     bus = pci_register_bus(dev, NULL,
 571                            pci_spapr_set_irq, pci_spapr_map_irq, sphb,
 572                            &sphb->memspace, &sphb->iospace,
 573                            PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
 574     phb->bus = bus;
 575
 576     /*
 577      * Initialize PHB address space.
 578      * By default there will be at least one subregion for default
 579      * 32bit DMA window.
 580      * Later the guest might want to create another DMA window
 581      * which will become another memory subregion.
 582      */
 583     sprintf(namebuf, "%s.iommu-root", sphb->dtbusname);
 584
 585     memory_region_init(&sphb->iommu_root, OBJECT(sphb),
 586                        namebuf, UINT64_MAX);
 587     address_space_init(&sphb->iommu_as, &sphb->iommu_root,
 588                        sphb->dtbusname);
 589
 590     /*
 591      * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
 592      * we need to allocate some memory to catch those writes coming
 593      * from msi_notify()/msix_notify().
 594      * As MSIMessage:addr is going to be the same and MSIMessage:data
 595      * is going to be a VIRQ number, 4 bytes of the MSI MR will only
 596      * be used.
 597      *
 598      * For KVM we want to ensure that this memory is a full page so that
 599      * our memory slot is of page size granularity.
 600      */
 601 #ifdef CONFIG_KVM
 602     if (kvm_enabled()) {
 603         msi_window_size = getpagesize();
 604     }
 605 #endif
 606
 607     memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr,
 608                           "msi", msi_window_size);
 609     memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
 610                                 &sphb->msiwindow);
 611
 612     pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
 613
 614     pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
 615
 616     QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
 617
 618     /* Initialize the LSI table */
 619     for (i = 0; i < PCI_NUM_PINS; i++) {
 620         uint32_t irq;
 621
 622         irq = xics_alloc_block(spapr->icp, 0, 1, true, false);
 623         if (!irq) {
 624             error_setg(errp, "spapr_allocate_lsi failed");
 625             return;
 626         }
 627
 628         sphb->lsi_table[i].irq = irq;
 629     }
 630
 631     if (!info->finish_realize) {
 632         error_setg(errp, "finish_realize not defined");
 633         return;
 634     }
 635
 636     info->finish_realize(sphb, errp);
 637
 638     sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free);
 639 }
 640
 641 static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp)
 642 {
 643     sPAPRTCETable *tcet;
 644
 645     tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn,
 646                                0,
 647                                SPAPR_TCE_PAGE_SHIFT,
 648                                0x40000000 >> SPAPR_TCE_PAGE_SHIFT, false);
 649     if (!tcet) {
 650         error_setg(errp, "Unable to create TCE table for %s",
 651                    sphb->dtbusname);
 652         return ;
 653     }
 654
 655     /* Register default 32bit DMA window */
 656     memory_region_add_subregion(&sphb->iommu_root, 0,
 657                                 spapr_tce_get_iommu(tcet));
 658 }
 659
 660 static int spapr_phb_children_reset(Object *child, void *opaque)
 661 {
 662     DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
 663
 664     if (dev) {
 665         device_reset(dev);
 666     }
 667
 668     return 0;
 669 }
 670
 671 static void spapr_phb_reset(DeviceState *qdev)
 672 {
 673     /* Reset the IOMMU state */
 674     object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
 675 }
 676
 677 static Property spapr_phb_properties[] = {
 678     DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1),
 679     DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1),
 680     DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn, -1),
 681     DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1),
 682     DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size,
 683                        SPAPR_PCI_MMIO_WIN_SIZE),
 684     DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1),
 685     DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size,
 686                        SPAPR_PCI_IO_WIN_SIZE),
 687     DEFINE_PROP_END_OF_LIST(),
 688 };
 689
 690 static const VMStateDescription vmstate_spapr_pci_lsi = {
 691     .name = "spapr_pci/lsi",
 692     .version_id = 1,
 693     .minimum_version_id = 1,
 694     .fields = (VMStateField[]) {
 695         VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi),
 696
 697         VMSTATE_END_OF_LIST()
 698     },
 699 };
 700
 701 static const VMStateDescription vmstate_spapr_pci_msi = {
 702     .name = "spapr_pci/msi",
 703     .version_id = 1,
 704     .minimum_version_id = 1,
 705     .fields = (VMStateField []) {
 706         VMSTATE_UINT32(key, spapr_pci_msi_mig),
 707         VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig),
 708         VMSTATE_UINT32(value.num, spapr_pci_msi_mig),
 709         VMSTATE_END_OF_LIST()
 710     },
 711 };
 712
 713 static void spapr_pci_fill_msi_devs(gpointer key, gpointer value,
 714                                     gpointer opaque)
 715 {
 716     sPAPRPHBState *sphb = opaque;
 717
 718     sphb->msi_devs[sphb->msi_devs_num].key = *(uint32_t *)key;
 719     sphb->msi_devs[sphb->msi_devs_num].value = *(spapr_pci_msi *)value;
 720     sphb->msi_devs_num++;
 721 }
 722
 723 static void spapr_pci_pre_save(void *opaque)
 724 {
 725     sPAPRPHBState *sphb = opaque;
 726     int msi_devs_num;
 727
 728     if (sphb->msi_devs) {
 729         g_free(sphb->msi_devs);
 730         sphb->msi_devs = NULL;
 731     }
 732     sphb->msi_devs_num = 0;
 733     msi_devs_num = g_hash_table_size(sphb->msi);
 734     if (!msi_devs_num) {
 735         return;
 736     }
 737     sphb->msi_devs = g_malloc(msi_devs_num * sizeof(spapr_pci_msi_mig));
 738
 739     g_hash_table_foreach(sphb->msi, spapr_pci_fill_msi_devs, sphb);
 740     assert(sphb->msi_devs_num == msi_devs_num);
 741 }
 742
 743 static int spapr_pci_post_load(void *opaque, int version_id)
 744 {
 745     sPAPRPHBState *sphb = opaque;
 746     gpointer key, value;
 747     int i;
 748
 749     for (i = 0; i < sphb->msi_devs_num; ++i) {
 750         key = g_memdup(&sphb->msi_devs[i].key,
 751                        sizeof(sphb->msi_devs[i].key));
 752         value = g_memdup(&sphb->msi_devs[i].value,
 753                          sizeof(sphb->msi_devs[i].value));
 754         g_hash_table_insert(sphb->msi, key, value);
 755     }
 756     if (sphb->msi_devs) {
 757         g_free(sphb->msi_devs);
 758         sphb->msi_devs = NULL;
 759     }
 760     sphb->msi_devs_num = 0;
 761
 762     return 0;
 763 }
 764
 765 static const VMStateDescription vmstate_spapr_pci = {
 766     .name = "spapr_pci",
 767     .version_id = 2,
 768     .minimum_version_id = 2,
 769     .pre_save = spapr_pci_pre_save,
 770     .post_load = spapr_pci_post_load,
 771     .fields = (VMStateField[]) {
 772         VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState),
 773         VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState),
 774         VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState),
 775         VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState),
 776         VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState),
 777         VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState),
 778         VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0,
 779                              vmstate_spapr_pci_lsi, struct spapr_pci_lsi),
 780         VMSTATE_INT32(msi_devs_num, sPAPRPHBState),
 781         VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0,
 782                                     vmstate_spapr_pci_msi, spapr_pci_msi_mig),
 783         VMSTATE_END_OF_LIST()
 784     },
 785 };
 786
 787 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
 788                                            PCIBus *rootbus)
 789 {
 790     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
 791
 792     return sphb->dtbusname;
 793 }
 794
 795 static void spapr_phb_class_init(ObjectClass *klass, void *data)
 796 {
 797     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 798     DeviceClass *dc = DEVICE_CLASS(klass);
 799     sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass);
 800
 801     hc->root_bus_path = spapr_phb_root_bus_path;
 802     dc->realize = spapr_phb_realize;
 803     dc->props = spapr_phb_properties;
 804     dc->reset = spapr_phb_reset;
 805     dc->vmsd = &vmstate_spapr_pci;
 806     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 807     dc->cannot_instantiate_with_device_add_yet = false;
 808     spc->finish_realize = spapr_phb_finish_realize;
 809 }
 810
 811 static const TypeInfo spapr_phb_info = {
 812     .name          = TYPE_SPAPR_PCI_HOST_BRIDGE,
 813     .parent        = TYPE_PCI_HOST_BRIDGE,
 814     .instance_size = sizeof(sPAPRPHBState),
 815     .class_init    = spapr_phb_class_init,
 816     .class_size    = sizeof(sPAPRPHBClass),
 817 };
 818
 819 PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index)
 820 {
 821     DeviceState *dev;
 822
 823     dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
 824     qdev_prop_set_uint32(dev, "index", index);
 825     qdev_init_nofail(dev);
 826
 827     return PCI_HOST_BRIDGE(dev);
 828 }
 829
 830 /* Macros to operate with address in OF binding to PCI */
 831 #define b_x(x, p, l)    (((x) & ((1<<(l))-1)) << (p))
 832 #define b_n(x)          b_x((x), 31, 1) /* 0 if relocatable */
 833 #define b_p(x)          b_x((x), 30, 1) /* 1 if prefetchable */
 834 #define b_t(x)          b_x((x), 29, 1) /* 1 if the address is aliased */
 835 #define b_ss(x)         b_x((x), 24, 2) /* the space code */
 836 #define b_bbbbbbbb(x)   b_x((x), 16, 8) /* bus number */
 837 #define b_ddddd(x)      b_x((x), 11, 5) /* device number */
 838 #define b_fff(x)        b_x((x), 8, 3)  /* function number */
 839 #define b_rrrrrrrr(x)   b_x((x), 0, 8)  /* register number */
 840
 841 typedef struct sPAPRTCEDT {
 842     void *fdt;
 843     int node_off;
 844 } sPAPRTCEDT;
 845
 846 static int spapr_phb_children_dt(Object *child, void *opaque)
 847 {
 848     sPAPRTCEDT *p = opaque;
 849     sPAPRTCETable *tcet;
 850
 851     tcet = (sPAPRTCETable *) object_dynamic_cast(child, TYPE_SPAPR_TCE_TABLE);
 852     if (!tcet) {
 853         return 0;
 854     }
 855
 856     spapr_dma_dt(p->fdt, p->node_off, "ibm,dma-window",
 857                  tcet->liobn, tcet->bus_offset,
 858                  tcet->nb_table << tcet->page_shift);
 859     /* Stop after the first window */
 860
 861     return 1;
 862 }
 863
 864 int spapr_populate_pci_dt(sPAPRPHBState *phb,
 865                           uint32_t xics_phandle,
 866                           void *fdt)
 867 {
 868     int bus_off, i, j;
 869     char nodename[256];
 870     uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
 871     struct {
 872         uint32_t hi;
 873         uint64_t child;
 874         uint64_t parent;
 875         uint64_t size;
 876     } QEMU_PACKED ranges[] = {
 877         {
 878             cpu_to_be32(b_ss(1)), cpu_to_be64(0),
 879             cpu_to_be64(phb->io_win_addr),
 880             cpu_to_be64(memory_region_size(&phb->iospace)),
 881         },
 882         {
 883             cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
 884             cpu_to_be64(phb->mem_win_addr),
 885             cpu_to_be64(memory_region_size(&phb->memwindow)),
 886         },
 887     };
 888     uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
 889     uint32_t interrupt_map_mask[] = {
 890         cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
 891     uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
 892
 893     /* Start populating the FDT */
 894     sprintf(nodename, "pci@%" PRIx64, phb->buid);
 895     bus_off = fdt_add_subnode(fdt, 0, nodename);
 896     if (bus_off < 0) {
 897         return bus_off;
 898     }
 899
 900 #define _FDT(exp) \
 901     do { \
 902         int ret = (exp);                                           \
 903         if (ret < 0) {                                             \
 904             return ret;                                            \
 905         }                                                          \
 906     } while (0)
 907
 908     /* Write PHB properties */
 909     _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
 910     _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
 911     _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
 912     _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
 913     _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
 914     _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
 915     _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
 916     _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
 917     _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
 918     _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
 919     _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS));
 920
 921     /* Build the interrupt-map, this must matches what is done
 922      * in pci_spapr_map_irq
 923      */
 924     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
 925                      &interrupt_map_mask, sizeof(interrupt_map_mask)));
 926     for (i = 0; i < PCI_SLOT_MAX; i++) {
 927         for (j = 0; j < PCI_NUM_PINS; j++) {
 928             uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
 929             int lsi_num = pci_spapr_swizzle(i, j);
 930
 931             irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
 932             irqmap[1] = 0;
 933             irqmap[2] = 0;
 934             irqmap[3] = cpu_to_be32(j+1);
 935             irqmap[4] = cpu_to_be32(xics_phandle);
 936             irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq);
 937             irqmap[6] = cpu_to_be32(0x8);
 938         }
 939     }
 940     /* Write interrupt map */
 941     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
 942                      sizeof(interrupt_map)));
 943
 944     object_child_foreach(OBJECT(phb), spapr_phb_children_dt,
 945                          &((sPAPRTCEDT){ .fdt = fdt, .node_off = bus_off }));
 946
 947     return 0;
 948 }
 949
 950 void spapr_pci_rtas_init(void)
 951 {
 952     spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config",
 953                         rtas_read_pci_config);
 954     spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config",
 955                         rtas_write_pci_config);
 956     spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config",
 957                         rtas_ibm_read_pci_config);
 958     spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config",
 959                         rtas_ibm_write_pci_config);
 960     if (msi_supported) {
 961         spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER,
 962                             "ibm,query-interrupt-source-number",
 963                             rtas_ibm_query_interrupt_source_number);
 964         spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
 965                             rtas_ibm_change_msi);
 966     }
 967 }
 968
 969 static void spapr_pci_register_types(void)
 970 {
 971     type_register_static(&spapr_phb_info);
 972 }
 973
 974 type_init(spapr_pci_register_types)