2 * QEMU sPAPR PCI host originated from Uninorth PCI host
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
30 #include "hw/sysbus.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/msi.h"
33 #include "hw/pci/msix.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/ppc/spapr.h"
36 #include "hw/pci-host/spapr.h"
37 #include "exec/address-spaces.h"
38 #include "exec/ram_addr.h"
41 #include "qemu/error-report.h"
42 #include "qapi/qmp/qerror.h"
43 #include "hw/ppc/fdt.h"
44 #include "hw/pci/pci_bridge.h"
45 #include "hw/pci/pci_bus.h"
46 #include "hw/pci/pci_ids.h"
47 #include "hw/ppc/spapr_drc.h"
48 #include "sysemu/device_tree.h"
49 #include "sysemu/kvm.h"
50 #include "sysemu/hostmem.h"
51 #include "sysemu/numa.h"
53 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
54 #define RTAS_QUERY_FN 0
55 #define RTAS_CHANGE_FN 1
56 #define RTAS_RESET_FN 2
57 #define RTAS_CHANGE_MSI_FN 3
58 #define RTAS_CHANGE_MSIX_FN 4
60 /* Interrupt types to return on RTAS_CHANGE_* */
61 #define RTAS_TYPE_MSI 1
62 #define RTAS_TYPE_MSIX 2
64 sPAPRPHBState
*spapr_pci_find_phb(sPAPRMachineState
*spapr
, uint64_t buid
)
68 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
69 if (sphb
->buid
!= buid
) {
78 PCIDevice
*spapr_pci_find_dev(sPAPRMachineState
*spapr
, uint64_t buid
,
81 sPAPRPHBState
*sphb
= spapr_pci_find_phb(spapr
, buid
);
82 PCIHostState
*phb
= PCI_HOST_BRIDGE(sphb
);
83 int bus_num
= (config_addr
>> 16) & 0xFF;
84 int devfn
= (config_addr
>> 8) & 0xFF;
90 return pci_find_device(phb
->bus
, bus_num
, devfn
);
93 static uint32_t rtas_pci_cfgaddr(uint32_t arg
)
95 /* This handles the encoding of extended config space addresses */
96 return ((arg
>> 20) & 0xf00) | (arg
& 0xff);
99 static void finish_read_pci_config(sPAPRMachineState
*spapr
, uint64_t buid
,
100 uint32_t addr
, uint32_t size
,
106 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
107 /* access must be 1, 2 or 4 bytes */
108 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
112 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
113 addr
= rtas_pci_cfgaddr(addr
);
115 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
116 /* Access must be to a valid device, within bounds and
117 * naturally aligned */
118 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
122 val
= pci_host_config_read_common(pci_dev
, addr
,
123 pci_config_size(pci_dev
), size
);
125 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
126 rtas_st(rets
, 1, val
);
129 static void rtas_ibm_read_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
130 uint32_t token
, uint32_t nargs
,
132 uint32_t nret
, target_ulong rets
)
137 if ((nargs
!= 4) || (nret
!= 2)) {
138 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
142 buid
= rtas_ldq(args
, 1);
143 size
= rtas_ld(args
, 3);
144 addr
= rtas_ld(args
, 0);
146 finish_read_pci_config(spapr
, buid
, addr
, size
, rets
);
149 static void rtas_read_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
150 uint32_t token
, uint32_t nargs
,
152 uint32_t nret
, target_ulong rets
)
156 if ((nargs
!= 2) || (nret
!= 2)) {
157 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
161 size
= rtas_ld(args
, 1);
162 addr
= rtas_ld(args
, 0);
164 finish_read_pci_config(spapr
, 0, addr
, size
, rets
);
167 static void finish_write_pci_config(sPAPRMachineState
*spapr
, uint64_t buid
,
168 uint32_t addr
, uint32_t size
,
169 uint32_t val
, target_ulong rets
)
173 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
174 /* access must be 1, 2 or 4 bytes */
175 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
179 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
180 addr
= rtas_pci_cfgaddr(addr
);
182 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
183 /* Access must be to a valid device, within bounds and
184 * naturally aligned */
185 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
189 pci_host_config_write_common(pci_dev
, addr
, pci_config_size(pci_dev
),
192 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
195 static void rtas_ibm_write_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
196 uint32_t token
, uint32_t nargs
,
198 uint32_t nret
, target_ulong rets
)
201 uint32_t val
, size
, addr
;
203 if ((nargs
!= 5) || (nret
!= 1)) {
204 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
208 buid
= rtas_ldq(args
, 1);
209 val
= rtas_ld(args
, 4);
210 size
= rtas_ld(args
, 3);
211 addr
= rtas_ld(args
, 0);
213 finish_write_pci_config(spapr
, buid
, addr
, size
, val
, rets
);
216 static void rtas_write_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
217 uint32_t token
, uint32_t nargs
,
219 uint32_t nret
, target_ulong rets
)
221 uint32_t val
, size
, addr
;
223 if ((nargs
!= 3) || (nret
!= 1)) {
224 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
229 val
= rtas_ld(args
, 2);
230 size
= rtas_ld(args
, 1);
231 addr
= rtas_ld(args
, 0);
233 finish_write_pci_config(spapr
, 0, addr
, size
, val
, rets
);
237 * Set MSI/MSIX message data.
238 * This is required for msi_notify()/msix_notify() which
239 * will write at the addresses via spapr_msi_write().
241 * If hwaddr == 0, all entries will have .data == first_irq i.e.
242 * table will be reset.
244 static void spapr_msi_setmsg(PCIDevice
*pdev
, hwaddr addr
, bool msix
,
245 unsigned first_irq
, unsigned req_num
)
248 MSIMessage msg
= { .address
= addr
, .data
= first_irq
};
251 msi_set_message(pdev
, msg
);
252 trace_spapr_pci_msi_setup(pdev
->name
, 0, msg
.address
);
256 for (i
= 0; i
< req_num
; ++i
) {
257 msix_set_message(pdev
, i
, msg
);
258 trace_spapr_pci_msi_setup(pdev
->name
, i
, msg
.address
);
265 static void rtas_ibm_change_msi(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
266 uint32_t token
, uint32_t nargs
,
267 target_ulong args
, uint32_t nret
,
270 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
271 uint32_t config_addr
= rtas_ld(args
, 0);
272 uint64_t buid
= rtas_ldq(args
, 1);
273 unsigned int func
= rtas_ld(args
, 3);
274 unsigned int req_num
= rtas_ld(args
, 4); /* 0 == remove all */
275 unsigned int seq_num
= rtas_ld(args
, 5);
276 unsigned int ret_intr_type
;
277 unsigned int irq
, max_irqs
= 0;
278 sPAPRPHBState
*phb
= NULL
;
279 PCIDevice
*pdev
= NULL
;
281 int *config_addr_key
;
285 /* Fins sPAPRPHBState */
286 phb
= spapr_pci_find_phb(spapr
, buid
);
288 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
291 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
297 if (msi_present(pdev
)) {
298 ret_intr_type
= RTAS_TYPE_MSI
;
299 } else if (msix_present(pdev
)) {
300 ret_intr_type
= RTAS_TYPE_MSIX
;
302 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
306 case RTAS_CHANGE_MSI_FN
:
307 if (msi_present(pdev
)) {
308 ret_intr_type
= RTAS_TYPE_MSI
;
310 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
314 case RTAS_CHANGE_MSIX_FN
:
315 if (msix_present(pdev
)) {
316 ret_intr_type
= RTAS_TYPE_MSIX
;
318 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
323 error_report("rtas_ibm_change_msi(%u) is not implemented", func
);
324 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
328 msi
= (spapr_pci_msi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
333 trace_spapr_pci_msi("Releasing wrong config", config_addr
);
334 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
338 if (!smc
->legacy_irq_allocation
) {
339 spapr_irq_msi_free(spapr
, msi
->first_irq
, msi
->num
);
341 spapr_irq_free(spapr
, msi
->first_irq
, msi
->num
);
342 if (msi_present(pdev
)) {
343 spapr_msi_setmsg(pdev
, 0, false, 0, 0);
345 if (msix_present(pdev
)) {
346 spapr_msi_setmsg(pdev
, 0, true, 0, 0);
348 g_hash_table_remove(phb
->msi
, &config_addr
);
350 trace_spapr_pci_msi("Released MSIs", config_addr
);
351 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
358 /* Check if the device supports as many IRQs as requested */
359 if (ret_intr_type
== RTAS_TYPE_MSI
) {
360 max_irqs
= msi_nr_vectors_allocated(pdev
);
361 } else if (ret_intr_type
== RTAS_TYPE_MSIX
) {
362 max_irqs
= pdev
->msix_entries_nr
;
365 error_report("Requested interrupt type %d is not enabled for device %x",
366 ret_intr_type
, config_addr
);
367 rtas_st(rets
, 0, -1); /* Hardware error */
370 /* Correct the number if the guest asked for too many */
371 if (req_num
> max_irqs
) {
372 trace_spapr_pci_msi_retry(config_addr
, req_num
, max_irqs
);
374 irq
= 0; /* to avoid misleading trace */
379 if (smc
->legacy_irq_allocation
) {
380 irq
= spapr_irq_find(spapr
, req_num
, ret_intr_type
== RTAS_TYPE_MSI
,
383 irq
= spapr_irq_msi_alloc(spapr
, req_num
,
384 ret_intr_type
== RTAS_TYPE_MSI
, &err
);
387 error_reportf_err(err
, "Can't allocate MSIs for device %x: ",
389 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
393 for (i
= 0; i
< req_num
; i
++) {
394 spapr_irq_claim(spapr
, irq
+ i
, false, &err
);
397 spapr_irq_free(spapr
, irq
, i
);
399 if (!smc
->legacy_irq_allocation
) {
400 spapr_irq_msi_free(spapr
, irq
, req_num
);
402 error_reportf_err(err
, "Can't allocate MSIs for device %x: ",
404 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
409 /* Release previous MSIs */
411 if (!smc
->legacy_irq_allocation
) {
412 spapr_irq_msi_free(spapr
, msi
->first_irq
, msi
->num
);
414 spapr_irq_free(spapr
, msi
->first_irq
, msi
->num
);
415 g_hash_table_remove(phb
->msi
, &config_addr
);
418 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
419 spapr_msi_setmsg(pdev
, SPAPR_PCI_MSI_WINDOW
, ret_intr_type
== RTAS_TYPE_MSIX
,
422 /* Add MSI device to cache */
423 msi
= g_new(spapr_pci_msi
, 1);
424 msi
->first_irq
= irq
;
426 config_addr_key
= g_new(int, 1);
427 *config_addr_key
= config_addr
;
428 g_hash_table_insert(phb
->msi
, config_addr_key
, msi
);
431 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
432 rtas_st(rets
, 1, req_num
);
433 rtas_st(rets
, 2, ++seq_num
);
435 rtas_st(rets
, 3, ret_intr_type
);
438 trace_spapr_pci_rtas_ibm_change_msi(config_addr
, func
, req_num
, irq
);
441 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU
*cpu
,
442 sPAPRMachineState
*spapr
,
449 uint32_t config_addr
= rtas_ld(args
, 0);
450 uint64_t buid
= rtas_ldq(args
, 1);
451 unsigned int intr_src_num
= -1, ioa_intr_num
= rtas_ld(args
, 3);
452 sPAPRPHBState
*phb
= NULL
;
453 PCIDevice
*pdev
= NULL
;
456 /* Find sPAPRPHBState */
457 phb
= spapr_pci_find_phb(spapr
, buid
);
459 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
462 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
466 /* Find device descriptor and start IRQ */
467 msi
= (spapr_pci_msi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
468 if (!msi
|| !msi
->first_irq
|| !msi
->num
|| (ioa_intr_num
>= msi
->num
)) {
469 trace_spapr_pci_msi("Failed to return vector", config_addr
);
470 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
473 intr_src_num
= msi
->first_irq
+ ioa_intr_num
;
474 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num
,
477 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
478 rtas_st(rets
, 1, intr_src_num
);
479 rtas_st(rets
, 2, 1);/* 0 == level; 1 == edge */
482 static void rtas_ibm_set_eeh_option(PowerPCCPU
*cpu
,
483 sPAPRMachineState
*spapr
,
484 uint32_t token
, uint32_t nargs
,
485 target_ulong args
, uint32_t nret
,
489 uint32_t addr
, option
;
493 if ((nargs
!= 4) || (nret
!= 1)) {
494 goto param_error_exit
;
497 buid
= rtas_ldq(args
, 1);
498 addr
= rtas_ld(args
, 0);
499 option
= rtas_ld(args
, 3);
501 sphb
= spapr_pci_find_phb(spapr
, buid
);
503 goto param_error_exit
;
506 if (!spapr_phb_eeh_available(sphb
)) {
507 goto param_error_exit
;
510 ret
= spapr_phb_vfio_eeh_set_option(sphb
, addr
, option
);
511 rtas_st(rets
, 0, ret
);
515 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
518 static void rtas_ibm_get_config_addr_info2(PowerPCCPU
*cpu
,
519 sPAPRMachineState
*spapr
,
520 uint32_t token
, uint32_t nargs
,
521 target_ulong args
, uint32_t nret
,
526 uint32_t addr
, option
;
529 if ((nargs
!= 4) || (nret
!= 2)) {
530 goto param_error_exit
;
533 buid
= rtas_ldq(args
, 1);
534 sphb
= spapr_pci_find_phb(spapr
, buid
);
536 goto param_error_exit
;
539 if (!spapr_phb_eeh_available(sphb
)) {
540 goto param_error_exit
;
544 * We always have PE address of form "00BB0001". "BB"
545 * represents the bus number of PE's primary bus.
547 option
= rtas_ld(args
, 3);
549 case RTAS_GET_PE_ADDR
:
550 addr
= rtas_ld(args
, 0);
551 pdev
= spapr_pci_find_dev(spapr
, buid
, addr
);
553 goto param_error_exit
;
556 rtas_st(rets
, 1, (pci_bus_num(pci_get_bus(pdev
)) << 16) + 1);
558 case RTAS_GET_PE_MODE
:
559 rtas_st(rets
, 1, RTAS_PE_MODE_SHARED
);
562 goto param_error_exit
;
565 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
569 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
572 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU
*cpu
,
573 sPAPRMachineState
*spapr
,
574 uint32_t token
, uint32_t nargs
,
575 target_ulong args
, uint32_t nret
,
582 if ((nargs
!= 3) || (nret
!= 4 && nret
!= 5)) {
583 goto param_error_exit
;
586 buid
= rtas_ldq(args
, 1);
587 sphb
= spapr_pci_find_phb(spapr
, buid
);
589 goto param_error_exit
;
592 if (!spapr_phb_eeh_available(sphb
)) {
593 goto param_error_exit
;
596 ret
= spapr_phb_vfio_eeh_get_state(sphb
, &state
);
597 rtas_st(rets
, 0, ret
);
598 if (ret
!= RTAS_OUT_SUCCESS
) {
602 rtas_st(rets
, 1, state
);
603 rtas_st(rets
, 2, RTAS_EEH_SUPPORT
);
604 rtas_st(rets
, 3, RTAS_EEH_PE_UNAVAIL_INFO
);
606 rtas_st(rets
, 4, RTAS_EEH_PE_RECOVER_INFO
);
611 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
614 static void rtas_ibm_set_slot_reset(PowerPCCPU
*cpu
,
615 sPAPRMachineState
*spapr
,
616 uint32_t token
, uint32_t nargs
,
617 target_ulong args
, uint32_t nret
,
625 if ((nargs
!= 4) || (nret
!= 1)) {
626 goto param_error_exit
;
629 buid
= rtas_ldq(args
, 1);
630 option
= rtas_ld(args
, 3);
631 sphb
= spapr_pci_find_phb(spapr
, buid
);
633 goto param_error_exit
;
636 if (!spapr_phb_eeh_available(sphb
)) {
637 goto param_error_exit
;
640 ret
= spapr_phb_vfio_eeh_reset(sphb
, option
);
641 rtas_st(rets
, 0, ret
);
645 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
648 static void rtas_ibm_configure_pe(PowerPCCPU
*cpu
,
649 sPAPRMachineState
*spapr
,
650 uint32_t token
, uint32_t nargs
,
651 target_ulong args
, uint32_t nret
,
658 if ((nargs
!= 3) || (nret
!= 1)) {
659 goto param_error_exit
;
662 buid
= rtas_ldq(args
, 1);
663 sphb
= spapr_pci_find_phb(spapr
, buid
);
665 goto param_error_exit
;
668 if (!spapr_phb_eeh_available(sphb
)) {
669 goto param_error_exit
;
672 ret
= spapr_phb_vfio_eeh_configure(sphb
);
673 rtas_st(rets
, 0, ret
);
677 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
680 /* To support it later */
681 static void rtas_ibm_slot_error_detail(PowerPCCPU
*cpu
,
682 sPAPRMachineState
*spapr
,
683 uint32_t token
, uint32_t nargs
,
684 target_ulong args
, uint32_t nret
,
691 if ((nargs
!= 8) || (nret
!= 1)) {
692 goto param_error_exit
;
695 buid
= rtas_ldq(args
, 1);
696 sphb
= spapr_pci_find_phb(spapr
, buid
);
698 goto param_error_exit
;
701 if (!spapr_phb_eeh_available(sphb
)) {
702 goto param_error_exit
;
705 option
= rtas_ld(args
, 7);
707 case RTAS_SLOT_TEMP_ERR_LOG
:
708 case RTAS_SLOT_PERM_ERR_LOG
:
711 goto param_error_exit
;
714 /* We don't have error log yet */
715 rtas_st(rets
, 0, RTAS_OUT_NO_ERRORS_FOUND
);
719 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
722 static int pci_spapr_swizzle(int slot
, int pin
)
724 return (slot
+ pin
) % PCI_NUM_PINS
;
727 static int pci_spapr_map_irq(PCIDevice
*pci_dev
, int irq_num
)
730 * Here we need to convert pci_dev + irq_num to some unique value
731 * which is less than number of IRQs on the specific bus (4). We
732 * use standard PCI swizzling, that is (slot number + pin number)
735 return pci_spapr_swizzle(PCI_SLOT(pci_dev
->devfn
), irq_num
);
738 static void pci_spapr_set_irq(void *opaque
, int irq_num
, int level
)
741 * Here we use the number returned by pci_spapr_map_irq to find a
742 * corresponding qemu_irq.
744 sPAPRPHBState
*phb
= opaque
;
746 trace_spapr_pci_lsi_set(phb
->dtbusname
, irq_num
, phb
->lsi_table
[irq_num
].irq
);
747 qemu_set_irq(spapr_phb_lsi_qirq(phb
, irq_num
), level
);
750 static PCIINTxRoute
spapr_route_intx_pin_to_irq(void *opaque
, int pin
)
752 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(opaque
);
755 route
.mode
= PCI_INTX_ENABLED
;
756 route
.irq
= sphb
->lsi_table
[pin
].irq
;
762 * MSI/MSIX memory region implementation.
763 * The handler handles both MSI and MSIX.
764 * The vector number is encoded in least bits in data.
766 static void spapr_msi_write(void *opaque
, hwaddr addr
,
767 uint64_t data
, unsigned size
)
769 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
772 trace_spapr_pci_msi_write(addr
, data
, irq
);
774 qemu_irq_pulse(spapr_qirq(spapr
, irq
));
777 static const MemoryRegionOps spapr_msi_ops
= {
778 /* There is no .read as the read result is undefined by PCI spec */
780 .write
= spapr_msi_write
,
781 .endianness
= DEVICE_LITTLE_ENDIAN
787 static AddressSpace
*spapr_pci_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
789 sPAPRPHBState
*phb
= opaque
;
791 return &phb
->iommu_as
;
794 static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState
*sphb
, PCIDevice
*pdev
)
796 char *path
= NULL
, *buf
= NULL
, *host
= NULL
;
798 /* Get the PCI VFIO host id */
799 host
= object_property_get_str(OBJECT(pdev
), "host", NULL
);
804 /* Construct the path of the file that will give us the DT location */
805 path
= g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host
);
807 if (!g_file_get_contents(path
, &buf
, NULL
, NULL
)) {
812 /* Construct and read from host device tree the loc-code */
813 path
= g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf
);
815 if (!g_file_get_contents(path
, &buf
, NULL
, NULL
)) {
825 static char *spapr_phb_get_loc_code(sPAPRPHBState
*sphb
, PCIDevice
*pdev
)
828 const char *devtype
= "qemu";
829 uint32_t busnr
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
))));
831 if (object_dynamic_cast(OBJECT(pdev
), "vfio-pci")) {
832 buf
= spapr_phb_vfio_get_loc_code(sphb
, pdev
);
839 * For emulated devices and VFIO-failure case, make up
842 buf
= g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
843 devtype
, pdev
->name
, sphb
->index
, busnr
,
844 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
));
848 /* Macros to operate with address in OF binding to PCI */
849 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
850 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
851 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
852 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
853 #define b_ss(x) b_x((x), 24, 2) /* the space code */
854 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
855 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
856 #define b_fff(x) b_x((x), 8, 3) /* function number */
857 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
859 /* for 'reg'/'assigned-addresses' OF properties */
860 #define RESOURCE_CELLS_SIZE 2
861 #define RESOURCE_CELLS_ADDRESS 3
863 typedef struct ResourceFields
{
869 } QEMU_PACKED ResourceFields
;
871 typedef struct ResourceProps
{
872 ResourceFields reg
[8];
873 ResourceFields assigned
[7];
875 uint32_t assigned_len
;
878 /* fill in the 'reg'/'assigned-resources' OF properties for
879 * a PCI device. 'reg' describes resource requirements for a
880 * device's IO/MEM regions, 'assigned-addresses' describes the
881 * actual resource assignments.
883 * the properties are arrays of ('phys-addr', 'size') pairs describing
884 * the addressable regions of the PCI device, where 'phys-addr' is a
885 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
886 * (phys.hi, phys.mid, phys.lo), and 'size' is a
887 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
889 * phys.hi = 0xYYXXXXZZ, where:
894 * ||| + 00 if configuration space
895 * ||| + 01 if IO region,
896 * ||| + 10 if 32-bit MEM region
897 * ||| + 11 if 64-bit MEM region
899 * ||+------ for non-relocatable IO: 1 if aliased
900 * || for relocatable IO: 1 if below 64KB
901 * || for MEM: 1 if below 1MB
902 * |+------- 1 if region is prefetchable
903 * +-------- 1 if region is non-relocatable
904 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
906 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding
909 * phys.mid and phys.lo correspond respectively to the hi/lo portions
910 * of the actual address of the region.
912 * how the phys-addr/size values are used differ slightly between
913 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has
914 * an additional description for the config space region of the
915 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0
916 * to describe the region as relocatable, with an address-mapping
917 * that corresponds directly to the PHB's address space for the
918 * resource. 'assigned-addresses' always has n=1 set with an absolute
919 * address assigned for the resource. in general, 'assigned-addresses'
920 * won't be populated, since addresses for PCI devices are generally
921 * unmapped initially and left to the guest to assign.
923 * note also that addresses defined in these properties are, at least
924 * for PAPR guests, relative to the PHBs IO/MEM windows, and
925 * correspond directly to the addresses in the BARs.
927 * in accordance with PCI Bus Binding to Open Firmware,
928 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
931 static void populate_resource_props(PCIDevice
*d
, ResourceProps
*rp
)
933 int bus_num
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d
))));
934 uint32_t dev_id
= (b_bbbbbbbb(bus_num
) |
935 b_ddddd(PCI_SLOT(d
->devfn
)) |
936 b_fff(PCI_FUNC(d
->devfn
)));
937 ResourceFields
*reg
, *assigned
;
938 int i
, reg_idx
= 0, assigned_idx
= 0;
940 /* config space region */
941 reg
= &rp
->reg
[reg_idx
++];
942 reg
->phys_hi
= cpu_to_be32(dev_id
);
948 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
949 if (!d
->io_regions
[i
].size
) {
953 reg
= &rp
->reg
[reg_idx
++];
955 reg
->phys_hi
= cpu_to_be32(dev_id
| b_rrrrrrrr(pci_bar(d
, i
)));
956 if (d
->io_regions
[i
].type
& PCI_BASE_ADDRESS_SPACE_IO
) {
957 reg
->phys_hi
|= cpu_to_be32(b_ss(1));
958 } else if (d
->io_regions
[i
].type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
959 reg
->phys_hi
|= cpu_to_be32(b_ss(3));
961 reg
->phys_hi
|= cpu_to_be32(b_ss(2));
965 reg
->size_hi
= cpu_to_be32(d
->io_regions
[i
].size
>> 32);
966 reg
->size_lo
= cpu_to_be32(d
->io_regions
[i
].size
);
968 if (d
->io_regions
[i
].addr
== PCI_BAR_UNMAPPED
) {
972 assigned
= &rp
->assigned
[assigned_idx
++];
973 assigned
->phys_hi
= cpu_to_be32(be32_to_cpu(reg
->phys_hi
) | b_n(1));
974 assigned
->phys_mid
= cpu_to_be32(d
->io_regions
[i
].addr
>> 32);
975 assigned
->phys_lo
= cpu_to_be32(d
->io_regions
[i
].addr
);
976 assigned
->size_hi
= reg
->size_hi
;
977 assigned
->size_lo
= reg
->size_lo
;
980 rp
->reg_len
= reg_idx
* sizeof(ResourceFields
);
981 rp
->assigned_len
= assigned_idx
* sizeof(ResourceFields
);
984 typedef struct PCIClass PCIClass
;
985 typedef struct PCISubClass PCISubClass
;
986 typedef struct PCIIFace PCIIFace
;
996 const PCIIFace
*iface
;
1001 const PCISubClass
*subc
;
1004 static const PCISubClass undef_subclass
[] = {
1005 { PCI_CLASS_NOT_DEFINED_VGA
, "display", NULL
},
1006 { 0xFF, NULL
, NULL
},
1009 static const PCISubClass mass_subclass
[] = {
1010 { PCI_CLASS_STORAGE_SCSI
, "scsi", NULL
},
1011 { PCI_CLASS_STORAGE_IDE
, "ide", NULL
},
1012 { PCI_CLASS_STORAGE_FLOPPY
, "fdc", NULL
},
1013 { PCI_CLASS_STORAGE_IPI
, "ipi", NULL
},
1014 { PCI_CLASS_STORAGE_RAID
, "raid", NULL
},
1015 { PCI_CLASS_STORAGE_ATA
, "ata", NULL
},
1016 { PCI_CLASS_STORAGE_SATA
, "sata", NULL
},
1017 { PCI_CLASS_STORAGE_SAS
, "sas", NULL
},
1018 { 0xFF, NULL
, NULL
},
1021 static const PCISubClass net_subclass
[] = {
1022 { PCI_CLASS_NETWORK_ETHERNET
, "ethernet", NULL
},
1023 { PCI_CLASS_NETWORK_TOKEN_RING
, "token-ring", NULL
},
1024 { PCI_CLASS_NETWORK_FDDI
, "fddi", NULL
},
1025 { PCI_CLASS_NETWORK_ATM
, "atm", NULL
},
1026 { PCI_CLASS_NETWORK_ISDN
, "isdn", NULL
},
1027 { PCI_CLASS_NETWORK_WORLDFIP
, "worldfip", NULL
},
1028 { PCI_CLASS_NETWORK_PICMG214
, "picmg", NULL
},
1029 { 0xFF, NULL
, NULL
},
1032 static const PCISubClass displ_subclass
[] = {
1033 { PCI_CLASS_DISPLAY_VGA
, "vga", NULL
},
1034 { PCI_CLASS_DISPLAY_XGA
, "xga", NULL
},
1035 { PCI_CLASS_DISPLAY_3D
, "3d-controller", NULL
},
1036 { 0xFF, NULL
, NULL
},
1039 static const PCISubClass media_subclass
[] = {
1040 { PCI_CLASS_MULTIMEDIA_VIDEO
, "video", NULL
},
1041 { PCI_CLASS_MULTIMEDIA_AUDIO
, "sound", NULL
},
1042 { PCI_CLASS_MULTIMEDIA_PHONE
, "telephony", NULL
},
1043 { 0xFF, NULL
, NULL
},
1046 static const PCISubClass mem_subclass
[] = {
1047 { PCI_CLASS_MEMORY_RAM
, "memory", NULL
},
1048 { PCI_CLASS_MEMORY_FLASH
, "flash", NULL
},
1049 { 0xFF, NULL
, NULL
},
1052 static const PCISubClass bridg_subclass
[] = {
1053 { PCI_CLASS_BRIDGE_HOST
, "host", NULL
},
1054 { PCI_CLASS_BRIDGE_ISA
, "isa", NULL
},
1055 { PCI_CLASS_BRIDGE_EISA
, "eisa", NULL
},
1056 { PCI_CLASS_BRIDGE_MC
, "mca", NULL
},
1057 { PCI_CLASS_BRIDGE_PCI
, "pci", NULL
},
1058 { PCI_CLASS_BRIDGE_PCMCIA
, "pcmcia", NULL
},
1059 { PCI_CLASS_BRIDGE_NUBUS
, "nubus", NULL
},
1060 { PCI_CLASS_BRIDGE_CARDBUS
, "cardbus", NULL
},
1061 { PCI_CLASS_BRIDGE_RACEWAY
, "raceway", NULL
},
1062 { PCI_CLASS_BRIDGE_PCI_SEMITP
, "semi-transparent-pci", NULL
},
1063 { PCI_CLASS_BRIDGE_IB_PCI
, "infiniband", NULL
},
1064 { 0xFF, NULL
, NULL
},
1067 static const PCISubClass comm_subclass
[] = {
1068 { PCI_CLASS_COMMUNICATION_SERIAL
, "serial", NULL
},
1069 { PCI_CLASS_COMMUNICATION_PARALLEL
, "parallel", NULL
},
1070 { PCI_CLASS_COMMUNICATION_MULTISERIAL
, "multiport-serial", NULL
},
1071 { PCI_CLASS_COMMUNICATION_MODEM
, "modem", NULL
},
1072 { PCI_CLASS_COMMUNICATION_GPIB
, "gpib", NULL
},
1073 { PCI_CLASS_COMMUNICATION_SC
, "smart-card", NULL
},
1074 { 0xFF, NULL
, NULL
, },
1077 static const PCIIFace pic_iface
[] = {
1078 { PCI_CLASS_SYSTEM_PIC_IOAPIC
, "io-apic" },
1079 { PCI_CLASS_SYSTEM_PIC_IOXAPIC
, "io-xapic" },
1083 static const PCISubClass sys_subclass
[] = {
1084 { PCI_CLASS_SYSTEM_PIC
, "interrupt-controller", pic_iface
},
1085 { PCI_CLASS_SYSTEM_DMA
, "dma-controller", NULL
},
1086 { PCI_CLASS_SYSTEM_TIMER
, "timer", NULL
},
1087 { PCI_CLASS_SYSTEM_RTC
, "rtc", NULL
},
1088 { PCI_CLASS_SYSTEM_PCI_HOTPLUG
, "hot-plug-controller", NULL
},
1089 { PCI_CLASS_SYSTEM_SDHCI
, "sd-host-controller", NULL
},
1090 { 0xFF, NULL
, NULL
},
1093 static const PCISubClass inp_subclass
[] = {
1094 { PCI_CLASS_INPUT_KEYBOARD
, "keyboard", NULL
},
1095 { PCI_CLASS_INPUT_PEN
, "pen", NULL
},
1096 { PCI_CLASS_INPUT_MOUSE
, "mouse", NULL
},
1097 { PCI_CLASS_INPUT_SCANNER
, "scanner", NULL
},
1098 { PCI_CLASS_INPUT_GAMEPORT
, "gameport", NULL
},
1099 { 0xFF, NULL
, NULL
},
1102 static const PCISubClass dock_subclass
[] = {
1103 { PCI_CLASS_DOCKING_GENERIC
, "dock", NULL
},
1104 { 0xFF, NULL
, NULL
},
1107 static const PCISubClass cpu_subclass
[] = {
1108 { PCI_CLASS_PROCESSOR_PENTIUM
, "pentium", NULL
},
1109 { PCI_CLASS_PROCESSOR_POWERPC
, "powerpc", NULL
},
1110 { PCI_CLASS_PROCESSOR_MIPS
, "mips", NULL
},
1111 { PCI_CLASS_PROCESSOR_CO
, "co-processor", NULL
},
1112 { 0xFF, NULL
, NULL
},
1115 static const PCIIFace usb_iface
[] = {
1116 { PCI_CLASS_SERIAL_USB_UHCI
, "usb-uhci" },
1117 { PCI_CLASS_SERIAL_USB_OHCI
, "usb-ohci", },
1118 { PCI_CLASS_SERIAL_USB_EHCI
, "usb-ehci" },
1119 { PCI_CLASS_SERIAL_USB_XHCI
, "usb-xhci" },
1120 { PCI_CLASS_SERIAL_USB_UNKNOWN
, "usb-unknown" },
1121 { PCI_CLASS_SERIAL_USB_DEVICE
, "usb-device" },
1125 static const PCISubClass ser_subclass
[] = {
1126 { PCI_CLASS_SERIAL_FIREWIRE
, "firewire", NULL
},
1127 { PCI_CLASS_SERIAL_ACCESS
, "access-bus", NULL
},
1128 { PCI_CLASS_SERIAL_SSA
, "ssa", NULL
},
1129 { PCI_CLASS_SERIAL_USB
, "usb", usb_iface
},
1130 { PCI_CLASS_SERIAL_FIBER
, "fibre-channel", NULL
},
1131 { PCI_CLASS_SERIAL_SMBUS
, "smb", NULL
},
1132 { PCI_CLASS_SERIAL_IB
, "infiniband", NULL
},
1133 { PCI_CLASS_SERIAL_IPMI
, "ipmi", NULL
},
1134 { PCI_CLASS_SERIAL_SERCOS
, "sercos", NULL
},
1135 { PCI_CLASS_SERIAL_CANBUS
, "canbus", NULL
},
1136 { 0xFF, NULL
, NULL
},
1139 static const PCISubClass wrl_subclass
[] = {
1140 { PCI_CLASS_WIRELESS_IRDA
, "irda", NULL
},
1141 { PCI_CLASS_WIRELESS_CIR
, "consumer-ir", NULL
},
1142 { PCI_CLASS_WIRELESS_RF_CONTROLLER
, "rf-controller", NULL
},
1143 { PCI_CLASS_WIRELESS_BLUETOOTH
, "bluetooth", NULL
},
1144 { PCI_CLASS_WIRELESS_BROADBAND
, "broadband", NULL
},
1145 { 0xFF, NULL
, NULL
},
1148 static const PCISubClass sat_subclass
[] = {
1149 { PCI_CLASS_SATELLITE_TV
, "satellite-tv", NULL
},
1150 { PCI_CLASS_SATELLITE_AUDIO
, "satellite-audio", NULL
},
1151 { PCI_CLASS_SATELLITE_VOICE
, "satellite-voice", NULL
},
1152 { PCI_CLASS_SATELLITE_DATA
, "satellite-data", NULL
},
1153 { 0xFF, NULL
, NULL
},
1156 static const PCISubClass crypt_subclass
[] = {
1157 { PCI_CLASS_CRYPT_NETWORK
, "network-encryption", NULL
},
1158 { PCI_CLASS_CRYPT_ENTERTAINMENT
,
1159 "entertainment-encryption", NULL
},
1160 { 0xFF, NULL
, NULL
},
1163 static const PCISubClass spc_subclass
[] = {
1164 { PCI_CLASS_SP_DPIO
, "dpio", NULL
},
1165 { PCI_CLASS_SP_PERF
, "counter", NULL
},
1166 { PCI_CLASS_SP_SYNCH
, "measurement", NULL
},
1167 { PCI_CLASS_SP_MANAGEMENT
, "management-card", NULL
},
1168 { 0xFF, NULL
, NULL
},
1171 static const PCIClass pci_classes
[] = {
1172 { "legacy-device", undef_subclass
},
1173 { "mass-storage", mass_subclass
},
1174 { "network", net_subclass
},
1175 { "display", displ_subclass
, },
1176 { "multimedia-device", media_subclass
},
1177 { "memory-controller", mem_subclass
},
1178 { "unknown-bridge", bridg_subclass
},
1179 { "communication-controller", comm_subclass
},
1180 { "system-peripheral", sys_subclass
},
1181 { "input-controller", inp_subclass
},
1182 { "docking-station", dock_subclass
},
1183 { "cpu", cpu_subclass
},
1184 { "serial-bus", ser_subclass
},
1185 { "wireless-controller", wrl_subclass
},
1186 { "intelligent-io", NULL
},
1187 { "satellite-device", sat_subclass
},
1188 { "encryption", crypt_subclass
},
1189 { "data-processing-controller", spc_subclass
},
1192 static const char *pci_find_device_name(uint8_t class, uint8_t subclass
,
1195 const PCIClass
*pclass
;
1196 const PCISubClass
*psubclass
;
1197 const PCIIFace
*piface
;
1200 if (class >= ARRAY_SIZE(pci_classes
)) {
1204 pclass
= pci_classes
+ class;
1205 name
= pclass
->name
;
1207 if (pclass
->subc
== NULL
) {
1211 psubclass
= pclass
->subc
;
1212 while ((psubclass
->subclass
& 0xff) != 0xff) {
1213 if ((psubclass
->subclass
& 0xff) == subclass
) {
1214 name
= psubclass
->name
;
1220 piface
= psubclass
->iface
;
1221 if (piface
== NULL
) {
1224 while ((piface
->iface
& 0xff) != 0xff) {
1225 if ((piface
->iface
& 0xff) == iface
) {
1226 name
= piface
->name
;
1235 static gchar
*pci_get_node_name(PCIDevice
*dev
)
1237 int slot
= PCI_SLOT(dev
->devfn
);
1238 int func
= PCI_FUNC(dev
->devfn
);
1239 uint32_t ccode
= pci_default_read_config(dev
, PCI_CLASS_PROG
, 3);
1242 name
= pci_find_device_name((ccode
>> 16) & 0xff, (ccode
>> 8) & 0xff,
1246 return g_strdup_printf("%s@%x,%x", name
, slot
, func
);
1248 return g_strdup_printf("%s@%x", name
, slot
);
1252 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState
*phb
,
1255 static void spapr_populate_pci_child_dt(PCIDevice
*dev
, void *fdt
, int offset
,
1256 sPAPRPHBState
*sphb
)
1259 bool is_bridge
= false;
1262 uint32_t drc_index
= spapr_phb_get_pci_drc_index(sphb
, dev
);
1263 uint32_t ccode
= pci_default_read_config(dev
, PCI_CLASS_PROG
, 3);
1264 uint32_t max_msi
, max_msix
;
1266 if (pci_default_read_config(dev
, PCI_HEADER_TYPE
, 1) ==
1267 PCI_HEADER_TYPE_BRIDGE
) {
1271 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
1272 _FDT(fdt_setprop_cell(fdt
, offset
, "vendor-id",
1273 pci_default_read_config(dev
, PCI_VENDOR_ID
, 2)));
1274 _FDT(fdt_setprop_cell(fdt
, offset
, "device-id",
1275 pci_default_read_config(dev
, PCI_DEVICE_ID
, 2)));
1276 _FDT(fdt_setprop_cell(fdt
, offset
, "revision-id",
1277 pci_default_read_config(dev
, PCI_REVISION_ID
, 1)));
1278 _FDT(fdt_setprop_cell(fdt
, offset
, "class-code", ccode
));
1279 if (pci_default_read_config(dev
, PCI_INTERRUPT_PIN
, 1)) {
1280 _FDT(fdt_setprop_cell(fdt
, offset
, "interrupts",
1281 pci_default_read_config(dev
, PCI_INTERRUPT_PIN
, 1)));
1285 _FDT(fdt_setprop_cell(fdt
, offset
, "min-grant",
1286 pci_default_read_config(dev
, PCI_MIN_GNT
, 1)));
1287 _FDT(fdt_setprop_cell(fdt
, offset
, "max-latency",
1288 pci_default_read_config(dev
, PCI_MAX_LAT
, 1)));
1291 if (pci_default_read_config(dev
, PCI_SUBSYSTEM_ID
, 2)) {
1292 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-id",
1293 pci_default_read_config(dev
, PCI_SUBSYSTEM_ID
, 2)));
1296 if (pci_default_read_config(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2)) {
1297 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-vendor-id",
1298 pci_default_read_config(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2)));
1301 _FDT(fdt_setprop_cell(fdt
, offset
, "cache-line-size",
1302 pci_default_read_config(dev
, PCI_CACHE_LINE_SIZE
, 1)));
1304 /* the following fdt cells are masked off the pci status register */
1305 pci_status
= pci_default_read_config(dev
, PCI_STATUS
, 2);
1306 _FDT(fdt_setprop_cell(fdt
, offset
, "devsel-speed",
1307 PCI_STATUS_DEVSEL_MASK
& pci_status
));
1309 if (pci_status
& PCI_STATUS_FAST_BACK
) {
1310 _FDT(fdt_setprop(fdt
, offset
, "fast-back-to-back", NULL
, 0));
1312 if (pci_status
& PCI_STATUS_66MHZ
) {
1313 _FDT(fdt_setprop(fdt
, offset
, "66mhz-capable", NULL
, 0));
1315 if (pci_status
& PCI_STATUS_UDF
) {
1316 _FDT(fdt_setprop(fdt
, offset
, "udf-supported", NULL
, 0));
1319 _FDT(fdt_setprop_string(fdt
, offset
, "name",
1320 pci_find_device_name((ccode
>> 16) & 0xff,
1321 (ccode
>> 8) & 0xff,
1324 buf
= spapr_phb_get_loc_code(sphb
, dev
);
1325 _FDT(fdt_setprop_string(fdt
, offset
, "ibm,loc-code", buf
));
1329 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
));
1332 _FDT(fdt_setprop_cell(fdt
, offset
, "#address-cells",
1333 RESOURCE_CELLS_ADDRESS
));
1334 _FDT(fdt_setprop_cell(fdt
, offset
, "#size-cells",
1335 RESOURCE_CELLS_SIZE
));
1337 if (msi_present(dev
)) {
1338 max_msi
= msi_nr_vectors_allocated(dev
);
1340 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,req#msi", max_msi
));
1343 if (msix_present(dev
)) {
1344 max_msix
= dev
->msix_entries_nr
;
1346 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,req#msi-x", max_msix
));
1350 populate_resource_props(dev
, &rp
);
1351 _FDT(fdt_setprop(fdt
, offset
, "reg", (uint8_t *)rp
.reg
, rp
.reg_len
));
1352 _FDT(fdt_setprop(fdt
, offset
, "assigned-addresses",
1353 (uint8_t *)rp
.assigned
, rp
.assigned_len
));
1355 if (sphb
->pcie_ecs
&& pci_is_express(dev
)) {
1356 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,pci-config-space-type", 0x1));
1360 /* create OF node for pci device and required OF DT properties */
1361 static int spapr_create_pci_child_dt(sPAPRPHBState
*phb
, PCIDevice
*dev
,
1362 void *fdt
, int node_offset
)
1367 nodename
= pci_get_node_name(dev
);
1368 _FDT(offset
= fdt_add_subnode(fdt
, node_offset
, nodename
));
1371 spapr_populate_pci_child_dt(dev
, fdt
, offset
, phb
);
1376 /* Callback to be called during DRC release. */
1377 void spapr_phb_remove_pci_device_cb(DeviceState
*dev
)
1379 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
1381 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
1384 static sPAPRDRConnector
*spapr_phb_get_pci_func_drc(sPAPRPHBState
*phb
,
1388 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI
,
1389 (phb
->index
<< 16) | (busnr
<< 8) | devfn
);
1392 static sPAPRDRConnector
*spapr_phb_get_pci_drc(sPAPRPHBState
*phb
,
1395 uint32_t busnr
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
))));
1396 return spapr_phb_get_pci_func_drc(phb
, busnr
, pdev
->devfn
);
1399 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState
*phb
,
1402 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1408 return spapr_drc_index(drc
);
1411 int spapr_pci_dt_populate(sPAPRDRConnector
*drc
, sPAPRMachineState
*spapr
,
1412 void *fdt
, int *fdt_start_offset
, Error
**errp
)
1414 HotplugHandler
*plug_handler
= qdev_get_hotplug_handler(drc
->dev
);
1415 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(plug_handler
);
1416 PCIDevice
*pdev
= PCI_DEVICE(drc
->dev
);
1418 *fdt_start_offset
= spapr_create_pci_child_dt(sphb
, pdev
, fdt
, 0);
1422 static void spapr_pci_plug(HotplugHandler
*plug_handler
,
1423 DeviceState
*plugged_dev
, Error
**errp
)
1425 sPAPRPHBState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1426 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1427 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1428 Error
*local_err
= NULL
;
1429 PCIBus
*bus
= PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
)));
1430 uint32_t slotnr
= PCI_SLOT(pdev
->devfn
);
1432 /* if DR is disabled we don't need to do anything in the case of
1433 * hotplug or coldplug callbacks
1435 if (!phb
->dr_enabled
) {
1436 /* if this is a hotplug operation initiated by the user
1437 * we need to let them know it's not enabled
1439 if (plugged_dev
->hotplugged
) {
1440 error_setg(&local_err
, QERR_BUS_NO_HOTPLUG
,
1441 object_get_typename(OBJECT(phb
)));
1448 /* Following the QEMU convention used for PCIe multifunction
1449 * hotplug, we do not allow functions to be hotplugged to a
1450 * slot that already has function 0 present
1452 if (plugged_dev
->hotplugged
&& bus
->devices
[PCI_DEVFN(slotnr
, 0)] &&
1453 PCI_FUNC(pdev
->devfn
) != 0) {
1454 error_setg(&local_err
, "PCI: slot %d function 0 already ocuppied by %s,"
1455 " additional functions can no longer be exposed to guest.",
1456 slotnr
, bus
->devices
[PCI_DEVFN(slotnr
, 0)]->name
);
1460 spapr_drc_attach(drc
, DEVICE(pdev
), &local_err
);
1465 /* If this is function 0, signal hotplug for all the device functions.
1466 * Otherwise defer sending the hotplug event.
1468 if (!spapr_drc_hotplugged(plugged_dev
)) {
1469 spapr_drc_reset(drc
);
1470 } else if (PCI_FUNC(pdev
->devfn
) == 0) {
1473 for (i
= 0; i
< 8; i
++) {
1474 sPAPRDRConnector
*func_drc
;
1475 sPAPRDRConnectorClass
*func_drck
;
1476 sPAPRDREntitySense state
;
1478 func_drc
= spapr_phb_get_pci_func_drc(phb
, pci_bus_num(bus
),
1479 PCI_DEVFN(slotnr
, i
));
1480 func_drck
= SPAPR_DR_CONNECTOR_GET_CLASS(func_drc
);
1481 state
= func_drck
->dr_entity_sense(func_drc
);
1483 if (state
== SPAPR_DR_ENTITY_SENSE_PRESENT
) {
1484 spapr_hotplug_req_add_by_index(func_drc
);
1491 error_propagate(errp
, local_err
);
1495 static void spapr_pci_unplug(HotplugHandler
*plug_handler
,
1496 DeviceState
*plugged_dev
, Error
**errp
)
1498 /* some version guests do not wait for completion of a device
1499 * cleanup (generally done asynchronously by the kernel) before
1500 * signaling to QEMU that the device is safe, but instead sleep
1501 * for some 'safe' period of time. unfortunately on a busy host
1502 * this sleep isn't guaranteed to be long enough, resulting in
1503 * bad things like IRQ lines being left asserted during final
1504 * device removal. to deal with this we call reset just prior
1505 * to finalizing the device, which will put the device back into
1506 * an 'idle' state, as the device cleanup code expects.
1508 pci_device_reset(PCI_DEVICE(plugged_dev
));
1509 object_unparent(OBJECT(plugged_dev
));
1512 static void spapr_pci_unplug_request(HotplugHandler
*plug_handler
,
1513 DeviceState
*plugged_dev
, Error
**errp
)
1515 sPAPRPHBState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1516 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1517 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1519 if (!phb
->dr_enabled
) {
1520 error_setg(errp
, QERR_BUS_NO_HOTPLUG
,
1521 object_get_typename(OBJECT(phb
)));
1526 g_assert(drc
->dev
== plugged_dev
);
1528 if (!spapr_drc_unplug_requested(drc
)) {
1529 PCIBus
*bus
= PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
)));
1530 uint32_t slotnr
= PCI_SLOT(pdev
->devfn
);
1531 sPAPRDRConnector
*func_drc
;
1532 sPAPRDRConnectorClass
*func_drck
;
1533 sPAPRDREntitySense state
;
1536 /* ensure any other present functions are pending unplug */
1537 if (PCI_FUNC(pdev
->devfn
) == 0) {
1538 for (i
= 1; i
< 8; i
++) {
1539 func_drc
= spapr_phb_get_pci_func_drc(phb
, pci_bus_num(bus
),
1540 PCI_DEVFN(slotnr
, i
));
1541 func_drck
= SPAPR_DR_CONNECTOR_GET_CLASS(func_drc
);
1542 state
= func_drck
->dr_entity_sense(func_drc
);
1543 if (state
== SPAPR_DR_ENTITY_SENSE_PRESENT
1544 && !spapr_drc_unplug_requested(func_drc
)) {
1546 "PCI: slot %d, function %d still present. "
1547 "Must unplug all non-0 functions first.",
1554 spapr_drc_detach(drc
);
1556 /* if this isn't func 0, defer unplug event. otherwise signal removal
1557 * for all present functions
1559 if (PCI_FUNC(pdev
->devfn
) == 0) {
1560 for (i
= 7; i
>= 0; i
--) {
1561 func_drc
= spapr_phb_get_pci_func_drc(phb
, pci_bus_num(bus
),
1562 PCI_DEVFN(slotnr
, i
));
1563 func_drck
= SPAPR_DR_CONNECTOR_GET_CLASS(func_drc
);
1564 state
= func_drck
->dr_entity_sense(func_drc
);
1565 if (state
== SPAPR_DR_ENTITY_SENSE_PRESENT
) {
1566 spapr_hotplug_req_remove_by_index(func_drc
);
1573 static void spapr_phb_finalizefn(Object
*obj
)
1575 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(obj
);
1577 g_free(sphb
->dtbusname
);
1578 sphb
->dtbusname
= NULL
;
1581 static void spapr_phb_unrealize(DeviceState
*dev
, Error
**errp
)
1583 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
1584 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
1585 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
1586 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(phb
);
1587 sPAPRTCETable
*tcet
;
1589 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
1592 g_hash_table_unref(sphb
->msi
);
1597 * Remove IO/MMIO subregions and aliases, rest should get cleaned
1598 * via PHB's unrealize->object_finalize
1600 for (i
= windows_supported
- 1; i
>= 0; i
--) {
1601 tcet
= spapr_tce_find_by_liobn(sphb
->dma_liobn
[i
]);
1603 memory_region_del_subregion(&sphb
->iommu_root
,
1604 spapr_tce_get_iommu(tcet
));
1608 if (sphb
->dr_enabled
) {
1609 for (i
= PCI_SLOT_MAX
* 8 - 1; i
>= 0; i
--) {
1610 sPAPRDRConnector
*drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PCI
,
1611 (sphb
->index
<< 16) | i
);
1614 object_unparent(OBJECT(drc
));
1619 for (i
= PCI_NUM_PINS
- 1; i
>= 0; i
--) {
1620 if (sphb
->lsi_table
[i
].irq
) {
1621 spapr_irq_free(spapr
, sphb
->lsi_table
[i
].irq
, 1);
1622 sphb
->lsi_table
[i
].irq
= 0;
1626 QLIST_REMOVE(sphb
, list
);
1628 memory_region_del_subregion(&sphb
->iommu_root
, &sphb
->msiwindow
);
1630 address_space_destroy(&sphb
->iommu_as
);
1632 qbus_set_hotplug_handler(BUS(phb
->bus
), NULL
, &error_abort
);
1633 pci_unregister_root_bus(phb
->bus
);
1635 memory_region_del_subregion(get_system_memory(), &sphb
->iowindow
);
1636 if (sphb
->mem64_win_pciaddr
!= (hwaddr
)-1) {
1637 memory_region_del_subregion(get_system_memory(), &sphb
->mem64window
);
1639 memory_region_del_subregion(get_system_memory(), &sphb
->mem32window
);
1642 static void spapr_phb_realize(DeviceState
*dev
, Error
**errp
)
1644 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
1645 * tries to add a sPAPR PHB to a non-pseries machine.
1647 sPAPRMachineState
*spapr
=
1648 (sPAPRMachineState
*) object_dynamic_cast(qdev_get_machine(),
1649 TYPE_SPAPR_MACHINE
);
1650 sPAPRMachineClass
*smc
= spapr
? SPAPR_MACHINE_GET_CLASS(spapr
) : NULL
;
1651 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
1652 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(s
);
1653 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
1657 uint64_t msi_window_size
= 4096;
1658 sPAPRTCETable
*tcet
;
1659 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
1662 error_setg(errp
, TYPE_SPAPR_PCI_HOST_BRIDGE
" needs a pseries machine");
1666 assert(sphb
->index
!= (uint32_t)-1); /* checked in spapr_phb_pre_plug() */
1668 if (sphb
->mem64_win_size
!= 0) {
1669 if (sphb
->mem_win_size
> SPAPR_PCI_MEM32_WIN_SIZE
) {
1670 error_setg(errp
, "32-bit memory window of size 0x%"HWADDR_PRIx
1671 " (max 2 GiB)", sphb
->mem_win_size
);
1675 /* 64-bit window defaults to identity mapping */
1676 sphb
->mem64_win_pciaddr
= sphb
->mem64_win_addr
;
1677 } else if (sphb
->mem_win_size
> SPAPR_PCI_MEM32_WIN_SIZE
) {
1679 * For compatibility with old configuration, if no 64-bit MMIO
1680 * window is specified, but the ordinary (32-bit) memory
1681 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit
1682 * window, with a 64-bit MMIO window following on immediately
1685 sphb
->mem64_win_size
= sphb
->mem_win_size
- SPAPR_PCI_MEM32_WIN_SIZE
;
1686 sphb
->mem64_win_addr
= sphb
->mem_win_addr
+ SPAPR_PCI_MEM32_WIN_SIZE
;
1687 sphb
->mem64_win_pciaddr
=
1688 SPAPR_PCI_MEM_WIN_BUS_OFFSET
+ SPAPR_PCI_MEM32_WIN_SIZE
;
1689 sphb
->mem_win_size
= SPAPR_PCI_MEM32_WIN_SIZE
;
1692 if (spapr_pci_find_phb(spapr
, sphb
->buid
)) {
1693 error_setg(errp
, "PCI host bridges must have unique BUIDs");
1697 if (sphb
->numa_node
!= -1 &&
1698 (sphb
->numa_node
>= MAX_NODES
|| !numa_info
[sphb
->numa_node
].present
)) {
1699 error_setg(errp
, "Invalid NUMA node ID for PCI host bridge");
1703 sphb
->dtbusname
= g_strdup_printf("pci@%" PRIx64
, sphb
->buid
);
1705 /* Initialize memory regions */
1706 namebuf
= g_strdup_printf("%s.mmio", sphb
->dtbusname
);
1707 memory_region_init(&sphb
->memspace
, OBJECT(sphb
), namebuf
, UINT64_MAX
);
1710 namebuf
= g_strdup_printf("%s.mmio32-alias", sphb
->dtbusname
);
1711 memory_region_init_alias(&sphb
->mem32window
, OBJECT(sphb
),
1712 namebuf
, &sphb
->memspace
,
1713 SPAPR_PCI_MEM_WIN_BUS_OFFSET
, sphb
->mem_win_size
);
1715 memory_region_add_subregion(get_system_memory(), sphb
->mem_win_addr
,
1716 &sphb
->mem32window
);
1718 if (sphb
->mem64_win_size
!= 0) {
1719 namebuf
= g_strdup_printf("%s.mmio64-alias", sphb
->dtbusname
);
1720 memory_region_init_alias(&sphb
->mem64window
, OBJECT(sphb
),
1721 namebuf
, &sphb
->memspace
,
1722 sphb
->mem64_win_pciaddr
, sphb
->mem64_win_size
);
1725 memory_region_add_subregion(get_system_memory(),
1726 sphb
->mem64_win_addr
,
1727 &sphb
->mem64window
);
1730 /* Initialize IO regions */
1731 namebuf
= g_strdup_printf("%s.io", sphb
->dtbusname
);
1732 memory_region_init(&sphb
->iospace
, OBJECT(sphb
),
1733 namebuf
, SPAPR_PCI_IO_WIN_SIZE
);
1736 namebuf
= g_strdup_printf("%s.io-alias", sphb
->dtbusname
);
1737 memory_region_init_alias(&sphb
->iowindow
, OBJECT(sphb
), namebuf
,
1738 &sphb
->iospace
, 0, SPAPR_PCI_IO_WIN_SIZE
);
1740 memory_region_add_subregion(get_system_memory(), sphb
->io_win_addr
,
1743 bus
= pci_register_root_bus(dev
, NULL
,
1744 pci_spapr_set_irq
, pci_spapr_map_irq
, sphb
,
1745 &sphb
->memspace
, &sphb
->iospace
,
1746 PCI_DEVFN(0, 0), PCI_NUM_PINS
, TYPE_PCI_BUS
);
1748 qbus_set_hotplug_handler(BUS(phb
->bus
), OBJECT(sphb
), NULL
);
1751 * Initialize PHB address space.
1752 * By default there will be at least one subregion for default
1754 * Later the guest might want to create another DMA window
1755 * which will become another memory subregion.
1757 namebuf
= g_strdup_printf("%s.iommu-root", sphb
->dtbusname
);
1758 memory_region_init(&sphb
->iommu_root
, OBJECT(sphb
),
1759 namebuf
, UINT64_MAX
);
1761 address_space_init(&sphb
->iommu_as
, &sphb
->iommu_root
,
1765 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1766 * we need to allocate some memory to catch those writes coming
1767 * from msi_notify()/msix_notify().
1768 * As MSIMessage:addr is going to be the same and MSIMessage:data
1769 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1772 * For KVM we want to ensure that this memory is a full page so that
1773 * our memory slot is of page size granularity.
1776 if (kvm_enabled()) {
1777 msi_window_size
= getpagesize();
1781 memory_region_init_io(&sphb
->msiwindow
, OBJECT(sphb
), &spapr_msi_ops
, spapr
,
1782 "msi", msi_window_size
);
1783 memory_region_add_subregion(&sphb
->iommu_root
, SPAPR_PCI_MSI_WINDOW
,
1786 pci_setup_iommu(bus
, spapr_pci_dma_iommu
, sphb
);
1788 pci_bus_set_route_irq_fn(bus
, spapr_route_intx_pin_to_irq
);
1790 QLIST_INSERT_HEAD(&spapr
->phbs
, sphb
, list
);
1792 /* Initialize the LSI table */
1793 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
1794 uint32_t irq
= SPAPR_IRQ_PCI_LSI
+ sphb
->index
* PCI_NUM_PINS
+ i
;
1795 Error
*local_err
= NULL
;
1797 if (smc
->legacy_irq_allocation
) {
1798 irq
= spapr_irq_findone(spapr
, &local_err
);
1800 error_propagate_prepend(errp
, local_err
,
1801 "can't allocate LSIs: ");
1803 * Older machines will never support PHB hotplug, ie, this is an
1804 * init only path and QEMU will terminate. No need to rollback.
1810 spapr_irq_claim(spapr
, irq
, true, &local_err
);
1812 error_propagate_prepend(errp
, local_err
, "can't allocate LSIs: ");
1816 sphb
->lsi_table
[i
].irq
= irq
;
1819 /* allocate connectors for child PCI devices */
1820 if (sphb
->dr_enabled
) {
1821 for (i
= 0; i
< PCI_SLOT_MAX
* 8; i
++) {
1822 spapr_dr_connector_new(OBJECT(phb
), TYPE_SPAPR_DRC_PCI
,
1823 (sphb
->index
<< 16) | i
);
1828 for (i
= 0; i
< windows_supported
; ++i
) {
1829 tcet
= spapr_tce_new_table(DEVICE(sphb
), sphb
->dma_liobn
[i
]);
1831 error_setg(errp
, "Creating window#%d failed for %s",
1832 i
, sphb
->dtbusname
);
1835 memory_region_add_subregion(&sphb
->iommu_root
, 0,
1836 spapr_tce_get_iommu(tcet
));
1839 sphb
->msi
= g_hash_table_new_full(g_int_hash
, g_int_equal
, g_free
, g_free
);
1843 spapr_phb_unrealize(dev
, NULL
);
1846 static int spapr_phb_children_reset(Object
*child
, void *opaque
)
1848 DeviceState
*dev
= (DeviceState
*) object_dynamic_cast(child
, TYPE_DEVICE
);
1857 void spapr_phb_dma_reset(sPAPRPHBState
*sphb
)
1860 sPAPRTCETable
*tcet
;
1862 for (i
= 0; i
< SPAPR_PCI_DMA_MAX_WINDOWS
; ++i
) {
1863 tcet
= spapr_tce_find_by_liobn(sphb
->dma_liobn
[i
]);
1865 if (tcet
&& tcet
->nb_table
) {
1866 spapr_tce_table_disable(tcet
);
1870 /* Register default 32bit DMA window */
1871 tcet
= spapr_tce_find_by_liobn(sphb
->dma_liobn
[0]);
1872 spapr_tce_table_enable(tcet
, SPAPR_TCE_PAGE_SHIFT
, sphb
->dma_win_addr
,
1873 sphb
->dma_win_size
>> SPAPR_TCE_PAGE_SHIFT
);
1876 static void spapr_phb_reset(DeviceState
*qdev
)
1878 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(qdev
);
1880 spapr_phb_dma_reset(sphb
);
1882 /* Reset the IOMMU state */
1883 object_child_foreach(OBJECT(qdev
), spapr_phb_children_reset
, NULL
);
1885 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev
))) {
1886 spapr_phb_vfio_reset(qdev
);
1890 static Property spapr_phb_properties
[] = {
1891 DEFINE_PROP_UINT32("index", sPAPRPHBState
, index
, -1),
1892 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState
, mem_win_size
,
1893 SPAPR_PCI_MEM32_WIN_SIZE
),
1894 DEFINE_PROP_UINT64("mem64_win_size", sPAPRPHBState
, mem64_win_size
,
1895 SPAPR_PCI_MEM64_WIN_SIZE
),
1896 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState
, io_win_size
,
1897 SPAPR_PCI_IO_WIN_SIZE
),
1898 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState
, dr_enabled
,
1900 /* Default DMA window is 0..1GB */
1901 DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState
, dma_win_addr
, 0),
1902 DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState
, dma_win_size
, 0x40000000),
1903 DEFINE_PROP_UINT64("dma64_win_addr", sPAPRPHBState
, dma64_win_addr
,
1904 0x800000000000000ULL
),
1905 DEFINE_PROP_BOOL("ddw", sPAPRPHBState
, ddw_enabled
, true),
1906 DEFINE_PROP_UINT64("pgsz", sPAPRPHBState
, page_size_mask
,
1907 (1ULL << 12) | (1ULL << 16)),
1908 DEFINE_PROP_UINT32("numa_node", sPAPRPHBState
, numa_node
, -1),
1909 DEFINE_PROP_BOOL("pre-2.8-migration", sPAPRPHBState
,
1910 pre_2_8_migration
, false),
1911 DEFINE_PROP_BOOL("pcie-extended-configuration-space", sPAPRPHBState
,
1913 DEFINE_PROP_END_OF_LIST(),
1916 static const VMStateDescription vmstate_spapr_pci_lsi
= {
1917 .name
= "spapr_pci/lsi",
1919 .minimum_version_id
= 1,
1920 .fields
= (VMStateField
[]) {
1921 VMSTATE_UINT32_EQUAL(irq
, struct spapr_pci_lsi
, NULL
),
1923 VMSTATE_END_OF_LIST()
1927 static const VMStateDescription vmstate_spapr_pci_msi
= {
1928 .name
= "spapr_pci/msi",
1930 .minimum_version_id
= 1,
1931 .fields
= (VMStateField
[]) {
1932 VMSTATE_UINT32(key
, spapr_pci_msi_mig
),
1933 VMSTATE_UINT32(value
.first_irq
, spapr_pci_msi_mig
),
1934 VMSTATE_UINT32(value
.num
, spapr_pci_msi_mig
),
1935 VMSTATE_END_OF_LIST()
1939 static int spapr_pci_pre_save(void *opaque
)
1941 sPAPRPHBState
*sphb
= opaque
;
1942 GHashTableIter iter
;
1943 gpointer key
, value
;
1946 if (sphb
->pre_2_8_migration
) {
1947 sphb
->mig_liobn
= sphb
->dma_liobn
[0];
1948 sphb
->mig_mem_win_addr
= sphb
->mem_win_addr
;
1949 sphb
->mig_mem_win_size
= sphb
->mem_win_size
;
1950 sphb
->mig_io_win_addr
= sphb
->io_win_addr
;
1951 sphb
->mig_io_win_size
= sphb
->io_win_size
;
1953 if ((sphb
->mem64_win_size
!= 0)
1954 && (sphb
->mem64_win_addr
1955 == (sphb
->mem_win_addr
+ sphb
->mem_win_size
))) {
1956 sphb
->mig_mem_win_size
+= sphb
->mem64_win_size
;
1960 g_free(sphb
->msi_devs
);
1961 sphb
->msi_devs
= NULL
;
1962 sphb
->msi_devs_num
= g_hash_table_size(sphb
->msi
);
1963 if (!sphb
->msi_devs_num
) {
1966 sphb
->msi_devs
= g_new(spapr_pci_msi_mig
, sphb
->msi_devs_num
);
1968 g_hash_table_iter_init(&iter
, sphb
->msi
);
1969 for (i
= 0; g_hash_table_iter_next(&iter
, &key
, &value
); ++i
) {
1970 sphb
->msi_devs
[i
].key
= *(uint32_t *) key
;
1971 sphb
->msi_devs
[i
].value
= *(spapr_pci_msi
*) value
;
1977 static int spapr_pci_post_load(void *opaque
, int version_id
)
1979 sPAPRPHBState
*sphb
= opaque
;
1980 gpointer key
, value
;
1983 for (i
= 0; i
< sphb
->msi_devs_num
; ++i
) {
1984 key
= g_memdup(&sphb
->msi_devs
[i
].key
,
1985 sizeof(sphb
->msi_devs
[i
].key
));
1986 value
= g_memdup(&sphb
->msi_devs
[i
].value
,
1987 sizeof(sphb
->msi_devs
[i
].value
));
1988 g_hash_table_insert(sphb
->msi
, key
, value
);
1990 g_free(sphb
->msi_devs
);
1991 sphb
->msi_devs
= NULL
;
1992 sphb
->msi_devs_num
= 0;
1997 static bool pre_2_8_migration(void *opaque
, int version_id
)
1999 sPAPRPHBState
*sphb
= opaque
;
2001 return sphb
->pre_2_8_migration
;
2004 static const VMStateDescription vmstate_spapr_pci
= {
2005 .name
= "spapr_pci",
2007 .minimum_version_id
= 2,
2008 .pre_save
= spapr_pci_pre_save
,
2009 .post_load
= spapr_pci_post_load
,
2010 .fields
= (VMStateField
[]) {
2011 VMSTATE_UINT64_EQUAL(buid
, sPAPRPHBState
, NULL
),
2012 VMSTATE_UINT32_TEST(mig_liobn
, sPAPRPHBState
, pre_2_8_migration
),
2013 VMSTATE_UINT64_TEST(mig_mem_win_addr
, sPAPRPHBState
, pre_2_8_migration
),
2014 VMSTATE_UINT64_TEST(mig_mem_win_size
, sPAPRPHBState
, pre_2_8_migration
),
2015 VMSTATE_UINT64_TEST(mig_io_win_addr
, sPAPRPHBState
, pre_2_8_migration
),
2016 VMSTATE_UINT64_TEST(mig_io_win_size
, sPAPRPHBState
, pre_2_8_migration
),
2017 VMSTATE_STRUCT_ARRAY(lsi_table
, sPAPRPHBState
, PCI_NUM_PINS
, 0,
2018 vmstate_spapr_pci_lsi
, struct spapr_pci_lsi
),
2019 VMSTATE_INT32(msi_devs_num
, sPAPRPHBState
),
2020 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs
, sPAPRPHBState
, msi_devs_num
, 0,
2021 vmstate_spapr_pci_msi
, spapr_pci_msi_mig
),
2022 VMSTATE_END_OF_LIST()
2026 static const char *spapr_phb_root_bus_path(PCIHostState
*host_bridge
,
2029 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(host_bridge
);
2031 return sphb
->dtbusname
;
2034 static void spapr_phb_class_init(ObjectClass
*klass
, void *data
)
2036 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_CLASS(klass
);
2037 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2038 HotplugHandlerClass
*hp
= HOTPLUG_HANDLER_CLASS(klass
);
2040 hc
->root_bus_path
= spapr_phb_root_bus_path
;
2041 dc
->realize
= spapr_phb_realize
;
2042 dc
->unrealize
= spapr_phb_unrealize
;
2043 dc
->props
= spapr_phb_properties
;
2044 dc
->reset
= spapr_phb_reset
;
2045 dc
->vmsd
= &vmstate_spapr_pci
;
2046 /* Supported by TYPE_SPAPR_MACHINE */
2047 dc
->user_creatable
= true;
2048 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
2049 hp
->plug
= spapr_pci_plug
;
2050 hp
->unplug
= spapr_pci_unplug
;
2051 hp
->unplug_request
= spapr_pci_unplug_request
;
2054 static const TypeInfo spapr_phb_info
= {
2055 .name
= TYPE_SPAPR_PCI_HOST_BRIDGE
,
2056 .parent
= TYPE_PCI_HOST_BRIDGE
,
2057 .instance_size
= sizeof(sPAPRPHBState
),
2058 .instance_finalize
= spapr_phb_finalizefn
,
2059 .class_init
= spapr_phb_class_init
,
2060 .interfaces
= (InterfaceInfo
[]) {
2061 { TYPE_HOTPLUG_HANDLER
},
2066 typedef struct sPAPRFDT
{
2069 sPAPRPHBState
*sphb
;
2072 static void spapr_populate_pci_devices_dt(PCIBus
*bus
, PCIDevice
*pdev
,
2076 sPAPRFDT
*p
= opaque
;
2080 offset
= spapr_create_pci_child_dt(p
->sphb
, pdev
, p
->fdt
, p
->node_off
);
2082 error_report("Failed to create pci child device tree node");
2086 if ((pci_default_read_config(pdev
, PCI_HEADER_TYPE
, 1) !=
2087 PCI_HEADER_TYPE_BRIDGE
)) {
2091 sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
2097 s_fdt
.node_off
= offset
;
2098 s_fdt
.sphb
= p
->sphb
;
2099 pci_for_each_device_reverse(sec_bus
, pci_bus_num(sec_bus
),
2100 spapr_populate_pci_devices_dt
,
2104 static void spapr_phb_pci_enumerate_bridge(PCIBus
*bus
, PCIDevice
*pdev
,
2107 unsigned int *bus_no
= opaque
;
2108 PCIBus
*sec_bus
= NULL
;
2110 if ((pci_default_read_config(pdev
, PCI_HEADER_TYPE
, 1) !=
2111 PCI_HEADER_TYPE_BRIDGE
)) {
2116 pci_default_write_config(pdev
, PCI_PRIMARY_BUS
, pci_dev_bus_num(pdev
), 1);
2117 pci_default_write_config(pdev
, PCI_SECONDARY_BUS
, *bus_no
, 1);
2118 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, *bus_no
, 1);
2120 sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
2125 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
2126 spapr_phb_pci_enumerate_bridge
, bus_no
);
2127 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, *bus_no
, 1);
2130 static void spapr_phb_pci_enumerate(sPAPRPHBState
*phb
)
2132 PCIBus
*bus
= PCI_HOST_BRIDGE(phb
)->bus
;
2133 unsigned int bus_no
= 0;
2135 pci_for_each_device(bus
, pci_bus_num(bus
),
2136 spapr_phb_pci_enumerate_bridge
,
2141 int spapr_populate_pci_dt(sPAPRPHBState
*phb
, uint32_t intc_phandle
, void *fdt
,
2142 uint32_t nr_msis
, int *node_offset
)
2144 int bus_off
, i
, j
, ret
;
2146 uint32_t bus_range
[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2152 } QEMU_PACKED ranges
[] = {
2154 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2155 cpu_to_be64(phb
->io_win_addr
),
2156 cpu_to_be64(memory_region_size(&phb
->iospace
)),
2159 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET
),
2160 cpu_to_be64(phb
->mem_win_addr
),
2161 cpu_to_be64(phb
->mem_win_size
),
2164 cpu_to_be32(b_ss(3)), cpu_to_be64(phb
->mem64_win_pciaddr
),
2165 cpu_to_be64(phb
->mem64_win_addr
),
2166 cpu_to_be64(phb
->mem64_win_size
),
2169 const unsigned sizeof_ranges
=
2170 (phb
->mem64_win_size
? 3 : 2) * sizeof(ranges
[0]);
2171 uint64_t bus_reg
[] = { cpu_to_be64(phb
->buid
), 0 };
2172 uint32_t interrupt_map_mask
[] = {
2173 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2174 uint32_t interrupt_map
[PCI_SLOT_MAX
* PCI_NUM_PINS
][7];
2175 uint32_t ddw_applicable
[] = {
2176 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW
),
2177 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW
),
2178 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW
)
2180 uint32_t ddw_extensions
[] = {
2182 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW
)
2184 uint32_t associativity
[] = {cpu_to_be32(0x4),
2188 cpu_to_be32(phb
->numa_node
)};
2189 sPAPRTCETable
*tcet
;
2190 PCIBus
*bus
= PCI_HOST_BRIDGE(phb
)->bus
;
2192 sPAPRDRConnector
*drc
;
2194 /* Start populating the FDT */
2195 nodename
= g_strdup_printf("pci@%" PRIx64
, phb
->buid
);
2196 _FDT(bus_off
= fdt_add_subnode(fdt
, 0, nodename
));
2199 *node_offset
= bus_off
;
2202 /* Write PHB properties */
2203 _FDT(fdt_setprop_string(fdt
, bus_off
, "device_type", "pci"));
2204 _FDT(fdt_setprop_string(fdt
, bus_off
, "compatible", "IBM,Logical_PHB"));
2205 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#address-cells", 0x3));
2206 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#size-cells", 0x2));
2207 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#interrupt-cells", 0x1));
2208 _FDT(fdt_setprop(fdt
, bus_off
, "used-by-rtas", NULL
, 0));
2209 _FDT(fdt_setprop(fdt
, bus_off
, "bus-range", &bus_range
, sizeof(bus_range
)));
2210 _FDT(fdt_setprop(fdt
, bus_off
, "ranges", &ranges
, sizeof_ranges
));
2211 _FDT(fdt_setprop(fdt
, bus_off
, "reg", &bus_reg
, sizeof(bus_reg
)));
2212 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pci-config-space-type", 0x1));
2213 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pe-total-#msi", nr_msis
));
2215 /* Dynamic DMA window */
2216 if (phb
->ddw_enabled
) {
2217 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,ddw-applicable", &ddw_applicable
,
2218 sizeof(ddw_applicable
)));
2219 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,ddw-extensions",
2220 &ddw_extensions
, sizeof(ddw_extensions
)));
2223 /* Advertise NUMA via ibm,associativity */
2224 if (phb
->numa_node
!= -1) {
2225 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,associativity", associativity
,
2226 sizeof(associativity
)));
2229 /* Build the interrupt-map, this must matches what is done
2230 * in pci_spapr_map_irq
2232 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map-mask",
2233 &interrupt_map_mask
, sizeof(interrupt_map_mask
)));
2234 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
2235 for (j
= 0; j
< PCI_NUM_PINS
; j
++) {
2236 uint32_t *irqmap
= interrupt_map
[i
*PCI_NUM_PINS
+ j
];
2237 int lsi_num
= pci_spapr_swizzle(i
, j
);
2239 irqmap
[0] = cpu_to_be32(b_ddddd(i
)|b_fff(0));
2242 irqmap
[3] = cpu_to_be32(j
+1);
2243 irqmap
[4] = cpu_to_be32(intc_phandle
);
2244 spapr_dt_irq(&irqmap
[5], phb
->lsi_table
[lsi_num
].irq
, true);
2247 /* Write interrupt map */
2248 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map", &interrupt_map
,
2249 sizeof(interrupt_map
)));
2251 tcet
= spapr_tce_find_by_liobn(phb
->dma_liobn
[0]);
2255 spapr_dma_dt(fdt
, bus_off
, "ibm,dma-window",
2256 tcet
->liobn
, tcet
->bus_offset
,
2257 tcet
->nb_table
<< tcet
->page_shift
);
2259 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, phb
->index
);
2261 uint32_t drc_index
= cpu_to_be32(spapr_drc_index(drc
));
2263 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,my-drc-index", &drc_index
,
2264 sizeof(drc_index
)));
2267 /* Walk the bridges and program the bus numbers*/
2268 spapr_phb_pci_enumerate(phb
);
2269 _FDT(fdt_setprop_cell(fdt
, bus_off
, "qemu,phb-enumerated", 0x1));
2271 /* Populate tree nodes with PCI devices attached */
2273 s_fdt
.node_off
= bus_off
;
2275 pci_for_each_device_reverse(bus
, pci_bus_num(bus
),
2276 spapr_populate_pci_devices_dt
,
2279 ret
= spapr_drc_populate_dt(fdt
, bus_off
, OBJECT(phb
),
2280 SPAPR_DR_CONNECTOR_TYPE_PCI
);
2288 void spapr_pci_rtas_init(void)
2290 spapr_rtas_register(RTAS_READ_PCI_CONFIG
, "read-pci-config",
2291 rtas_read_pci_config
);
2292 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG
, "write-pci-config",
2293 rtas_write_pci_config
);
2294 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG
, "ibm,read-pci-config",
2295 rtas_ibm_read_pci_config
);
2296 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG
, "ibm,write-pci-config",
2297 rtas_ibm_write_pci_config
);
2298 if (msi_nonbroken
) {
2299 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER
,
2300 "ibm,query-interrupt-source-number",
2301 rtas_ibm_query_interrupt_source_number
);
2302 spapr_rtas_register(RTAS_IBM_CHANGE_MSI
, "ibm,change-msi",
2303 rtas_ibm_change_msi
);
2306 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION
,
2307 "ibm,set-eeh-option",
2308 rtas_ibm_set_eeh_option
);
2309 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2
,
2310 "ibm,get-config-addr-info2",
2311 rtas_ibm_get_config_addr_info2
);
2312 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2
,
2313 "ibm,read-slot-reset-state2",
2314 rtas_ibm_read_slot_reset_state2
);
2315 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET
,
2316 "ibm,set-slot-reset",
2317 rtas_ibm_set_slot_reset
);
2318 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE
,
2320 rtas_ibm_configure_pe
);
2321 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL
,
2322 "ibm,slot-error-detail",
2323 rtas_ibm_slot_error_detail
);
2326 static void spapr_pci_register_types(void)
2328 type_register_static(&spapr_phb_info
);
2331 type_init(spapr_pci_register_types
)
2333 static int spapr_switch_one_vga(DeviceState
*dev
, void *opaque
)
2335 bool be
= *(bool *)opaque
;
2337 if (object_dynamic_cast(OBJECT(dev
), "VGA")
2338 || object_dynamic_cast(OBJECT(dev
), "secondary-vga")) {
2339 object_property_set_bool(OBJECT(dev
), be
, "big-endian-framebuffer",
2345 void spapr_pci_switch_vga(bool big_endian
)
2347 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
2348 sPAPRPHBState
*sphb
;
2351 * For backward compatibility with existing guests, we switch
2352 * the endianness of the VGA controller when changing the guest
2355 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
2356 BusState
*bus
= &PCI_HOST_BRIDGE(sphb
)->bus
->qbus
;
2357 qbus_walk_children(bus
, spapr_switch_one_vga
, NULL
, NULL
, NULL
,