2 * QEMU sPAPR PCI host originated from Uninorth PCI host
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/sysbus.h"
27 #include "hw/pci/pci.h"
28 #include "hw/pci/msi.h"
29 #include "hw/pci/msix.h"
30 #include "hw/pci/pci_host.h"
31 #include "hw/ppc/spapr.h"
32 #include "hw/pci-host/spapr.h"
33 #include "exec/address-spaces.h"
36 #include "qemu/error-report.h"
37 #include "qapi/qmp/qerror.h"
39 #include "hw/pci/pci_bridge.h"
40 #include "hw/pci/pci_bus.h"
41 #include "hw/ppc/spapr_drc.h"
42 #include "sysemu/device_tree.h"
44 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
45 #define RTAS_QUERY_FN 0
46 #define RTAS_CHANGE_FN 1
47 #define RTAS_RESET_FN 2
48 #define RTAS_CHANGE_MSI_FN 3
49 #define RTAS_CHANGE_MSIX_FN 4
51 /* Interrupt types to return on RTAS_CHANGE_* */
52 #define RTAS_TYPE_MSI 1
53 #define RTAS_TYPE_MSIX 2
55 #define FDT_NAME_MAX 128
65 sPAPRPHBState
*spapr_pci_find_phb(sPAPRMachineState
*spapr
, uint64_t buid
)
69 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
70 if (sphb
->buid
!= buid
) {
79 PCIDevice
*spapr_pci_find_dev(sPAPRMachineState
*spapr
, uint64_t buid
,
82 sPAPRPHBState
*sphb
= spapr_pci_find_phb(spapr
, buid
);
83 PCIHostState
*phb
= PCI_HOST_BRIDGE(sphb
);
84 int bus_num
= (config_addr
>> 16) & 0xFF;
85 int devfn
= (config_addr
>> 8) & 0xFF;
91 return pci_find_device(phb
->bus
, bus_num
, devfn
);
94 static uint32_t rtas_pci_cfgaddr(uint32_t arg
)
96 /* This handles the encoding of extended config space addresses */
97 return ((arg
>> 20) & 0xf00) | (arg
& 0xff);
100 static void finish_read_pci_config(sPAPRMachineState
*spapr
, uint64_t buid
,
101 uint32_t addr
, uint32_t size
,
107 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
108 /* access must be 1, 2 or 4 bytes */
109 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
113 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
114 addr
= rtas_pci_cfgaddr(addr
);
116 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
117 /* Access must be to a valid device, within bounds and
118 * naturally aligned */
119 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
123 val
= pci_host_config_read_common(pci_dev
, addr
,
124 pci_config_size(pci_dev
), size
);
126 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
127 rtas_st(rets
, 1, val
);
130 static void rtas_ibm_read_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
131 uint32_t token
, uint32_t nargs
,
133 uint32_t nret
, target_ulong rets
)
138 if ((nargs
!= 4) || (nret
!= 2)) {
139 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
143 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
144 size
= rtas_ld(args
, 3);
145 addr
= rtas_ld(args
, 0);
147 finish_read_pci_config(spapr
, buid
, addr
, size
, rets
);
150 static void rtas_read_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
151 uint32_t token
, uint32_t nargs
,
153 uint32_t nret
, target_ulong rets
)
157 if ((nargs
!= 2) || (nret
!= 2)) {
158 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
162 size
= rtas_ld(args
, 1);
163 addr
= rtas_ld(args
, 0);
165 finish_read_pci_config(spapr
, 0, addr
, size
, rets
);
168 static void finish_write_pci_config(sPAPRMachineState
*spapr
, uint64_t buid
,
169 uint32_t addr
, uint32_t size
,
170 uint32_t val
, target_ulong rets
)
174 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
175 /* access must be 1, 2 or 4 bytes */
176 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
180 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
181 addr
= rtas_pci_cfgaddr(addr
);
183 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
184 /* Access must be to a valid device, within bounds and
185 * naturally aligned */
186 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
190 pci_host_config_write_common(pci_dev
, addr
, pci_config_size(pci_dev
),
193 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
196 static void rtas_ibm_write_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
197 uint32_t token
, uint32_t nargs
,
199 uint32_t nret
, target_ulong rets
)
202 uint32_t val
, size
, addr
;
204 if ((nargs
!= 5) || (nret
!= 1)) {
205 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
209 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
210 val
= rtas_ld(args
, 4);
211 size
= rtas_ld(args
, 3);
212 addr
= rtas_ld(args
, 0);
214 finish_write_pci_config(spapr
, buid
, addr
, size
, val
, rets
);
217 static void rtas_write_pci_config(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
218 uint32_t token
, uint32_t nargs
,
220 uint32_t nret
, target_ulong rets
)
222 uint32_t val
, size
, addr
;
224 if ((nargs
!= 3) || (nret
!= 1)) {
225 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
230 val
= rtas_ld(args
, 2);
231 size
= rtas_ld(args
, 1);
232 addr
= rtas_ld(args
, 0);
234 finish_write_pci_config(spapr
, 0, addr
, size
, val
, rets
);
238 * Set MSI/MSIX message data.
239 * This is required for msi_notify()/msix_notify() which
240 * will write at the addresses via spapr_msi_write().
242 * If hwaddr == 0, all entries will have .data == first_irq i.e.
243 * table will be reset.
245 static void spapr_msi_setmsg(PCIDevice
*pdev
, hwaddr addr
, bool msix
,
246 unsigned first_irq
, unsigned req_num
)
249 MSIMessage msg
= { .address
= addr
, .data
= first_irq
};
252 msi_set_message(pdev
, msg
);
253 trace_spapr_pci_msi_setup(pdev
->name
, 0, msg
.address
);
257 for (i
= 0; i
< req_num
; ++i
) {
258 msix_set_message(pdev
, i
, msg
);
259 trace_spapr_pci_msi_setup(pdev
->name
, i
, msg
.address
);
266 static void rtas_ibm_change_msi(PowerPCCPU
*cpu
, sPAPRMachineState
*spapr
,
267 uint32_t token
, uint32_t nargs
,
268 target_ulong args
, uint32_t nret
,
271 uint32_t config_addr
= rtas_ld(args
, 0);
272 uint64_t buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
273 unsigned int func
= rtas_ld(args
, 3);
274 unsigned int req_num
= rtas_ld(args
, 4); /* 0 == remove all */
275 unsigned int seq_num
= rtas_ld(args
, 5);
276 unsigned int ret_intr_type
;
277 unsigned int irq
, max_irqs
= 0, num
= 0;
278 sPAPRPHBState
*phb
= NULL
;
279 PCIDevice
*pdev
= NULL
;
281 int *config_addr_key
;
284 case RTAS_CHANGE_MSI_FN
:
286 ret_intr_type
= RTAS_TYPE_MSI
;
288 case RTAS_CHANGE_MSIX_FN
:
289 ret_intr_type
= RTAS_TYPE_MSIX
;
292 error_report("rtas_ibm_change_msi(%u) is not implemented", func
);
293 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
297 /* Fins sPAPRPHBState */
298 phb
= spapr_pci_find_phb(spapr
, buid
);
300 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
303 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
309 msi
= (spapr_pci_msi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
311 trace_spapr_pci_msi("Releasing wrong config", config_addr
);
312 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
316 xics_free(spapr
->icp
, msi
->first_irq
, msi
->num
);
317 if (msi_present(pdev
)) {
318 spapr_msi_setmsg(pdev
, 0, false, 0, num
);
320 if (msix_present(pdev
)) {
321 spapr_msi_setmsg(pdev
, 0, true, 0, num
);
323 g_hash_table_remove(phb
->msi
, &config_addr
);
325 trace_spapr_pci_msi("Released MSIs", config_addr
);
326 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
333 /* Check if the device supports as many IRQs as requested */
334 if (ret_intr_type
== RTAS_TYPE_MSI
) {
335 max_irqs
= msi_nr_vectors_allocated(pdev
);
336 } else if (ret_intr_type
== RTAS_TYPE_MSIX
) {
337 max_irqs
= pdev
->msix_entries_nr
;
340 error_report("Requested interrupt type %d is not enabled for device %x",
341 ret_intr_type
, config_addr
);
342 rtas_st(rets
, 0, -1); /* Hardware error */
345 /* Correct the number if the guest asked for too many */
346 if (req_num
> max_irqs
) {
347 trace_spapr_pci_msi_retry(config_addr
, req_num
, max_irqs
);
349 irq
= 0; /* to avoid misleading trace */
354 irq
= xics_alloc_block(spapr
->icp
, 0, req_num
, false,
355 ret_intr_type
== RTAS_TYPE_MSI
);
357 error_report("Cannot allocate MSIs for device %x", config_addr
);
358 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
362 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
363 spapr_msi_setmsg(pdev
, SPAPR_PCI_MSI_WINDOW
, ret_intr_type
== RTAS_TYPE_MSIX
,
366 /* Add MSI device to cache */
367 msi
= g_new(spapr_pci_msi
, 1);
368 msi
->first_irq
= irq
;
370 config_addr_key
= g_new(int, 1);
371 *config_addr_key
= config_addr
;
372 g_hash_table_insert(phb
->msi
, config_addr_key
, msi
);
375 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
376 rtas_st(rets
, 1, req_num
);
377 rtas_st(rets
, 2, ++seq_num
);
378 rtas_st(rets
, 3, ret_intr_type
);
380 trace_spapr_pci_rtas_ibm_change_msi(config_addr
, func
, req_num
, irq
);
383 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU
*cpu
,
384 sPAPRMachineState
*spapr
,
391 uint32_t config_addr
= rtas_ld(args
, 0);
392 uint64_t buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
393 unsigned int intr_src_num
= -1, ioa_intr_num
= rtas_ld(args
, 3);
394 sPAPRPHBState
*phb
= NULL
;
395 PCIDevice
*pdev
= NULL
;
398 /* Find sPAPRPHBState */
399 phb
= spapr_pci_find_phb(spapr
, buid
);
401 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
404 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
408 /* Find device descriptor and start IRQ */
409 msi
= (spapr_pci_msi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
410 if (!msi
|| !msi
->first_irq
|| !msi
->num
|| (ioa_intr_num
>= msi
->num
)) {
411 trace_spapr_pci_msi("Failed to return vector", config_addr
);
412 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
415 intr_src_num
= msi
->first_irq
+ ioa_intr_num
;
416 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num
,
419 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
420 rtas_st(rets
, 1, intr_src_num
);
421 rtas_st(rets
, 2, 1);/* 0 == level; 1 == edge */
424 static void rtas_ibm_set_eeh_option(PowerPCCPU
*cpu
,
425 sPAPRMachineState
*spapr
,
426 uint32_t token
, uint32_t nargs
,
427 target_ulong args
, uint32_t nret
,
432 uint32_t addr
, option
;
436 if ((nargs
!= 4) || (nret
!= 1)) {
437 goto param_error_exit
;
440 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
441 addr
= rtas_ld(args
, 0);
442 option
= rtas_ld(args
, 3);
444 sphb
= spapr_pci_find_phb(spapr
, buid
);
446 goto param_error_exit
;
449 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
450 if (!spc
->eeh_set_option
) {
451 goto param_error_exit
;
454 ret
= spc
->eeh_set_option(sphb
, addr
, option
);
455 rtas_st(rets
, 0, ret
);
459 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
462 static void rtas_ibm_get_config_addr_info2(PowerPCCPU
*cpu
,
463 sPAPRMachineState
*spapr
,
464 uint32_t token
, uint32_t nargs
,
465 target_ulong args
, uint32_t nret
,
471 uint32_t addr
, option
;
474 if ((nargs
!= 4) || (nret
!= 2)) {
475 goto param_error_exit
;
478 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
479 sphb
= spapr_pci_find_phb(spapr
, buid
);
481 goto param_error_exit
;
484 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
485 if (!spc
->eeh_set_option
) {
486 goto param_error_exit
;
490 * We always have PE address of form "00BB0001". "BB"
491 * represents the bus number of PE's primary bus.
493 option
= rtas_ld(args
, 3);
495 case RTAS_GET_PE_ADDR
:
496 addr
= rtas_ld(args
, 0);
497 pdev
= spapr_pci_find_dev(spapr
, buid
, addr
);
499 goto param_error_exit
;
502 rtas_st(rets
, 1, (pci_bus_num(pdev
->bus
) << 16) + 1);
504 case RTAS_GET_PE_MODE
:
505 rtas_st(rets
, 1, RTAS_PE_MODE_SHARED
);
508 goto param_error_exit
;
511 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
515 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
518 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU
*cpu
,
519 sPAPRMachineState
*spapr
,
520 uint32_t token
, uint32_t nargs
,
521 target_ulong args
, uint32_t nret
,
529 if ((nargs
!= 3) || (nret
!= 4 && nret
!= 5)) {
530 goto param_error_exit
;
533 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
534 sphb
= spapr_pci_find_phb(spapr
, buid
);
536 goto param_error_exit
;
539 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
540 if (!spc
->eeh_get_state
) {
541 goto param_error_exit
;
544 ret
= spc
->eeh_get_state(sphb
, &state
);
545 rtas_st(rets
, 0, ret
);
546 if (ret
!= RTAS_OUT_SUCCESS
) {
550 rtas_st(rets
, 1, state
);
551 rtas_st(rets
, 2, RTAS_EEH_SUPPORT
);
552 rtas_st(rets
, 3, RTAS_EEH_PE_UNAVAIL_INFO
);
554 rtas_st(rets
, 4, RTAS_EEH_PE_RECOVER_INFO
);
559 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
562 static void rtas_ibm_set_slot_reset(PowerPCCPU
*cpu
,
563 sPAPRMachineState
*spapr
,
564 uint32_t token
, uint32_t nargs
,
565 target_ulong args
, uint32_t nret
,
574 if ((nargs
!= 4) || (nret
!= 1)) {
575 goto param_error_exit
;
578 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
579 option
= rtas_ld(args
, 3);
580 sphb
= spapr_pci_find_phb(spapr
, buid
);
582 goto param_error_exit
;
585 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
586 if (!spc
->eeh_reset
) {
587 goto param_error_exit
;
590 ret
= spc
->eeh_reset(sphb
, option
);
591 rtas_st(rets
, 0, ret
);
595 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
598 static void rtas_ibm_configure_pe(PowerPCCPU
*cpu
,
599 sPAPRMachineState
*spapr
,
600 uint32_t token
, uint32_t nargs
,
601 target_ulong args
, uint32_t nret
,
609 if ((nargs
!= 3) || (nret
!= 1)) {
610 goto param_error_exit
;
613 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
614 sphb
= spapr_pci_find_phb(spapr
, buid
);
616 goto param_error_exit
;
619 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
620 if (!spc
->eeh_configure
) {
621 goto param_error_exit
;
624 ret
= spc
->eeh_configure(sphb
);
625 rtas_st(rets
, 0, ret
);
629 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
632 /* To support it later */
633 static void rtas_ibm_slot_error_detail(PowerPCCPU
*cpu
,
634 sPAPRMachineState
*spapr
,
635 uint32_t token
, uint32_t nargs
,
636 target_ulong args
, uint32_t nret
,
644 if ((nargs
!= 8) || (nret
!= 1)) {
645 goto param_error_exit
;
648 buid
= ((uint64_t)rtas_ld(args
, 1) << 32) | rtas_ld(args
, 2);
649 sphb
= spapr_pci_find_phb(spapr
, buid
);
651 goto param_error_exit
;
654 spc
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb
);
655 if (!spc
->eeh_set_option
) {
656 goto param_error_exit
;
659 option
= rtas_ld(args
, 7);
661 case RTAS_SLOT_TEMP_ERR_LOG
:
662 case RTAS_SLOT_PERM_ERR_LOG
:
665 goto param_error_exit
;
668 /* We don't have error log yet */
669 rtas_st(rets
, 0, RTAS_OUT_NO_ERRORS_FOUND
);
673 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
676 static int pci_spapr_swizzle(int slot
, int pin
)
678 return (slot
+ pin
) % PCI_NUM_PINS
;
681 static int pci_spapr_map_irq(PCIDevice
*pci_dev
, int irq_num
)
684 * Here we need to convert pci_dev + irq_num to some unique value
685 * which is less than number of IRQs on the specific bus (4). We
686 * use standard PCI swizzling, that is (slot number + pin number)
689 return pci_spapr_swizzle(PCI_SLOT(pci_dev
->devfn
), irq_num
);
692 static void pci_spapr_set_irq(void *opaque
, int irq_num
, int level
)
695 * Here we use the number returned by pci_spapr_map_irq to find a
696 * corresponding qemu_irq.
698 sPAPRPHBState
*phb
= opaque
;
700 trace_spapr_pci_lsi_set(phb
->dtbusname
, irq_num
, phb
->lsi_table
[irq_num
].irq
);
701 qemu_set_irq(spapr_phb_lsi_qirq(phb
, irq_num
), level
);
704 static PCIINTxRoute
spapr_route_intx_pin_to_irq(void *opaque
, int pin
)
706 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(opaque
);
709 route
.mode
= PCI_INTX_ENABLED
;
710 route
.irq
= sphb
->lsi_table
[pin
].irq
;
716 * MSI/MSIX memory region implementation.
717 * The handler handles both MSI and MSIX.
718 * For MSI-X, the vector number is encoded as a part of the address,
720 * For MSI, the vector number is encoded in least bits in data.
722 static void spapr_msi_write(void *opaque
, hwaddr addr
,
723 uint64_t data
, unsigned size
)
725 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
728 trace_spapr_pci_msi_write(addr
, data
, irq
);
730 qemu_irq_pulse(xics_get_qirq(spapr
->icp
, irq
));
733 static const MemoryRegionOps spapr_msi_ops
= {
734 /* There is no .read as the read result is undefined by PCI spec */
736 .write
= spapr_msi_write
,
737 .endianness
= DEVICE_LITTLE_ENDIAN
743 static AddressSpace
*spapr_pci_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
745 sPAPRPHBState
*phb
= opaque
;
747 return &phb
->iommu_as
;
750 static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState
*sphb
, PCIDevice
*pdev
)
752 char *path
= NULL
, *buf
= NULL
, *host
= NULL
;
754 /* Get the PCI VFIO host id */
755 host
= object_property_get_str(OBJECT(pdev
), "host", NULL
);
760 /* Construct the path of the file that will give us the DT location */
761 path
= g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host
);
763 if (!path
|| !g_file_get_contents(path
, &buf
, NULL
, NULL
)) {
768 /* Construct and read from host device tree the loc-code */
769 path
= g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf
);
771 if (!path
|| !g_file_get_contents(path
, &buf
, NULL
, NULL
)) {
781 static char *spapr_phb_get_loc_code(sPAPRPHBState
*sphb
, PCIDevice
*pdev
)
784 const char *devtype
= "qemu";
785 uint32_t busnr
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
))));
787 if (object_dynamic_cast(OBJECT(pdev
), "vfio-pci")) {
788 buf
= spapr_phb_vfio_get_loc_code(sphb
, pdev
);
795 * For emulated devices and VFIO-failure case, make up
798 buf
= g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
799 devtype
, pdev
->name
, sphb
->index
, busnr
,
800 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
));
804 /* Macros to operate with address in OF binding to PCI */
805 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
806 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
807 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
808 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
809 #define b_ss(x) b_x((x), 24, 2) /* the space code */
810 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
811 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
812 #define b_fff(x) b_x((x), 8, 3) /* function number */
813 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
815 /* for 'reg'/'assigned-addresses' OF properties */
816 #define RESOURCE_CELLS_SIZE 2
817 #define RESOURCE_CELLS_ADDRESS 3
819 typedef struct ResourceFields
{
825 } QEMU_PACKED ResourceFields
;
827 typedef struct ResourceProps
{
828 ResourceFields reg
[8];
829 ResourceFields assigned
[7];
831 uint32_t assigned_len
;
834 /* fill in the 'reg'/'assigned-resources' OF properties for
835 * a PCI device. 'reg' describes resource requirements for a
836 * device's IO/MEM regions, 'assigned-addresses' describes the
837 * actual resource assignments.
839 * the properties are arrays of ('phys-addr', 'size') pairs describing
840 * the addressable regions of the PCI device, where 'phys-addr' is a
841 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
842 * (phys.hi, phys.mid, phys.lo), and 'size' is a
843 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
845 * phys.hi = 0xYYXXXXZZ, where:
850 * ||| + 00 if configuration space
851 * ||| + 01 if IO region,
852 * ||| + 10 if 32-bit MEM region
853 * ||| + 11 if 64-bit MEM region
855 * ||+------ for non-relocatable IO: 1 if aliased
856 * || for relocatable IO: 1 if below 64KB
857 * || for MEM: 1 if below 1MB
858 * |+------- 1 if region is prefetchable
859 * +-------- 1 if region is non-relocatable
860 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
862 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding
865 * phys.mid and phys.lo correspond respectively to the hi/lo portions
866 * of the actual address of the region.
868 * how the phys-addr/size values are used differ slightly between
869 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has
870 * an additional description for the config space region of the
871 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0
872 * to describe the region as relocatable, with an address-mapping
873 * that corresponds directly to the PHB's address space for the
874 * resource. 'assigned-addresses' always has n=1 set with an absolute
875 * address assigned for the resource. in general, 'assigned-addresses'
876 * won't be populated, since addresses for PCI devices are generally
877 * unmapped initially and left to the guest to assign.
879 * note also that addresses defined in these properties are, at least
880 * for PAPR guests, relative to the PHBs IO/MEM windows, and
881 * correspond directly to the addresses in the BARs.
883 * in accordance with PCI Bus Binding to Open Firmware,
884 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
887 static void populate_resource_props(PCIDevice
*d
, ResourceProps
*rp
)
889 int bus_num
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d
))));
890 uint32_t dev_id
= (b_bbbbbbbb(bus_num
) |
891 b_ddddd(PCI_SLOT(d
->devfn
)) |
892 b_fff(PCI_FUNC(d
->devfn
)));
893 ResourceFields
*reg
, *assigned
;
894 int i
, reg_idx
= 0, assigned_idx
= 0;
896 /* config space region */
897 reg
= &rp
->reg
[reg_idx
++];
898 reg
->phys_hi
= cpu_to_be32(dev_id
);
904 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
905 if (!d
->io_regions
[i
].size
) {
909 reg
= &rp
->reg
[reg_idx
++];
911 reg
->phys_hi
= cpu_to_be32(dev_id
| b_rrrrrrrr(pci_bar(d
, i
)));
912 if (d
->io_regions
[i
].type
& PCI_BASE_ADDRESS_SPACE_IO
) {
913 reg
->phys_hi
|= cpu_to_be32(b_ss(1));
914 } else if (d
->io_regions
[i
].type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
915 reg
->phys_hi
|= cpu_to_be32(b_ss(3));
917 reg
->phys_hi
|= cpu_to_be32(b_ss(2));
921 reg
->size_hi
= cpu_to_be32(d
->io_regions
[i
].size
>> 32);
922 reg
->size_lo
= cpu_to_be32(d
->io_regions
[i
].size
);
924 if (d
->io_regions
[i
].addr
== PCI_BAR_UNMAPPED
) {
928 assigned
= &rp
->assigned
[assigned_idx
++];
929 assigned
->phys_hi
= cpu_to_be32(reg
->phys_hi
| b_n(1));
930 assigned
->phys_mid
= cpu_to_be32(d
->io_regions
[i
].addr
>> 32);
931 assigned
->phys_lo
= cpu_to_be32(d
->io_regions
[i
].addr
);
932 assigned
->size_hi
= reg
->size_hi
;
933 assigned
->size_lo
= reg
->size_lo
;
936 rp
->reg_len
= reg_idx
* sizeof(ResourceFields
);
937 rp
->assigned_len
= assigned_idx
* sizeof(ResourceFields
);
940 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState
*phb
,
943 static int spapr_populate_pci_child_dt(PCIDevice
*dev
, void *fdt
, int offset
,
947 bool is_bridge
= false;
950 uint32_t drc_index
= spapr_phb_get_pci_drc_index(sphb
, dev
);
952 if (pci_default_read_config(dev
, PCI_HEADER_TYPE
, 1) ==
953 PCI_HEADER_TYPE_BRIDGE
) {
957 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
958 _FDT(fdt_setprop_cell(fdt
, offset
, "vendor-id",
959 pci_default_read_config(dev
, PCI_VENDOR_ID
, 2)));
960 _FDT(fdt_setprop_cell(fdt
, offset
, "device-id",
961 pci_default_read_config(dev
, PCI_DEVICE_ID
, 2)));
962 _FDT(fdt_setprop_cell(fdt
, offset
, "revision-id",
963 pci_default_read_config(dev
, PCI_REVISION_ID
, 1)));
964 _FDT(fdt_setprop_cell(fdt
, offset
, "class-code",
965 pci_default_read_config(dev
, PCI_CLASS_PROG
, 3)));
966 if (pci_default_read_config(dev
, PCI_INTERRUPT_PIN
, 1)) {
967 _FDT(fdt_setprop_cell(fdt
, offset
, "interrupts",
968 pci_default_read_config(dev
, PCI_INTERRUPT_PIN
, 1)));
972 _FDT(fdt_setprop_cell(fdt
, offset
, "min-grant",
973 pci_default_read_config(dev
, PCI_MIN_GNT
, 1)));
974 _FDT(fdt_setprop_cell(fdt
, offset
, "max-latency",
975 pci_default_read_config(dev
, PCI_MAX_LAT
, 1)));
978 if (pci_default_read_config(dev
, PCI_SUBSYSTEM_ID
, 2)) {
979 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-id",
980 pci_default_read_config(dev
, PCI_SUBSYSTEM_ID
, 2)));
983 if (pci_default_read_config(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2)) {
984 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-vendor-id",
985 pci_default_read_config(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2)));
988 _FDT(fdt_setprop_cell(fdt
, offset
, "cache-line-size",
989 pci_default_read_config(dev
, PCI_CACHE_LINE_SIZE
, 1)));
991 /* the following fdt cells are masked off the pci status register */
992 pci_status
= pci_default_read_config(dev
, PCI_STATUS
, 2);
993 _FDT(fdt_setprop_cell(fdt
, offset
, "devsel-speed",
994 PCI_STATUS_DEVSEL_MASK
& pci_status
));
996 if (pci_status
& PCI_STATUS_FAST_BACK
) {
997 _FDT(fdt_setprop(fdt
, offset
, "fast-back-to-back", NULL
, 0));
999 if (pci_status
& PCI_STATUS_66MHZ
) {
1000 _FDT(fdt_setprop(fdt
, offset
, "66mhz-capable", NULL
, 0));
1002 if (pci_status
& PCI_STATUS_UDF
) {
1003 _FDT(fdt_setprop(fdt
, offset
, "udf-supported", NULL
, 0));
1006 /* NOTE: this is normally generated by firmware via path/unit name,
1007 * but in our case we must set it manually since it does not get
1008 * processed by OF beforehand
1010 _FDT(fdt_setprop_string(fdt
, offset
, "name", "pci"));
1011 buf
= spapr_phb_get_loc_code(sphb
, dev
);
1013 error_report("Failed setting the ibm,loc-code");
1017 err
= fdt_setprop_string(fdt
, offset
, "ibm,loc-code", buf
);
1024 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
));
1027 _FDT(fdt_setprop_cell(fdt
, offset
, "#address-cells",
1028 RESOURCE_CELLS_ADDRESS
));
1029 _FDT(fdt_setprop_cell(fdt
, offset
, "#size-cells",
1030 RESOURCE_CELLS_SIZE
));
1031 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,req#msi-x",
1032 RESOURCE_CELLS_SIZE
));
1034 populate_resource_props(dev
, &rp
);
1035 _FDT(fdt_setprop(fdt
, offset
, "reg", (uint8_t *)rp
.reg
, rp
.reg_len
));
1036 _FDT(fdt_setprop(fdt
, offset
, "assigned-addresses",
1037 (uint8_t *)rp
.assigned
, rp
.assigned_len
));
1042 /* create OF node for pci device and required OF DT properties */
1043 static int spapr_create_pci_child_dt(sPAPRPHBState
*phb
, PCIDevice
*dev
,
1044 void *fdt
, int node_offset
)
1047 int slot
= PCI_SLOT(dev
->devfn
);
1048 int func
= PCI_FUNC(dev
->devfn
);
1049 char nodename
[FDT_NAME_MAX
];
1052 snprintf(nodename
, FDT_NAME_MAX
, "pci@%x,%x", slot
, func
);
1054 snprintf(nodename
, FDT_NAME_MAX
, "pci@%x", slot
);
1056 offset
= fdt_add_subnode(fdt
, node_offset
, nodename
);
1057 ret
= spapr_populate_pci_child_dt(dev
, fdt
, offset
, phb
);
1066 static void spapr_phb_add_pci_device(sPAPRDRConnector
*drc
,
1071 sPAPRDRConnectorClass
*drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1072 DeviceState
*dev
= DEVICE(pdev
);
1074 int fdt_start_offset
= 0, fdt_size
;
1076 if (dev
->hotplugged
) {
1077 fdt
= create_device_tree(&fdt_size
);
1078 fdt_start_offset
= spapr_create_pci_child_dt(phb
, pdev
, fdt
, 0);
1079 if (!fdt_start_offset
) {
1080 error_setg(errp
, "Failed to create pci child device tree node");
1085 drck
->attach(drc
, DEVICE(pdev
),
1086 fdt
, fdt_start_offset
, !dev
->hotplugged
, errp
);
1093 static void spapr_phb_remove_pci_device_cb(DeviceState
*dev
, void *opaque
)
1095 /* some version guests do not wait for completion of a device
1096 * cleanup (generally done asynchronously by the kernel) before
1097 * signaling to QEMU that the device is safe, but instead sleep
1098 * for some 'safe' period of time. unfortunately on a busy host
1099 * this sleep isn't guaranteed to be long enough, resulting in
1100 * bad things like IRQ lines being left asserted during final
1101 * device removal. to deal with this we call reset just prior
1102 * to finalizing the device, which will put the device back into
1103 * an 'idle' state, as the device cleanup code expects.
1105 pci_device_reset(PCI_DEVICE(dev
));
1106 object_unparent(OBJECT(dev
));
1109 static void spapr_phb_remove_pci_device(sPAPRDRConnector
*drc
,
1114 sPAPRDRConnectorClass
*drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1116 drck
->detach(drc
, DEVICE(pdev
), spapr_phb_remove_pci_device_cb
, phb
, errp
);
1119 static sPAPRDRConnector
*spapr_phb_get_pci_drc(sPAPRPHBState
*phb
,
1122 uint32_t busnr
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
))));
1123 return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI
,
1124 (phb
->index
<< 16) |
1129 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState
*phb
,
1132 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1133 sPAPRDRConnectorClass
*drck
;
1139 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1140 return drck
->get_index(drc
);
1143 static void spapr_phb_hot_plug_child(HotplugHandler
*plug_handler
,
1144 DeviceState
*plugged_dev
, Error
**errp
)
1146 sPAPRPHBState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1147 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1148 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1149 Error
*local_err
= NULL
;
1151 /* if DR is disabled we don't need to do anything in the case of
1152 * hotplug or coldplug callbacks
1154 if (!phb
->dr_enabled
) {
1155 /* if this is a hotplug operation initiated by the user
1156 * we need to let them know it's not enabled
1158 if (plugged_dev
->hotplugged
) {
1159 error_setg(errp
, QERR_BUS_NO_HOTPLUG
,
1160 object_get_typename(OBJECT(phb
)));
1167 spapr_phb_add_pci_device(drc
, phb
, pdev
, &local_err
);
1169 error_propagate(errp
, local_err
);
1172 if (plugged_dev
->hotplugged
) {
1173 spapr_hotplug_req_add_event(drc
);
1177 static void spapr_phb_hot_unplug_child(HotplugHandler
*plug_handler
,
1178 DeviceState
*plugged_dev
, Error
**errp
)
1180 sPAPRPHBState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1181 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1182 sPAPRDRConnectorClass
*drck
;
1183 sPAPRDRConnector
*drc
= spapr_phb_get_pci_drc(phb
, pdev
);
1184 Error
*local_err
= NULL
;
1186 if (!phb
->dr_enabled
) {
1187 error_setg(errp
, QERR_BUS_NO_HOTPLUG
,
1188 object_get_typename(OBJECT(phb
)));
1194 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
1195 if (!drck
->release_pending(drc
)) {
1196 spapr_phb_remove_pci_device(drc
, phb
, pdev
, &local_err
);
1198 error_propagate(errp
, local_err
);
1201 spapr_hotplug_req_remove_event(drc
);
1205 static void spapr_phb_realize(DeviceState
*dev
, Error
**errp
)
1207 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
1208 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
1209 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(s
);
1210 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
1211 sPAPRPHBClass
*info
= SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s
);
1215 uint64_t msi_window_size
= 4096;
1217 if (sphb
->index
!= (uint32_t)-1) {
1218 hwaddr windows_base
;
1220 if ((sphb
->buid
!= (uint64_t)-1) || (sphb
->dma_liobn
!= (uint32_t)-1)
1221 || (sphb
->mem_win_addr
!= (hwaddr
)-1)
1222 || (sphb
->io_win_addr
!= (hwaddr
)-1)) {
1223 error_setg(errp
, "Either \"index\" or other parameters must"
1224 " be specified for PAPR PHB, not both");
1228 if (sphb
->index
> SPAPR_PCI_MAX_INDEX
) {
1229 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
1230 SPAPR_PCI_MAX_INDEX
);
1234 sphb
->buid
= SPAPR_PCI_BASE_BUID
+ sphb
->index
;
1235 sphb
->dma_liobn
= SPAPR_PCI_LIOBN(sphb
->index
, 0);
1237 windows_base
= SPAPR_PCI_WINDOW_BASE
1238 + sphb
->index
* SPAPR_PCI_WINDOW_SPACING
;
1239 sphb
->mem_win_addr
= windows_base
+ SPAPR_PCI_MMIO_WIN_OFF
;
1240 sphb
->io_win_addr
= windows_base
+ SPAPR_PCI_IO_WIN_OFF
;
1243 if (sphb
->buid
== (uint64_t)-1) {
1244 error_setg(errp
, "BUID not specified for PHB");
1248 if (sphb
->dma_liobn
== (uint32_t)-1) {
1249 error_setg(errp
, "LIOBN not specified for PHB");
1253 if (sphb
->mem_win_addr
== (hwaddr
)-1) {
1254 error_setg(errp
, "Memory window address not specified for PHB");
1258 if (sphb
->io_win_addr
== (hwaddr
)-1) {
1259 error_setg(errp
, "IO window address not specified for PHB");
1263 if (spapr_pci_find_phb(spapr
, sphb
->buid
)) {
1264 error_setg(errp
, "PCI host bridges must have unique BUIDs");
1268 sphb
->dtbusname
= g_strdup_printf("pci@%" PRIx64
, sphb
->buid
);
1270 namebuf
= alloca(strlen(sphb
->dtbusname
) + 32);
1272 /* Initialize memory regions */
1273 sprintf(namebuf
, "%s.mmio", sphb
->dtbusname
);
1274 memory_region_init(&sphb
->memspace
, OBJECT(sphb
), namebuf
, UINT64_MAX
);
1276 sprintf(namebuf
, "%s.mmio-alias", sphb
->dtbusname
);
1277 memory_region_init_alias(&sphb
->memwindow
, OBJECT(sphb
),
1278 namebuf
, &sphb
->memspace
,
1279 SPAPR_PCI_MEM_WIN_BUS_OFFSET
, sphb
->mem_win_size
);
1280 memory_region_add_subregion(get_system_memory(), sphb
->mem_win_addr
,
1283 /* Initialize IO regions */
1284 sprintf(namebuf
, "%s.io", sphb
->dtbusname
);
1285 memory_region_init(&sphb
->iospace
, OBJECT(sphb
),
1286 namebuf
, SPAPR_PCI_IO_WIN_SIZE
);
1288 sprintf(namebuf
, "%s.io-alias", sphb
->dtbusname
);
1289 memory_region_init_alias(&sphb
->iowindow
, OBJECT(sphb
), namebuf
,
1290 &sphb
->iospace
, 0, SPAPR_PCI_IO_WIN_SIZE
);
1291 memory_region_add_subregion(get_system_memory(), sphb
->io_win_addr
,
1294 bus
= pci_register_bus(dev
, NULL
,
1295 pci_spapr_set_irq
, pci_spapr_map_irq
, sphb
,
1296 &sphb
->memspace
, &sphb
->iospace
,
1297 PCI_DEVFN(0, 0), PCI_NUM_PINS
, TYPE_PCI_BUS
);
1299 qbus_set_hotplug_handler(BUS(phb
->bus
), DEVICE(sphb
), NULL
);
1302 * Initialize PHB address space.
1303 * By default there will be at least one subregion for default
1305 * Later the guest might want to create another DMA window
1306 * which will become another memory subregion.
1308 sprintf(namebuf
, "%s.iommu-root", sphb
->dtbusname
);
1310 memory_region_init(&sphb
->iommu_root
, OBJECT(sphb
),
1311 namebuf
, UINT64_MAX
);
1312 address_space_init(&sphb
->iommu_as
, &sphb
->iommu_root
,
1316 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1317 * we need to allocate some memory to catch those writes coming
1318 * from msi_notify()/msix_notify().
1319 * As MSIMessage:addr is going to be the same and MSIMessage:data
1320 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1323 * For KVM we want to ensure that this memory is a full page so that
1324 * our memory slot is of page size granularity.
1327 if (kvm_enabled()) {
1328 msi_window_size
= getpagesize();
1332 memory_region_init_io(&sphb
->msiwindow
, NULL
, &spapr_msi_ops
, spapr
,
1333 "msi", msi_window_size
);
1334 memory_region_add_subregion(&sphb
->iommu_root
, SPAPR_PCI_MSI_WINDOW
,
1337 pci_setup_iommu(bus
, spapr_pci_dma_iommu
, sphb
);
1339 pci_bus_set_route_irq_fn(bus
, spapr_route_intx_pin_to_irq
);
1341 QLIST_INSERT_HEAD(&spapr
->phbs
, sphb
, list
);
1343 /* Initialize the LSI table */
1344 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
1347 irq
= xics_alloc_block(spapr
->icp
, 0, 1, true, false);
1349 error_setg(errp
, "spapr_allocate_lsi failed");
1353 sphb
->lsi_table
[i
].irq
= irq
;
1356 /* allocate connectors for child PCI devices */
1357 if (sphb
->dr_enabled
) {
1358 for (i
= 0; i
< PCI_SLOT_MAX
* 8; i
++) {
1359 spapr_dr_connector_new(OBJECT(phb
),
1360 SPAPR_DR_CONNECTOR_TYPE_PCI
,
1361 (sphb
->index
<< 16) | i
);
1365 if (!info
->finish_realize
) {
1366 error_setg(errp
, "finish_realize not defined");
1370 info
->finish_realize(sphb
, errp
);
1372 sphb
->msi
= g_hash_table_new_full(g_int_hash
, g_int_equal
, g_free
, g_free
);
1375 static void spapr_phb_finish_realize(sPAPRPHBState
*sphb
, Error
**errp
)
1377 sPAPRTCETable
*tcet
;
1380 nb_table
= SPAPR_PCI_DMA32_SIZE
>> SPAPR_TCE_PAGE_SHIFT
;
1381 tcet
= spapr_tce_new_table(DEVICE(sphb
), sphb
->dma_liobn
,
1382 0, SPAPR_TCE_PAGE_SHIFT
, nb_table
, false);
1384 error_setg(errp
, "Unable to create TCE table for %s",
1389 /* Register default 32bit DMA window */
1390 memory_region_add_subregion(&sphb
->iommu_root
, 0,
1391 spapr_tce_get_iommu(tcet
));
1394 static int spapr_phb_children_reset(Object
*child
, void *opaque
)
1396 DeviceState
*dev
= (DeviceState
*) object_dynamic_cast(child
, TYPE_DEVICE
);
1405 static void spapr_phb_reset(DeviceState
*qdev
)
1407 /* Reset the IOMMU state */
1408 object_child_foreach(OBJECT(qdev
), spapr_phb_children_reset
, NULL
);
1411 static Property spapr_phb_properties
[] = {
1412 DEFINE_PROP_UINT32("index", sPAPRPHBState
, index
, -1),
1413 DEFINE_PROP_UINT64("buid", sPAPRPHBState
, buid
, -1),
1414 DEFINE_PROP_UINT32("liobn", sPAPRPHBState
, dma_liobn
, -1),
1415 DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState
, mem_win_addr
, -1),
1416 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState
, mem_win_size
,
1417 SPAPR_PCI_MMIO_WIN_SIZE
),
1418 DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState
, io_win_addr
, -1),
1419 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState
, io_win_size
,
1420 SPAPR_PCI_IO_WIN_SIZE
),
1421 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState
, dr_enabled
,
1423 DEFINE_PROP_END_OF_LIST(),
1426 static const VMStateDescription vmstate_spapr_pci_lsi
= {
1427 .name
= "spapr_pci/lsi",
1429 .minimum_version_id
= 1,
1430 .fields
= (VMStateField
[]) {
1431 VMSTATE_UINT32_EQUAL(irq
, struct spapr_pci_lsi
),
1433 VMSTATE_END_OF_LIST()
1437 static const VMStateDescription vmstate_spapr_pci_msi
= {
1438 .name
= "spapr_pci/msi",
1440 .minimum_version_id
= 1,
1441 .fields
= (VMStateField
[]) {
1442 VMSTATE_UINT32(key
, spapr_pci_msi_mig
),
1443 VMSTATE_UINT32(value
.first_irq
, spapr_pci_msi_mig
),
1444 VMSTATE_UINT32(value
.num
, spapr_pci_msi_mig
),
1445 VMSTATE_END_OF_LIST()
1449 static void spapr_pci_pre_save(void *opaque
)
1451 sPAPRPHBState
*sphb
= opaque
;
1452 GHashTableIter iter
;
1453 gpointer key
, value
;
1456 if (sphb
->msi_devs
) {
1457 g_free(sphb
->msi_devs
);
1458 sphb
->msi_devs
= NULL
;
1460 sphb
->msi_devs_num
= g_hash_table_size(sphb
->msi
);
1461 if (!sphb
->msi_devs_num
) {
1464 sphb
->msi_devs
= g_malloc(sphb
->msi_devs_num
* sizeof(spapr_pci_msi_mig
));
1466 g_hash_table_iter_init(&iter
, sphb
->msi
);
1467 for (i
= 0; g_hash_table_iter_next(&iter
, &key
, &value
); ++i
) {
1468 sphb
->msi_devs
[i
].key
= *(uint32_t *) key
;
1469 sphb
->msi_devs
[i
].value
= *(spapr_pci_msi
*) value
;
1473 static int spapr_pci_post_load(void *opaque
, int version_id
)
1475 sPAPRPHBState
*sphb
= opaque
;
1476 gpointer key
, value
;
1479 for (i
= 0; i
< sphb
->msi_devs_num
; ++i
) {
1480 key
= g_memdup(&sphb
->msi_devs
[i
].key
,
1481 sizeof(sphb
->msi_devs
[i
].key
));
1482 value
= g_memdup(&sphb
->msi_devs
[i
].value
,
1483 sizeof(sphb
->msi_devs
[i
].value
));
1484 g_hash_table_insert(sphb
->msi
, key
, value
);
1486 if (sphb
->msi_devs
) {
1487 g_free(sphb
->msi_devs
);
1488 sphb
->msi_devs
= NULL
;
1490 sphb
->msi_devs_num
= 0;
1495 static const VMStateDescription vmstate_spapr_pci
= {
1496 .name
= "spapr_pci",
1498 .minimum_version_id
= 2,
1499 .pre_save
= spapr_pci_pre_save
,
1500 .post_load
= spapr_pci_post_load
,
1501 .fields
= (VMStateField
[]) {
1502 VMSTATE_UINT64_EQUAL(buid
, sPAPRPHBState
),
1503 VMSTATE_UINT32_EQUAL(dma_liobn
, sPAPRPHBState
),
1504 VMSTATE_UINT64_EQUAL(mem_win_addr
, sPAPRPHBState
),
1505 VMSTATE_UINT64_EQUAL(mem_win_size
, sPAPRPHBState
),
1506 VMSTATE_UINT64_EQUAL(io_win_addr
, sPAPRPHBState
),
1507 VMSTATE_UINT64_EQUAL(io_win_size
, sPAPRPHBState
),
1508 VMSTATE_STRUCT_ARRAY(lsi_table
, sPAPRPHBState
, PCI_NUM_PINS
, 0,
1509 vmstate_spapr_pci_lsi
, struct spapr_pci_lsi
),
1510 VMSTATE_INT32(msi_devs_num
, sPAPRPHBState
),
1511 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs
, sPAPRPHBState
, msi_devs_num
, 0,
1512 vmstate_spapr_pci_msi
, spapr_pci_msi_mig
),
1513 VMSTATE_END_OF_LIST()
1517 static const char *spapr_phb_root_bus_path(PCIHostState
*host_bridge
,
1520 sPAPRPHBState
*sphb
= SPAPR_PCI_HOST_BRIDGE(host_bridge
);
1522 return sphb
->dtbusname
;
1525 static void spapr_phb_class_init(ObjectClass
*klass
, void *data
)
1527 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_CLASS(klass
);
1528 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1529 sPAPRPHBClass
*spc
= SPAPR_PCI_HOST_BRIDGE_CLASS(klass
);
1530 HotplugHandlerClass
*hp
= HOTPLUG_HANDLER_CLASS(klass
);
1532 hc
->root_bus_path
= spapr_phb_root_bus_path
;
1533 dc
->realize
= spapr_phb_realize
;
1534 dc
->props
= spapr_phb_properties
;
1535 dc
->reset
= spapr_phb_reset
;
1536 dc
->vmsd
= &vmstate_spapr_pci
;
1537 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
1538 dc
->cannot_instantiate_with_device_add_yet
= false;
1539 spc
->finish_realize
= spapr_phb_finish_realize
;
1540 hp
->plug
= spapr_phb_hot_plug_child
;
1541 hp
->unplug
= spapr_phb_hot_unplug_child
;
1544 static const TypeInfo spapr_phb_info
= {
1545 .name
= TYPE_SPAPR_PCI_HOST_BRIDGE
,
1546 .parent
= TYPE_PCI_HOST_BRIDGE
,
1547 .instance_size
= sizeof(sPAPRPHBState
),
1548 .class_init
= spapr_phb_class_init
,
1549 .class_size
= sizeof(sPAPRPHBClass
),
1550 .interfaces
= (InterfaceInfo
[]) {
1551 { TYPE_HOTPLUG_HANDLER
},
1556 PCIHostState
*spapr_create_phb(sPAPRMachineState
*spapr
, int index
)
1560 dev
= qdev_create(NULL
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
1561 qdev_prop_set_uint32(dev
, "index", index
);
1562 qdev_init_nofail(dev
);
1564 return PCI_HOST_BRIDGE(dev
);
1567 typedef struct sPAPRFDT
{
1570 sPAPRPHBState
*sphb
;
1573 static void spapr_populate_pci_devices_dt(PCIBus
*bus
, PCIDevice
*pdev
,
1577 sPAPRFDT
*p
= opaque
;
1581 offset
= spapr_create_pci_child_dt(p
->sphb
, pdev
, p
->fdt
, p
->node_off
);
1583 error_report("Failed to create pci child device tree node");
1587 if ((pci_default_read_config(pdev
, PCI_HEADER_TYPE
, 1) !=
1588 PCI_HEADER_TYPE_BRIDGE
)) {
1592 sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
1598 s_fdt
.node_off
= offset
;
1599 s_fdt
.sphb
= p
->sphb
;
1600 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
1601 spapr_populate_pci_devices_dt
,
1605 static void spapr_phb_pci_enumerate_bridge(PCIBus
*bus
, PCIDevice
*pdev
,
1608 unsigned int *bus_no
= opaque
;
1609 unsigned int primary
= *bus_no
;
1610 unsigned int subordinate
= 0xff;
1611 PCIBus
*sec_bus
= NULL
;
1613 if ((pci_default_read_config(pdev
, PCI_HEADER_TYPE
, 1) !=
1614 PCI_HEADER_TYPE_BRIDGE
)) {
1619 pci_default_write_config(pdev
, PCI_PRIMARY_BUS
, primary
, 1);
1620 pci_default_write_config(pdev
, PCI_SECONDARY_BUS
, *bus_no
, 1);
1621 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, *bus_no
, 1);
1623 sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
1628 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, subordinate
, 1);
1629 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
1630 spapr_phb_pci_enumerate_bridge
, bus_no
);
1631 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, *bus_no
, 1);
1634 static void spapr_phb_pci_enumerate(sPAPRPHBState
*phb
)
1636 PCIBus
*bus
= PCI_HOST_BRIDGE(phb
)->bus
;
1637 unsigned int bus_no
= 0;
1639 pci_for_each_device(bus
, pci_bus_num(bus
),
1640 spapr_phb_pci_enumerate_bridge
,
1645 int spapr_populate_pci_dt(sPAPRPHBState
*phb
,
1646 uint32_t xics_phandle
,
1649 int bus_off
, i
, j
, ret
;
1650 char nodename
[FDT_NAME_MAX
];
1651 uint32_t bus_range
[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
1652 const uint64_t mmiosize
= memory_region_size(&phb
->memwindow
);
1653 const uint64_t w32max
= (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET
;
1654 const uint64_t w32size
= MIN(w32max
, mmiosize
);
1655 const uint64_t w64size
= (mmiosize
> w32size
) ? (mmiosize
- w32size
) : 0;
1661 } QEMU_PACKED ranges
[] = {
1663 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
1664 cpu_to_be64(phb
->io_win_addr
),
1665 cpu_to_be64(memory_region_size(&phb
->iospace
)),
1668 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET
),
1669 cpu_to_be64(phb
->mem_win_addr
),
1670 cpu_to_be64(w32size
),
1673 cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32),
1674 cpu_to_be64(phb
->mem_win_addr
+ w32size
),
1675 cpu_to_be64(w64size
)
1678 const unsigned sizeof_ranges
= (w64size
? 3 : 2) * sizeof(ranges
[0]);
1679 uint64_t bus_reg
[] = { cpu_to_be64(phb
->buid
), 0 };
1680 uint32_t interrupt_map_mask
[] = {
1681 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
1682 uint32_t interrupt_map
[PCI_SLOT_MAX
* PCI_NUM_PINS
][7];
1683 sPAPRTCETable
*tcet
;
1684 PCIBus
*bus
= PCI_HOST_BRIDGE(phb
)->bus
;
1687 /* Start populating the FDT */
1688 snprintf(nodename
, FDT_NAME_MAX
, "pci@%" PRIx64
, phb
->buid
);
1689 bus_off
= fdt_add_subnode(fdt
, 0, nodename
);
1694 /* Write PHB properties */
1695 _FDT(fdt_setprop_string(fdt
, bus_off
, "device_type", "pci"));
1696 _FDT(fdt_setprop_string(fdt
, bus_off
, "compatible", "IBM,Logical_PHB"));
1697 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#address-cells", 0x3));
1698 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#size-cells", 0x2));
1699 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#interrupt-cells", 0x1));
1700 _FDT(fdt_setprop(fdt
, bus_off
, "used-by-rtas", NULL
, 0));
1701 _FDT(fdt_setprop(fdt
, bus_off
, "bus-range", &bus_range
, sizeof(bus_range
)));
1702 _FDT(fdt_setprop(fdt
, bus_off
, "ranges", &ranges
, sizeof_ranges
));
1703 _FDT(fdt_setprop(fdt
, bus_off
, "reg", &bus_reg
, sizeof(bus_reg
)));
1704 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pci-config-space-type", 0x1));
1705 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pe-total-#msi", XICS_IRQS
));
1707 /* Build the interrupt-map, this must matches what is done
1708 * in pci_spapr_map_irq
1710 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map-mask",
1711 &interrupt_map_mask
, sizeof(interrupt_map_mask
)));
1712 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
1713 for (j
= 0; j
< PCI_NUM_PINS
; j
++) {
1714 uint32_t *irqmap
= interrupt_map
[i
*PCI_NUM_PINS
+ j
];
1715 int lsi_num
= pci_spapr_swizzle(i
, j
);
1717 irqmap
[0] = cpu_to_be32(b_ddddd(i
)|b_fff(0));
1720 irqmap
[3] = cpu_to_be32(j
+1);
1721 irqmap
[4] = cpu_to_be32(xics_phandle
);
1722 irqmap
[5] = cpu_to_be32(phb
->lsi_table
[lsi_num
].irq
);
1723 irqmap
[6] = cpu_to_be32(0x8);
1726 /* Write interrupt map */
1727 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map", &interrupt_map
,
1728 sizeof(interrupt_map
)));
1730 tcet
= spapr_tce_find_by_liobn(SPAPR_PCI_LIOBN(phb
->index
, 0));
1731 spapr_dma_dt(fdt
, bus_off
, "ibm,dma-window",
1732 tcet
->liobn
, tcet
->bus_offset
,
1733 tcet
->nb_table
<< tcet
->page_shift
);
1735 /* Walk the bridges and program the bus numbers*/
1736 spapr_phb_pci_enumerate(phb
);
1737 _FDT(fdt_setprop_cell(fdt
, bus_off
, "qemu,phb-enumerated", 0x1));
1739 /* Populate tree nodes with PCI devices attached */
1741 s_fdt
.node_off
= bus_off
;
1743 pci_for_each_device(bus
, pci_bus_num(bus
),
1744 spapr_populate_pci_devices_dt
,
1747 ret
= spapr_drc_populate_dt(fdt
, bus_off
, OBJECT(phb
),
1748 SPAPR_DR_CONNECTOR_TYPE_PCI
);
1756 void spapr_pci_rtas_init(void)
1758 spapr_rtas_register(RTAS_READ_PCI_CONFIG
, "read-pci-config",
1759 rtas_read_pci_config
);
1760 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG
, "write-pci-config",
1761 rtas_write_pci_config
);
1762 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG
, "ibm,read-pci-config",
1763 rtas_ibm_read_pci_config
);
1764 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG
, "ibm,write-pci-config",
1765 rtas_ibm_write_pci_config
);
1766 if (msi_supported
) {
1767 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER
,
1768 "ibm,query-interrupt-source-number",
1769 rtas_ibm_query_interrupt_source_number
);
1770 spapr_rtas_register(RTAS_IBM_CHANGE_MSI
, "ibm,change-msi",
1771 rtas_ibm_change_msi
);
1774 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION
,
1775 "ibm,set-eeh-option",
1776 rtas_ibm_set_eeh_option
);
1777 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2
,
1778 "ibm,get-config-addr-info2",
1779 rtas_ibm_get_config_addr_info2
);
1780 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2
,
1781 "ibm,read-slot-reset-state2",
1782 rtas_ibm_read_slot_reset_state2
);
1783 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET
,
1784 "ibm,set-slot-reset",
1785 rtas_ibm_set_slot_reset
);
1786 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE
,
1788 rtas_ibm_configure_pe
);
1789 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL
,
1790 "ibm,slot-error-detail",
1791 rtas_ibm_slot_error_detail
);
1794 static void spapr_pci_register_types(void)
1796 type_register_static(&spapr_phb_info
);
1799 type_init(spapr_pci_register_types
)
1801 static int spapr_switch_one_vga(DeviceState
*dev
, void *opaque
)
1803 bool be
= *(bool *)opaque
;
1805 if (object_dynamic_cast(OBJECT(dev
), "VGA")
1806 || object_dynamic_cast(OBJECT(dev
), "secondary-vga")) {
1807 object_property_set_bool(OBJECT(dev
), be
, "big-endian-framebuffer",
1813 void spapr_pci_switch_vga(bool big_endian
)
1815 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
1816 sPAPRPHBState
*sphb
;
1819 * For backward compatibility with existing guests, we switch
1820 * the endianness of the VGA controller when changing the guest
1823 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
1824 BusState
*bus
= &PCI_HOST_BRIDGE(sphb
)->bus
->qbus
;
1825 qbus_walk_children(bus
, spapr_switch_one_vga
, NULL
, NULL
, NULL
,