hw/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc405.h"
  27 #include "nvram.h"
  28 #include "flash.h"
  29 #include "sysemu.h"
  30 #include "block.h"
  31 #include "boards.h"
  32 #include "qemu-log.h"
  33 #include "loader.h"
  34 #include "blockdev.h"
  35 #include "exec-memory.h"
  36
  37 #define BIOS_FILENAME "ppc405_rom.bin"
  38 #define BIOS_SIZE (2048 * 1024)
  39
  40 #define KERNEL_LOAD_ADDR 0x00000000
  41 #define INITRD_LOAD_ADDR 0x01800000
  42
  43 #define USE_FLASH_BIOS
  44
  45 #define DEBUG_BOARD_INIT
  46
  47 /*****************************************************************************/
  48 /* PPC405EP reference board (IBM) */
  49 /* Standalone board with:
  50  * - PowerPC 405EP CPU
  51  * - SDRAM (0x00000000)
  52  * - Flash (0xFFF80000)
  53  * - SRAM  (0xFFF00000)
  54  * - NVRAM (0xF0000000)
  55  * - FPGA  (0xF0300000)
  56  */
  57 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  58 struct ref405ep_fpga_t {
  59     uint8_t reg0;
  60     uint8_t reg1;
  61 };
  62
  63 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
  64 {
  65     ref405ep_fpga_t *fpga;
  66     uint32_t ret;
  67
  68     fpga = opaque;
  69     switch (addr) {
  70     case 0x0:
  71         ret = fpga->reg0;
  72         break;
  73     case 0x1:
  74         ret = fpga->reg1;
  75         break;
  76     default:
  77         ret = 0;
  78         break;
  79     }
  80
  81     return ret;
  82 }
  83
  84 static void ref405ep_fpga_writeb (void *opaque,
  85                                   target_phys_addr_t addr, uint32_t value)
  86 {
  87     ref405ep_fpga_t *fpga;
  88
  89     fpga = opaque;
  90     switch (addr) {
  91     case 0x0:
  92         /* Read only */
  93         break;
  94     case 0x1:
  95         fpga->reg1 = value;
  96         break;
  97     default:
  98         break;
  99     }
 100 }
 101
 102 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
 103 {
 104     uint32_t ret;
 105
 106     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 107     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 108
 109     return ret;
 110 }
 111
 112 static void ref405ep_fpga_writew (void *opaque,
 113                                   target_phys_addr_t addr, uint32_t value)
 114 {
 115     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 116     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 117 }
 118
 119 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
 120 {
 121     uint32_t ret;
 122
 123     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 124     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 125     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 126     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 127
 128     return ret;
 129 }
 130
 131 static void ref405ep_fpga_writel (void *opaque,
 132                                   target_phys_addr_t addr, uint32_t value)
 133 {
 134     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 135     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 136     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 137     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 138 }
 139
 140 static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
 141     &ref405ep_fpga_readb,
 142     &ref405ep_fpga_readw,
 143     &ref405ep_fpga_readl,
 144 };
 145
 146 static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
 147     &ref405ep_fpga_writeb,
 148     &ref405ep_fpga_writew,
 149     &ref405ep_fpga_writel,
 150 };
 151
 152 static void ref405ep_fpga_reset (void *opaque)
 153 {
 154     ref405ep_fpga_t *fpga;
 155
 156     fpga = opaque;
 157     fpga->reg0 = 0x00;
 158     fpga->reg1 = 0x0F;
 159 }
 160
 161 static void ref405ep_fpga_init (uint32_t base)
 162 {
 163     ref405ep_fpga_t *fpga;
 164     int fpga_memory;
 165
 166     fpga = g_malloc0(sizeof(ref405ep_fpga_t));
 167     fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
 168                                          ref405ep_fpga_write, fpga,
 169                                          DEVICE_NATIVE_ENDIAN);
 170     cpu_register_physical_memory(base, 0x00000100, fpga_memory);
 171     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 172 }
 173
 174 static void ref405ep_init (ram_addr_t ram_size,
 175                            const char *boot_device,
 176                            const char *kernel_filename,
 177                            const char *kernel_cmdline,
 178                            const char *initrd_filename,
 179                            const char *cpu_model)
 180 {
 181     char *filename;
 182     ppc4xx_bd_info_t bd;
 183     CPUPPCState *env;
 184     qemu_irq *pic;
 185     MemoryRegion *bios;
 186     ram_addr_t sram_offset, bdloc;
 187     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 188     target_phys_addr_t ram_bases[2], ram_sizes[2];
 189     target_ulong sram_size;
 190     long bios_size;
 191     //int phy_addr = 0;
 192     //static int phy_addr = 1;
 193     target_ulong kernel_base, initrd_base;
 194     long kernel_size, initrd_size;
 195     int linux_boot;
 196     int fl_idx, fl_sectors, len;
 197     DriveInfo *dinfo;
 198
 199     /* XXX: fix this */
 200     memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000);
 201     ram_bases[0] = 0;
 202     ram_sizes[0] = 0x08000000;
 203     memory_region_init(&ram_memories[1], "ef405ep.ram1", 0);
 204     ram_bases[1] = 0x00000000;
 205     ram_sizes[1] = 0x00000000;
 206     ram_size = 128 * 1024 * 1024;
 207 #ifdef DEBUG_BOARD_INIT
 208     printf("%s: register cpu\n", __func__);
 209 #endif
 210     env = ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
 211                         kernel_filename == NULL ? 0 : 1);
 212     /* allocate SRAM */
 213     sram_size = 512 * 1024;
 214     sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size);
 215 #ifdef DEBUG_BOARD_INIT
 216     printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
 217 #endif
 218     cpu_register_physical_memory(0xFFF00000, sram_size,
 219                                  sram_offset | IO_MEM_RAM);
 220     /* allocate and load BIOS */
 221 #ifdef DEBUG_BOARD_INIT
 222     printf("%s: register BIOS\n", __func__);
 223 #endif
 224     fl_idx = 0;
 225 #ifdef USE_FLASH_BIOS
 226     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 227     if (dinfo) {
 228         bios_size = bdrv_getlength(dinfo->bdrv);
 229         fl_sectors = (bios_size + 65535) >> 16;
 230 #ifdef DEBUG_BOARD_INIT
 231         printf("Register parallel flash %d size %lx"
 232                " at addr %lx '%s' %d\n",
 233                fl_idx, bios_size, -bios_size,
 234                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 235 #endif
 236         pflash_cfi02_register((uint32_t)(-bios_size),
 237                               NULL, "ef405ep.bios", bios_size,
 238                               dinfo->bdrv, 65536, fl_sectors, 1,
 239                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 240                               1);
 241         fl_idx++;
 242     } else
 243 #endif
 244     {
 245 #ifdef DEBUG_BOARD_INIT
 246         printf("Load BIOS from file\n");
 247 #endif
 248         bios = g_new(MemoryRegion, 1);
 249         memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE);
 250         if (bios_name == NULL)
 251             bios_name = BIOS_FILENAME;
 252         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 253         if (filename) {
 254             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 255             g_free(filename);
 256         } else {
 257             bios_size = -1;
 258         }
 259         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 260             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 261                     bios_name);
 262             exit(1);
 263         }
 264         bios_size = (bios_size + 0xfff) & ~0xfff;
 265         memory_region_set_readonly(bios, true);
 266         memory_region_add_subregion(get_system_memory(),
 267                                     (uint32_t)(-bios_size), bios);
 268     }
 269     /* Register FPGA */
 270 #ifdef DEBUG_BOARD_INIT
 271     printf("%s: register FPGA\n", __func__);
 272 #endif
 273     ref405ep_fpga_init(0xF0300000);
 274     /* Register NVRAM */
 275 #ifdef DEBUG_BOARD_INIT
 276     printf("%s: register NVRAM\n", __func__);
 277 #endif
 278     m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
 279     /* Load kernel */
 280     linux_boot = (kernel_filename != NULL);
 281     if (linux_boot) {
 282 #ifdef DEBUG_BOARD_INIT
 283         printf("%s: load kernel\n", __func__);
 284 #endif
 285         memset(&bd, 0, sizeof(bd));
 286         bd.bi_memstart = 0x00000000;
 287         bd.bi_memsize = ram_size;
 288         bd.bi_flashstart = -bios_size;
 289         bd.bi_flashsize = -bios_size;
 290         bd.bi_flashoffset = 0;
 291         bd.bi_sramstart = 0xFFF00000;
 292         bd.bi_sramsize = sram_size;
 293         bd.bi_bootflags = 0;
 294         bd.bi_intfreq = 133333333;
 295         bd.bi_busfreq = 33333333;
 296         bd.bi_baudrate = 115200;
 297         bd.bi_s_version[0] = 'Q';
 298         bd.bi_s_version[1] = 'M';
 299         bd.bi_s_version[2] = 'U';
 300         bd.bi_s_version[3] = '\0';
 301         bd.bi_r_version[0] = 'Q';
 302         bd.bi_r_version[1] = 'E';
 303         bd.bi_r_version[2] = 'M';
 304         bd.bi_r_version[3] = 'U';
 305         bd.bi_r_version[4] = '\0';
 306         bd.bi_procfreq = 133333333;
 307         bd.bi_plb_busfreq = 33333333;
 308         bd.bi_pci_busfreq = 33333333;
 309         bd.bi_opbfreq = 33333333;
 310         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 311         env->gpr[3] = bdloc;
 312         kernel_base = KERNEL_LOAD_ADDR;
 313         /* now we can load the kernel */
 314         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 315                                           ram_size - kernel_base);
 316         if (kernel_size < 0) {
 317             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 318                     kernel_filename);
 319             exit(1);
 320         }
 321         printf("Load kernel size %ld at " TARGET_FMT_lx,
 322                kernel_size, kernel_base);
 323         /* load initrd */
 324         if (initrd_filename) {
 325             initrd_base = INITRD_LOAD_ADDR;
 326             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 327                                               ram_size - initrd_base);
 328             if (initrd_size < 0) {
 329                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 330                         initrd_filename);
 331                 exit(1);
 332             }
 333         } else {
 334             initrd_base = 0;
 335             initrd_size = 0;
 336         }
 337         env->gpr[4] = initrd_base;
 338         env->gpr[5] = initrd_size;
 339         if (kernel_cmdline != NULL) {
 340             len = strlen(kernel_cmdline);
 341             bdloc -= ((len + 255) & ~255);
 342             cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
 343             env->gpr[6] = bdloc;
 344             env->gpr[7] = bdloc + len;
 345         } else {
 346             env->gpr[6] = 0;
 347             env->gpr[7] = 0;
 348         }
 349         env->nip = KERNEL_LOAD_ADDR;
 350     } else {
 351         kernel_base = 0;
 352         kernel_size = 0;
 353         initrd_base = 0;
 354         initrd_size = 0;
 355         bdloc = 0;
 356     }
 357 #ifdef DEBUG_BOARD_INIT
 358     printf("%s: Done\n", __func__);
 359 #endif
 360     printf("bdloc %016lx\n", (unsigned long)bdloc);
 361 }
 362
 363 static QEMUMachine ref405ep_machine = {
 364     .name = "ref405ep",
 365     .desc = "ref405ep",
 366     .init = ref405ep_init,
 367 };
 368
 369 /*****************************************************************************/
 370 /* AMCC Taihu evaluation board */
 371 /* - PowerPC 405EP processor
 372  * - SDRAM               128 MB at 0x00000000
 373  * - Boot flash          2 MB   at 0xFFE00000
 374  * - Application flash   32 MB  at 0xFC000000
 375  * - 2 serial ports
 376  * - 2 ethernet PHY
 377  * - 1 USB 1.1 device    0x50000000
 378  * - 1 LCD display       0x50100000
 379  * - 1 CPLD              0x50100000
 380  * - 1 I2C EEPROM
 381  * - 1 I2C thermal sensor
 382  * - a set of LEDs
 383  * - bit-bang SPI port using GPIOs
 384  * - 1 EBC interface connector 0 0x50200000
 385  * - 1 cardbus controller + expansion slot.
 386  * - 1 PCI expansion slot.
 387  */
 388 typedef struct taihu_cpld_t taihu_cpld_t;
 389 struct taihu_cpld_t {
 390     uint8_t reg0;
 391     uint8_t reg1;
 392 };
 393
 394 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
 395 {
 396     taihu_cpld_t *cpld;
 397     uint32_t ret;
 398
 399     cpld = opaque;
 400     switch (addr) {
 401     case 0x0:
 402         ret = cpld->reg0;
 403         break;
 404     case 0x1:
 405         ret = cpld->reg1;
 406         break;
 407     default:
 408         ret = 0;
 409         break;
 410     }
 411
 412     return ret;
 413 }
 414
 415 static void taihu_cpld_writeb (void *opaque,
 416                                target_phys_addr_t addr, uint32_t value)
 417 {
 418     taihu_cpld_t *cpld;
 419
 420     cpld = opaque;
 421     switch (addr) {
 422     case 0x0:
 423         /* Read only */
 424         break;
 425     case 0x1:
 426         cpld->reg1 = value;
 427         break;
 428     default:
 429         break;
 430     }
 431 }
 432
 433 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
 434 {
 435     uint32_t ret;
 436
 437     ret = taihu_cpld_readb(opaque, addr) << 8;
 438     ret |= taihu_cpld_readb(opaque, addr + 1);
 439
 440     return ret;
 441 }
 442
 443 static void taihu_cpld_writew (void *opaque,
 444                                target_phys_addr_t addr, uint32_t value)
 445 {
 446     taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
 447     taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
 448 }
 449
 450 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
 451 {
 452     uint32_t ret;
 453
 454     ret = taihu_cpld_readb(opaque, addr) << 24;
 455     ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
 456     ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
 457     ret |= taihu_cpld_readb(opaque, addr + 3);
 458
 459     return ret;
 460 }
 461
 462 static void taihu_cpld_writel (void *opaque,
 463                                target_phys_addr_t addr, uint32_t value)
 464 {
 465     taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
 466     taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 467     taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 468     taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
 469 }
 470
 471 static CPUReadMemoryFunc * const taihu_cpld_read[] = {
 472     &taihu_cpld_readb,
 473     &taihu_cpld_readw,
 474     &taihu_cpld_readl,
 475 };
 476
 477 static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
 478     &taihu_cpld_writeb,
 479     &taihu_cpld_writew,
 480     &taihu_cpld_writel,
 481 };
 482
 483 static void taihu_cpld_reset (void *opaque)
 484 {
 485     taihu_cpld_t *cpld;
 486
 487     cpld = opaque;
 488     cpld->reg0 = 0x01;
 489     cpld->reg1 = 0x80;
 490 }
 491
 492 static void taihu_cpld_init (uint32_t base)
 493 {
 494     taihu_cpld_t *cpld;
 495     int cpld_memory;
 496
 497     cpld = g_malloc0(sizeof(taihu_cpld_t));
 498     cpld_memory = cpu_register_io_memory(taihu_cpld_read,
 499                                          taihu_cpld_write, cpld,
 500                                          DEVICE_NATIVE_ENDIAN);
 501     cpu_register_physical_memory(base, 0x00000100, cpld_memory);
 502     qemu_register_reset(&taihu_cpld_reset, cpld);
 503 }
 504
 505 static void taihu_405ep_init(ram_addr_t ram_size,
 506                              const char *boot_device,
 507                              const char *kernel_filename,
 508                              const char *kernel_cmdline,
 509                              const char *initrd_filename,
 510                              const char *cpu_model)
 511 {
 512     char *filename;
 513     qemu_irq *pic;
 514     MemoryRegion *bios;
 515     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 516     target_phys_addr_t ram_bases[2], ram_sizes[2];
 517     long bios_size;
 518     target_ulong kernel_base, initrd_base;
 519     long kernel_size, initrd_size;
 520     int linux_boot;
 521     int fl_idx, fl_sectors;
 522     DriveInfo *dinfo;
 523
 524     /* RAM is soldered to the board so the size cannot be changed */
 525     memory_region_init_ram(&ram_memories[0], NULL,
 526                            "taihu_405ep.ram-0", 0x04000000);
 527     ram_bases[0] = 0;
 528     ram_sizes[0] = 0x04000000;
 529     memory_region_init_ram(&ram_memories[1], NULL,
 530                            "taihu_405ep.ram-1", 0x04000000);
 531     ram_bases[1] = 0x04000000;
 532     ram_sizes[1] = 0x04000000;
 533     ram_size = 0x08000000;
 534 #ifdef DEBUG_BOARD_INIT
 535     printf("%s: register cpu\n", __func__);
 536 #endif
 537     ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
 538                   kernel_filename == NULL ? 0 : 1);
 539     /* allocate and load BIOS */
 540 #ifdef DEBUG_BOARD_INIT
 541     printf("%s: register BIOS\n", __func__);
 542 #endif
 543     fl_idx = 0;
 544 #if defined(USE_FLASH_BIOS)
 545     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 546     if (dinfo) {
 547         bios_size = bdrv_getlength(dinfo->bdrv);
 548         /* XXX: should check that size is 2MB */
 549         //        bios_size = 2 * 1024 * 1024;
 550         fl_sectors = (bios_size + 65535) >> 16;
 551 #ifdef DEBUG_BOARD_INIT
 552         printf("Register parallel flash %d size %lx"
 553                " at addr %lx '%s' %d\n",
 554                fl_idx, bios_size, -bios_size,
 555                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 556 #endif
 557         pflash_cfi02_register((uint32_t)(-bios_size),
 558                               NULL, "taihu_405ep.bios", bios_size,
 559                               dinfo->bdrv, 65536, fl_sectors, 1,
 560                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 561                               1);
 562         fl_idx++;
 563     } else
 564 #endif
 565     {
 566 #ifdef DEBUG_BOARD_INIT
 567         printf("Load BIOS from file\n");
 568 #endif
 569         if (bios_name == NULL)
 570             bios_name = BIOS_FILENAME;
 571         bios = g_new(MemoryRegion, 1);
 572         memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE);
 573         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 574         if (filename) {
 575             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 576             g_free(filename);
 577         } else {
 578             bios_size = -1;
 579         }
 580         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 581             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 582                     bios_name);
 583             exit(1);
 584         }
 585         bios_size = (bios_size + 0xfff) & ~0xfff;
 586         memory_region_set_readonly(bios, true);
 587         memory_region_add_subregion(get_system_memory(), (uint32_t)(-bios_size),
 588                                     bios);
 589     }
 590     /* Register Linux flash */
 591     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 592     if (dinfo) {
 593         bios_size = bdrv_getlength(dinfo->bdrv);
 594         /* XXX: should check that size is 32MB */
 595         bios_size = 32 * 1024 * 1024;
 596         fl_sectors = (bios_size + 65535) >> 16;
 597 #ifdef DEBUG_BOARD_INIT
 598         printf("Register parallel flash %d size %lx"
 599                " at addr " TARGET_FMT_lx " '%s'\n",
 600                fl_idx, bios_size, (target_ulong)0xfc000000,
 601                bdrv_get_device_name(dinfo->bdrv));
 602 #endif
 603         pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size,
 604                               dinfo->bdrv, 65536, fl_sectors, 1,
 605                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 606                               1);
 607         fl_idx++;
 608     }
 609     /* Register CLPD & LCD display */
 610 #ifdef DEBUG_BOARD_INIT
 611     printf("%s: register CPLD\n", __func__);
 612 #endif
 613     taihu_cpld_init(0x50100000);
 614     /* Load kernel */
 615     linux_boot = (kernel_filename != NULL);
 616     if (linux_boot) {
 617 #ifdef DEBUG_BOARD_INIT
 618         printf("%s: load kernel\n", __func__);
 619 #endif
 620         kernel_base = KERNEL_LOAD_ADDR;
 621         /* now we can load the kernel */
 622         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 623                                           ram_size - kernel_base);
 624         if (kernel_size < 0) {
 625             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 626                     kernel_filename);
 627             exit(1);
 628         }
 629         /* load initrd */
 630         if (initrd_filename) {
 631             initrd_base = INITRD_LOAD_ADDR;
 632             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 633                                               ram_size - initrd_base);
 634             if (initrd_size < 0) {
 635                 fprintf(stderr,
 636                         "qemu: could not load initial ram disk '%s'\n",
 637                         initrd_filename);
 638                 exit(1);
 639             }
 640         } else {
 641             initrd_base = 0;
 642             initrd_size = 0;
 643         }
 644     } else {
 645         kernel_base = 0;
 646         kernel_size = 0;
 647         initrd_base = 0;
 648         initrd_size = 0;
 649     }
 650 #ifdef DEBUG_BOARD_INIT
 651     printf("%s: Done\n", __func__);
 652 #endif
 653 }
 654
 655 static QEMUMachine taihu_machine = {
 656     .name = "taihu",
 657     .desc = "taihu",
 658     .init = taihu_405ep_init,
 659 };
 660
 661 static void ppc405_machine_init(void)
 662 {
 663     qemu_register_machine(&ref405ep_machine);
 664     qemu_register_machine(&taihu_machine);
 665 }
 666
 667 machine_init(ppc405_machine_init);