2 * QEMU PPC CHRP/PMAC hardware System Emulator
4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #define BIOS_FILENAME "ppc_rom.bin"
27 #define NVRAM_SIZE 0x2000
29 #define KERNEL_LOAD_ADDR 0x01000000
30 #define INITRD_LOAD_ADDR 0x01800000
32 /* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
33 NVRAM (not implemented). */
35 static int dbdma_mem_index
;
36 static int cuda_mem_index
;
37 static int ide0_mem_index
= -1;
38 static int ide1_mem_index
= -1;
39 static int openpic_mem_index
= -1;
40 static int heathrow_pic_mem_index
= -1;
42 /* DBDMA: currently no op - should suffice right now */
44 static void dbdma_writeb (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
46 printf("%s: 0x%08x <= 0x%08x\n", __func__
, addr
, value
);
49 static void dbdma_writew (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
53 static void dbdma_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
57 static uint32_t dbdma_readb (void *opaque
, target_phys_addr_t addr
)
59 printf("%s: 0x%08x => 0x00000000\n", __func__
, addr
);
63 static uint32_t dbdma_readw (void *opaque
, target_phys_addr_t addr
)
68 static uint32_t dbdma_readl (void *opaque
, target_phys_addr_t addr
)
73 static CPUWriteMemoryFunc
*dbdma_write
[] = {
79 static CPUReadMemoryFunc
*dbdma_read
[] = {
85 static void macio_map(PCIDevice
*pci_dev
, int region_num
,
86 uint32_t addr
, uint32_t size
, int type
)
88 if (heathrow_pic_mem_index
>= 0) {
89 cpu_register_physical_memory(addr
+ 0x00000, 0x1000,
90 heathrow_pic_mem_index
);
92 cpu_register_physical_memory(addr
+ 0x08000, 0x1000, dbdma_mem_index
);
93 cpu_register_physical_memory(addr
+ 0x16000, 0x2000, cuda_mem_index
);
94 if (ide0_mem_index
>= 0)
95 cpu_register_physical_memory(addr
+ 0x1f000, 0x1000, ide0_mem_index
);
96 if (ide1_mem_index
>= 0)
97 cpu_register_physical_memory(addr
+ 0x20000, 0x1000, ide1_mem_index
);
98 if (openpic_mem_index
>= 0) {
99 cpu_register_physical_memory(addr
+ 0x40000, 0x40000,
104 static void macio_init(PCIBus
*bus
)
108 d
= pci_register_device(bus
, "macio", sizeof(PCIDevice
),
110 /* Note: this code is strongly inspirated from the corresponding code
112 d
->config
[0x00] = 0x6b; // vendor_id
113 d
->config
[0x01] = 0x10;
114 d
->config
[0x02] = 0x22;
115 d
->config
[0x03] = 0x00;
117 d
->config
[0x0a] = 0x00; // class_sub = pci2pci
118 d
->config
[0x0b] = 0xff; // class_base = bridge
119 d
->config
[0x0e] = 0x00; // header_type
121 d
->config
[0x3d] = 0x01; // interrupt on pin 1
123 dbdma_mem_index
= cpu_register_io_memory(0, dbdma_read
, dbdma_write
, NULL
);
125 pci_register_io_region(d
, 0, 0x80000,
126 PCI_ADDRESS_SPACE_MEM
, macio_map
);
130 static void unin_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
134 static uint32_t unin_readl (void *opaque
, target_phys_addr_t addr
)
139 static CPUWriteMemoryFunc
*unin_write
[] = {
145 static CPUReadMemoryFunc
*unin_read
[] = {
151 /* temporary frame buffer OSI calls for the video.x driver. The right
152 solution is to modify the driver to use VGA PCI I/Os */
153 static int vga_osi_call(CPUState
*env
)
155 static int vga_vbl_enabled
;
158 // printf("osi_call R5=%d\n", env->gpr[5]);
160 /* same handler as PearPC, coming from the original MOL video
162 switch(env
->gpr
[5]) {
165 case 28: /* set_vmode */
166 if (env
->gpr
[6] != 1 || env
->gpr
[7] != 0)
171 case 29: /* get_vmode_info */
172 if (env
->gpr
[6] != 0) {
173 if (env
->gpr
[6] != 1 || env
->gpr
[7] != 0) {
179 env
->gpr
[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
180 env
->gpr
[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
181 env
->gpr
[6] = (graphic_width
<< 16) | graphic_height
; /* w, h */
182 env
->gpr
[7] = 85 << 16; /* refresh rate */
183 env
->gpr
[8] = (graphic_depth
+ 7) & ~7; /* depth (round to byte) */
184 linesize
= ((graphic_depth
+ 7) >> 3) * graphic_width
;
185 linesize
= (linesize
+ 3) & ~3;
186 env
->gpr
[9] = (linesize
<< 16) | 0; /* row_bytes, offset */
188 case 31: /* set_video power */
191 case 39: /* video_ctrl */
192 if (env
->gpr
[6] == 0 || env
->gpr
[6] == 1)
193 vga_vbl_enabled
= env
->gpr
[6];
198 case 59: /* set_color */
199 /* R6 = index, R7 = RGB */
202 case 64: /* get color */
206 case 116: /* set hwcursor */
207 /* R6 = x, R7 = y, R8 = visible, R9 = data */
210 fprintf(stderr
, "unsupported OSI call R5=%08x\n", env
->gpr
[5]);
213 return 1; /* osi_call handled */
216 /* XXX: suppress that */
217 static void pic_irq_request(void *opaque
, int level
)
221 /* PowerPC CHRP hardware initialisation */
222 static void ppc_chrp_init(int ram_size
, int vga_ram_size
, int boot_device
,
223 DisplayState
*ds
, const char **fd_filename
,
225 const char *kernel_filename
,
226 const char *kernel_cmdline
,
227 const char *initrd_filename
,
234 int PPC_io_memory
, unin_memory
;
235 int ret
, linux_boot
, i
;
236 unsigned long bios_offset
;
237 uint32_t kernel_base
, kernel_size
, initrd_base
, initrd_size
;
240 const char *arch_name
;
242 linux_boot
= (kernel_filename
!= NULL
);
245 cpu_register_physical_memory(0, ram_size
, IO_MEM_RAM
);
247 /* allocate and load BIOS */
248 bios_offset
= ram_size
+ vga_ram_size
;
249 snprintf(buf
, sizeof(buf
), "%s/%s", bios_dir
, BIOS_FILENAME
);
250 ret
= load_image(buf
, phys_ram_base
+ bios_offset
);
251 if (ret
!= BIOS_SIZE
) {
252 fprintf(stderr
, "qemu: could not load PPC PREP bios '%s'\n", buf
);
255 cpu_register_physical_memory((uint32_t)(-BIOS_SIZE
),
256 BIOS_SIZE
, bios_offset
| IO_MEM_ROM
);
257 cpu_single_env
->nip
= 0xfffffffc;
260 kernel_base
= KERNEL_LOAD_ADDR
;
261 /* now we can load the kernel */
262 kernel_size
= load_image(kernel_filename
, phys_ram_base
+ kernel_base
);
263 if (kernel_size
< 0) {
264 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
269 if (initrd_filename
) {
270 initrd_base
= INITRD_LOAD_ADDR
;
271 initrd_size
= load_image(initrd_filename
,
272 phys_ram_base
+ initrd_base
);
273 if (initrd_size
< 0) {
274 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
289 /* Register CPU as a 74x/75x */
290 /* XXX: CPU model (or PVR) should be provided on command line */
291 // ppc_find_by_name("750gx", &def); // Linux boot OK
292 // ppc_find_by_name("750fx", &def); // Linux boot OK
293 /* Linux does not boot on 750cxe (and probably other 750cx based)
294 * because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
296 // ppc_find_by_name("750cxe", &def);
297 // ppc_find_by_name("750p", &def);
298 // ppc_find_by_name("740p", &def);
299 ppc_find_by_name("750", &def
);
300 // ppc_find_by_name("740", &def);
301 // ppc_find_by_name("G3", &def);
302 // ppc_find_by_name("604r", &def);
303 // ppc_find_by_name("604e", &def);
304 // ppc_find_by_name("604", &def);
306 cpu_abort(cpu_single_env
, "Unable to find PowerPC CPU definition\n");
308 cpu_ppc_register(cpu_single_env
, def
);
310 /* Set time-base frequency to 100 Mhz */
311 cpu_ppc_tb_init(cpu_single_env
, 100UL * 1000UL * 1000UL);
313 cpu_single_env
->osi_call
= vga_osi_call
;
316 isa_mem_base
= 0x80000000;
317 pci_bus
= pci_grackle_init(0xfec00000);
319 /* Register 2 MB of ISA IO space */
320 PPC_io_memory
= cpu_register_io_memory(0, PPC_io_read
, PPC_io_write
, NULL
);
321 cpu_register_physical_memory(0xfe000000, 0x00200000, PPC_io_memory
);
323 /* init basic PC hardware */
324 vga_initialize(pci_bus
, ds
, phys_ram_base
+ ram_size
, ram_size
,
326 pic
= heathrow_pic_init(&heathrow_pic_mem_index
);
327 set_irq
= heathrow_pic_set_irq
;
328 pci_set_pic(pci_bus
, set_irq
, pic
);
330 /* XXX: suppress that */
331 isa_pic
= pic_init(pic_irq_request
, NULL
);
333 /* XXX: use Mac Serial port */
334 serial_init(0x3f8, 4, serial_hds
[0]);
336 for(i
= 0; i
< nb_nics
; i
++) {
337 pci_ne2000_init(pci_bus
, &nd_table
[i
]);
340 pci_cmd646_ide_init(pci_bus
, &bs_table
[0], 0);
342 /* cuda also initialize ADB */
343 cuda_mem_index
= cuda_init(set_irq
, pic
, 0x12);
345 adb_kbd_init(&adb_bus
);
346 adb_mouse_init(&adb_bus
);
350 nvram
= m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE
);
352 arch_name
= "HEATHROW";
354 isa_mem_base
= 0x80000000;
355 pci_bus
= pci_pmac_init();
357 /* Register 8 MB of ISA IO space */
358 PPC_io_memory
= cpu_register_io_memory(0, PPC_io_read
, PPC_io_write
, NULL
);
359 cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory
);
362 unin_memory
= cpu_register_io_memory(0, unin_read
, unin_write
, NULL
);
363 cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory
);
365 /* init basic PC hardware */
366 vga_initialize(pci_bus
, ds
, phys_ram_base
+ ram_size
, ram_size
,
368 pic
= openpic_init(NULL
, &openpic_mem_index
, 1);
369 set_irq
= openpic_set_irq
;
370 pci_set_pic(pci_bus
, set_irq
, pic
);
372 /* XXX: suppress that */
373 isa_pic
= pic_init(pic_irq_request
, NULL
);
375 /* XXX: use Mac Serial port */
376 serial_init(0x3f8, 4, serial_hds
[0]);
378 for(i
= 0; i
< nb_nics
; i
++) {
379 pci_ne2000_init(pci_bus
, &nd_table
[i
]);
383 ide0_mem_index
= pmac_ide_init(&bs_table
[0], set_irq
, pic
, 0x13);
384 ide1_mem_index
= pmac_ide_init(&bs_table
[2], set_irq
, pic
, 0x14);
386 pci_cmd646_ide_init(pci_bus
, &bs_table
[0], 0);
388 /* cuda also initialize ADB */
389 cuda_mem_index
= cuda_init(set_irq
, pic
, 0x19);
391 adb_kbd_init(&adb_bus
);
392 adb_mouse_init(&adb_bus
);
396 nvram
= m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE
);
401 if (graphic_depth
!= 15 && graphic_depth
!= 32 && graphic_depth
!= 8)
404 PPC_NVRAM_set_params(nvram
, NVRAM_SIZE
, arch_name
, ram_size
, boot_device
,
405 kernel_base
, kernel_size
,
407 initrd_base
, initrd_size
,
408 /* XXX: need an option to load a NVRAM image */
410 graphic_width
, graphic_height
, graphic_depth
);
411 /* No PCI init: the BIOS will do it */
413 /* Special port to get debug messages from Open-Firmware */
414 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write
, NULL
);
417 static void ppc_core99_init(int ram_size
, int vga_ram_size
, int boot_device
,
418 DisplayState
*ds
, const char **fd_filename
,
420 const char *kernel_filename
,
421 const char *kernel_cmdline
,
422 const char *initrd_filename
)
424 ppc_chrp_init(ram_size
, vga_ram_size
, boot_device
,
425 ds
, fd_filename
, snapshot
,
426 kernel_filename
, kernel_cmdline
,
430 static void ppc_heathrow_init(int ram_size
, int vga_ram_size
, int boot_device
,
431 DisplayState
*ds
, const char **fd_filename
,
433 const char *kernel_filename
,
434 const char *kernel_cmdline
,
435 const char *initrd_filename
)
437 ppc_chrp_init(ram_size
, vga_ram_size
, boot_device
,
438 ds
, fd_filename
, snapshot
,
439 kernel_filename
, kernel_cmdline
,
443 QEMUMachine core99_machine
= {
445 "Core99 based PowerMAC",
449 QEMUMachine heathrow_machine
= {
451 "Heathrow based PowerMAC",