hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "mac_dbdma.h"
  29 #include "nvram.h"
  30 #include "pc.h"
  31 #include "sysemu.h"
  32 #include "net.h"
  33 #include "isa.h"
  34 #include "pci.h"
  35 #include "usb-ohci.h"
  36 #include "boards.h"
  37 #include "fw_cfg.h"
  38 #include "escc.h"
  39 #include "ide.h"
  40 #include "loader.h"
  41 #include "elf.h"
  42 #include "kvm.h"
  43 #include "kvm_ppc.h"
  44 #include "blockdev.h"
  45
  46 #define MAX_IDE_BUS 2
  47 #define VGA_BIOS_SIZE 65536
  48 #define CFG_ADDR 0xf0000510
  49
  50 /* temporary frame buffer OSI calls for the video.x driver. The right
  51    solution is to modify the driver to use VGA PCI I/Os */
  52 /* XXX: to be removed. This is no way related to emulation */
  53 static int vga_osi_call (CPUState *env)
  54 {
  55     static int vga_vbl_enabled;
  56     int linesize;
  57
  58 #if 0
  59     printf("osi_call R5=%016" PRIx64 "\n", ppc_dump_gpr(env, 5));
  60 #endif
  61
  62     /* same handler as PearPC, coming from the original MOL video
  63        driver. */
  64     switch(env->gpr[5]) {
  65     case 4:
  66         break;
  67     case 28: /* set_vmode */
  68         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  69             env->gpr[3] = 1;
  70         else
  71             env->gpr[3] = 0;
  72         break;
  73     case 29: /* get_vmode_info */
  74         if (env->gpr[6] != 0) {
  75             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  76                 env->gpr[3] = 1;
  77                 break;
  78             }
  79         }
  80         env->gpr[3] = 0;
  81         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  82         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  83         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  84         env->gpr[7] = 85 << 16; /* refresh rate */
  85         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  86         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  87         linesize = (linesize + 3) & ~3;
  88         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  89         break;
  90     case 31: /* set_video power */
  91         env->gpr[3] = 0;
  92         break;
  93     case 39: /* video_ctrl */
  94         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  95             vga_vbl_enabled = env->gpr[6];
  96         env->gpr[3] = 0;
  97         break;
  98     case 47:
  99         break;
 100     case 59: /* set_color */
 101         /* R6 = index, R7 = RGB */
 102         env->gpr[3] = 0;
 103         break;
 104     case 64: /* get color */
 105         /* R6 = index */
 106         env->gpr[3] = 0;
 107         break;
 108     case 116: /* set hwcursor */
 109         /* R6 = x, R7 = y, R8 = visible, R9 = data */
 110         break;
 111     default:
 112         fprintf(stderr, "unsupported OSI call R5=%016" PRIx64 "\n",
 113                 ppc_dump_gpr(env, 5));
 114         break;
 115     }
 116
 117     return 1; /* osi_call handled */
 118 }
 119
 120 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 121 {
 122     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 123     return 0;
 124 }
 125
 126
 127 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
 128 {
 129     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
 130 }
 131
 132 static void ppc_heathrow_init (ram_addr_t ram_size,
 133                                const char *boot_device,
 134                                const char *kernel_filename,
 135                                const char *kernel_cmdline,
 136                                const char *initrd_filename,
 137                                const char *cpu_model)
 138 {
 139     CPUState *env = NULL, *envs[MAX_CPUS];
 140     char *filename;
 141     qemu_irq *pic, **heathrow_irqs;
 142     int linux_boot, i;
 143     ram_addr_t ram_offset, bios_offset, vga_bios_offset;
 144     uint32_t kernel_base, initrd_base;
 145     int32_t kernel_size, initrd_size;
 146     PCIBus *pci_bus;
 147     MacIONVRAMState *nvr;
 148     int vga_bios_size, bios_size;
 149     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 150     int escc_mem_index, ide_mem_index[2];
 151     uint16_t ppc_boot_device;
 152     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 153     void *fw_cfg;
 154     void *dbdma;
 155     uint8_t *vga_bios_ptr;
 156
 157     linux_boot = (kernel_filename != NULL);
 158
 159     /* init CPUs */
 160     if (cpu_model == NULL)
 161         cpu_model = "G3";
 162     for (i = 0; i < smp_cpus; i++) {
 163         env = cpu_init(cpu_model);
 164         if (!env) {
 165             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 166             exit(1);
 167         }
 168         /* Set time-base frequency to 16.6 Mhz */
 169         cpu_ppc_tb_init(env,  16600000UL);
 170         env->osi_call = vga_osi_call;
 171         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 172         envs[i] = env;
 173     }
 174
 175     /* allocate RAM */
 176     if (ram_size > (2047 << 20)) {
 177         fprintf(stderr,
 178                 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
 179                 ((unsigned int)ram_size / (1 << 20)));
 180         exit(1);
 181     }
 182
 183     ram_offset = qemu_ram_alloc(NULL, "ppc_heathrow.ram", ram_size);
 184     cpu_register_physical_memory(0, ram_size, ram_offset);
 185
 186     /* allocate and load BIOS */
 187     bios_offset = qemu_ram_alloc(NULL, "ppc_heathrow.bios", BIOS_SIZE);
 188     if (bios_name == NULL)
 189         bios_name = PROM_FILENAME;
 190     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 191     cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
 192
 193     /* Load OpenBIOS (ELF) */
 194     if (filename) {
 195         bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
 196                              1, ELF_MACHINE, 0);
 197         qemu_free(filename);
 198     } else {
 199         bios_size = -1;
 200     }
 201     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 202         hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
 203         exit(1);
 204     }
 205
 206     /* allocate and load VGA BIOS */
 207     vga_bios_offset = qemu_ram_alloc(NULL, "ppc_heathrow.vbios", VGA_BIOS_SIZE);
 208     vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset);
 209     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME);
 210     if (filename) {
 211         vga_bios_size = load_image(filename, vga_bios_ptr + 8);
 212         qemu_free(filename);
 213     } else {
 214         vga_bios_size = -1;
 215     }
 216     if (vga_bios_size < 0) {
 217         /* if no bios is present, we can still work */
 218         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n",
 219                 VGABIOS_FILENAME);
 220         vga_bios_size = 0;
 221     } else {
 222         /* set a specific header (XXX: find real Apple format for NDRV
 223            drivers) */
 224         vga_bios_ptr[0] = 'N';
 225         vga_bios_ptr[1] = 'D';
 226         vga_bios_ptr[2] = 'R';
 227         vga_bios_ptr[3] = 'V';
 228         cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size);
 229         vga_bios_size += 8;
 230
 231         /* Round to page boundary */
 232         vga_bios_size = (vga_bios_size + TARGET_PAGE_SIZE - 1) &
 233             TARGET_PAGE_MASK;
 234     }
 235
 236     if (linux_boot) {
 237         uint64_t lowaddr = 0;
 238         int bswap_needed;
 239
 240 #ifdef BSWAP_NEEDED
 241         bswap_needed = 1;
 242 #else
 243         bswap_needed = 0;
 244 #endif
 245         kernel_base = KERNEL_LOAD_ADDR;
 246         kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
 247                                NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
 248         if (kernel_size < 0)
 249             kernel_size = load_aout(kernel_filename, kernel_base,
 250                                     ram_size - kernel_base, bswap_needed,
 251                                     TARGET_PAGE_SIZE);
 252         if (kernel_size < 0)
 253             kernel_size = load_image_targphys(kernel_filename,
 254                                               kernel_base,
 255                                               ram_size - kernel_base);
 256         if (kernel_size < 0) {
 257             hw_error("qemu: could not load kernel '%s'\n",
 258                       kernel_filename);
 259             exit(1);
 260         }
 261         /* load initrd */
 262         if (initrd_filename) {
 263             initrd_base = INITRD_LOAD_ADDR;
 264             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 265                                               ram_size - initrd_base);
 266             if (initrd_size < 0) {
 267                 hw_error("qemu: could not load initial ram disk '%s'\n",
 268                          initrd_filename);
 269                 exit(1);
 270             }
 271         } else {
 272             initrd_base = 0;
 273             initrd_size = 0;
 274         }
 275         ppc_boot_device = 'm';
 276     } else {
 277         kernel_base = 0;
 278         kernel_size = 0;
 279         initrd_base = 0;
 280         initrd_size = 0;
 281         ppc_boot_device = '\0';
 282         for (i = 0; boot_device[i] != '\0'; i++) {
 283             /* TOFIX: for now, the second IDE channel is not properly
 284              *        used by OHW. The Mac floppy disk are not emulated.
 285              *        For now, OHW cannot boot from the network.
 286              */
 287 #if 0
 288             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 289                 ppc_boot_device = boot_device[i];
 290                 break;
 291             }
 292 #else
 293             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 294                 ppc_boot_device = boot_device[i];
 295                 break;
 296             }
 297 #endif
 298         }
 299         if (ppc_boot_device == '\0') {
 300             fprintf(stderr, "No valid boot device for G3 Beige machine\n");
 301             exit(1);
 302         }
 303     }
 304
 305     isa_mem_base = 0x80000000;
 306
 307     /* Register 2 MB of ISA IO space */
 308     isa_mmio_init(0xfe000000, 0x00200000, 1);
 309
 310     /* XXX: we register only 1 output pin for heathrow PIC */
 311     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 312     heathrow_irqs[0] =
 313         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 314     /* Connect the heathrow PIC outputs to the 6xx bus */
 315     for (i = 0; i < smp_cpus; i++) {
 316         switch (PPC_INPUT(env)) {
 317         case PPC_FLAGS_INPUT_6xx:
 318             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 319             heathrow_irqs[i][0] =
 320                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 321             break;
 322         default:
 323             hw_error("Bus model not supported on OldWorld Mac machine\n");
 324         }
 325     }
 326
 327     /* init basic PC hardware */
 328     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 329         hw_error("Only 6xx bus is supported on heathrow machine\n");
 330     }
 331     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 332     pci_bus = pci_grackle_init(0xfec00000, pic);
 333     pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size);
 334
 335     escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
 336                                serial_hds[1], ESCC_CLOCK, 4);
 337
 338     for(i = 0; i < nb_nics; i++)
 339         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 340
 341
 342     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 343         fprintf(stderr, "qemu: too many IDE bus\n");
 344         exit(1);
 345     }
 346
 347     /* First IDE channel is a MAC IDE on the MacIO bus */
 348     hd[0] = drive_get(IF_IDE, 0, 0);
 349     hd[1] = drive_get(IF_IDE, 0, 1);
 350     dbdma = DBDMA_init(&dbdma_mem_index);
 351     ide_mem_index[0] = -1;
 352     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
 353
 354     /* Second IDE channel is a CMD646 on the PCI bus */
 355     hd[0] = drive_get(IF_IDE, 1, 0);
 356     hd[1] = drive_get(IF_IDE, 1, 1);
 357     hd[3] = hd[2] = NULL;
 358     pci_cmd646_ide_init(pci_bus, hd, 0);
 359
 360     /* cuda also initialize ADB */
 361     cuda_init(&cuda_mem_index, pic[0x12]);
 362
 363     adb_kbd_init(&adb_bus);
 364     adb_mouse_init(&adb_bus);
 365
 366     nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4);
 367     pmac_format_nvram_partition(nvr, 0x2000);
 368
 369     macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index,
 370                dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index,
 371                escc_mem_index);
 372
 373     if (usb_enabled) {
 374         usb_ohci_init_pci(pci_bus, -1);
 375     }
 376
 377     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 378         graphic_depth = 15;
 379
 380     /* No PCI init: the BIOS will do it */
 381
 382     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 383     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 384     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 385     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 386     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 387     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 388     if (kernel_cmdline) {
 389         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 390         pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 391     } else {
 392         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 393     }
 394     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 395     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 396     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 397
 398     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 399     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 400     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 401
 402     if (kvm_enabled()) {
 403 #ifdef CONFIG_KVM
 404         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
 405 #endif
 406     } else {
 407         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
 408     }
 409
 410     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 411 }
 412
 413 static QEMUMachine heathrow_machine = {
 414     .name = "g3beige",
 415     .desc = "Heathrow based PowerMAC",
 416     .init = ppc_heathrow_init,
 417     .max_cpus = MAX_CPUS,
 418 #ifndef TARGET_PPC64
 419     .is_default = 1,
 420 #endif
 421 };
 422
 423 static void heathrow_machine_init(void)
 424 {
 425     qemu_register_machine(&heathrow_machine);
 426 }
 427
 428 machine_init(heathrow_machine_init);