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git.proxmox.com Git - qemu.git/blob - hw/ppc_prep.c
42ae22e865537f65fc33a513dcf70b36f875ab43
2 * QEMU PPC PREP hardware System Emulator
4 * Copyright (c) 2003-2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 //#define HARD_DEBUG_PPC_IO
28 //#define DEBUG_PPC_IO
33 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
37 #if defined (HARD_DEBUG_PPC_IO)
38 #define PPC_IO_DPRINTF(fmt, args...) \
41 fprintf(logfile, "%s: " fmt, __func__ , ##args); \
43 printf("%s : " fmt, __func__ , ##args); \
46 #elif defined (DEBUG_PPC_IO)
47 #define PPC_IO_DPRINTF(fmt, args...) \
50 fprintf(logfile, "%s: " fmt, __func__ , ##args); \
54 #define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
57 #define BIOS_FILENAME "ppc_rom.bin"
58 #define LINUX_BOOT_FILENAME "linux_boot.bin"
60 #define KERNEL_LOAD_ADDR 0x00000000
61 #define KERNEL_STACK_ADDR 0x00400000
62 #define INITRD_LOAD_ADDR 0x00800000
64 int load_kernel(const char *filename
, uint8_t *addr
,
70 fd
= open(filename
, O_RDONLY
);
74 /* load 16 bit code */
75 if (read(fd
, real_addr
, 512) != 512)
77 setup_sects
= real_addr
[0x1F1];
80 if (read(fd
, real_addr
+ 512, setup_sects
* 512) !=
84 /* load 32 bit code */
85 size
= read(fd
, addr
, 16 * 1024 * 1024);
95 static const int ide_iobase
[2] = { 0x1f0, 0x170 };
96 static const int ide_iobase2
[2] = { 0x3f6, 0x376 };
97 static const int ide_irq
[2] = { 13, 13 };
99 #define NE2000_NB_MAX 6
101 static uint32_t ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
102 static int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
104 /* IO ports emulation */
105 #define PPC_IO_BASE 0x80000000
107 static void PPC_io_writeb (target_phys_addr_t addr
, uint32_t value
)
109 /* Don't polute serial port output */
111 if ((addr
< 0x800003F0 || addr
> 0x80000400) &&
112 (addr
< 0x80000074 || addr
> 0x80000077) &&
113 (addr
< 0x80000020 || addr
> 0x80000021) &&
114 (addr
< 0x800000a0 || addr
> 0x800000a1) &&
115 (addr
< 0x800001f0 || addr
> 0x800001f7) &&
116 (addr
< 0x80000170 || addr
> 0x80000177))
119 PPC_IO_DPRINTF("0x%08x => 0x%02x\n", addr
- PPC_IO_BASE
, value
);
121 cpu_outb(NULL
, addr
- PPC_IO_BASE
, value
);
124 static uint32_t PPC_io_readb (target_phys_addr_t addr
)
126 uint32_t ret
= cpu_inb(NULL
, addr
- PPC_IO_BASE
);
129 if ((addr
< 0x800003F0 || addr
> 0x80000400) &&
130 (addr
< 0x80000074 || addr
> 0x80000077) &&
131 (addr
< 0x80000020 || addr
> 0x80000021) &&
132 (addr
< 0x800000a0 || addr
> 0x800000a1) &&
133 (addr
< 0x800001f0 || addr
> 0x800001f7) &&
134 (addr
< 0x80000170 || addr
> 0x80000177) &&
135 (addr
< 0x8000060 || addr
> 0x8000064))
138 PPC_IO_DPRINTF("0x%08x <= 0x%02x\n", addr
- PPC_IO_BASE
, ret
);
144 static void PPC_io_writew (target_phys_addr_t addr
, uint32_t value
)
146 if ((addr
< 0x800001f0 || addr
> 0x800001f7) &&
147 (addr
< 0x80000170 || addr
> 0x80000177)) {
148 PPC_IO_DPRINTF("0x%08x => 0x%04x\n", addr
- PPC_IO_BASE
, value
);
150 cpu_outw(NULL
, addr
- PPC_IO_BASE
, value
);
153 static uint32_t PPC_io_readw (target_phys_addr_t addr
)
155 uint32_t ret
= cpu_inw(NULL
, addr
- PPC_IO_BASE
);
157 if ((addr
< 0x800001f0 || addr
> 0x800001f7) &&
158 (addr
< 0x80000170 || addr
> 0x80000177)) {
159 PPC_IO_DPRINTF("0x%08x <= 0x%04x\n", addr
- PPC_IO_BASE
, ret
);
165 static void PPC_io_writel (target_phys_addr_t addr
, uint32_t value
)
167 PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr
- PPC_IO_BASE
, value
);
168 cpu_outl(NULL
, addr
- PPC_IO_BASE
, value
);
171 static uint32_t PPC_io_readl (target_phys_addr_t addr
)
173 uint32_t ret
= cpu_inl(NULL
, addr
- PPC_IO_BASE
);
175 PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr
- PPC_IO_BASE
, ret
);
180 static CPUWriteMemoryFunc
*PPC_io_write
[] = {
186 static CPUReadMemoryFunc
*PPC_io_read
[] = {
192 /* Read-only register (?) */
193 static void _PPC_ioB_write (target_phys_addr_t addr
, uint32_t value
)
195 // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
198 static uint32_t _PPC_ioB_read (target_phys_addr_t addr
)
202 if (addr
== 0xBFFFFFF0)
203 retval
= pic_intack_read(NULL
);
204 // printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
209 static CPUWriteMemoryFunc
*PPC_ioB_write
[] = {
215 static CPUReadMemoryFunc
*PPC_ioB_read
[] = {
222 static CPUWriteMemoryFunc
*PPC_io3_write
[] = {
228 static CPUReadMemoryFunc
*PPC_io3_read
[] = {
235 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
236 static uint8_t PREP_fake_io
[2];
237 static uint8_t NVRAM_lock
;
239 static void PREP_io_write (void *opaque
, uint32_t addr
, uint32_t val
)
241 PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr
- PPC_IO_BASE
, val
);
242 PREP_fake_io
[addr
- 0x0398] = val
;
245 static uint32_t PREP_io_read (void *opaque
, uint32_t addr
)
247 PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr
- PPC_IO_BASE
, PREP_fake_io
[addr
- 0x0398]);
248 return PREP_fake_io
[addr
- 0x0398];
251 static uint8_t syscontrol
;
253 static void PREP_io_800_writeb (void *opaque
, uint32_t addr
, uint32_t val
)
255 PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr
- PPC_IO_BASE
, val
);
258 /* Special port 92 */
259 /* Check soft reset asked */
261 printf("Soft reset asked... Stop emulation\n");
266 printf("Little Endian mode isn't supported (yet ?)\n");
271 /* Hardfile light register: don't care */
274 /* Password protect 1 register */
278 /* Password protect 2 register */
282 /* L2 invalidate register: don't care */
285 /* system control register */
289 /* I/O map type register */
291 printf("No support for non-continuous I/O map mode\n");
300 static uint32_t PREP_io_800_readb (void *opaque
, uint32_t addr
)
302 uint32_t retval
= 0xFF;
306 /* Special port 92 */
310 /* Equipment present register:
312 * no upgrade processor
313 * no cards in PCI slots
323 /* system control register
324 * 7 - 6 / 1 - 0: L2 cache enable
330 retval
= 0x03; /* no L2 cache */
333 /* I/O map type register */
339 PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr
- PPC_IO_BASE
, retval
);
344 #define NVRAM_SIZE 0x2000
345 #define NVRAM_END 0x1FF0
346 #define NVRAM_OSAREA_SIZE 512
347 #define NVRAM_CONFSIZE 1024
349 static inline void NVRAM_set_byte (m48t59_t
*nvram
, uint32_t addr
, uint8_t value
)
351 m48t59_set_addr(nvram
, addr
);
352 m48t59_write(nvram
, value
);
355 static inline uint8_t NVRAM_get_byte (m48t59_t
*nvram
, uint32_t addr
)
357 m48t59_set_addr(nvram
, addr
);
358 return m48t59_read(nvram
);
361 static inline void NVRAM_set_word (m48t59_t
*nvram
, uint32_t addr
, uint16_t value
)
363 m48t59_set_addr(nvram
, addr
);
364 m48t59_write(nvram
, value
>> 8);
365 m48t59_set_addr(nvram
, addr
+ 1);
366 m48t59_write(nvram
, value
& 0xFF);
369 static inline uint16_t NVRAM_get_word (m48t59_t
*nvram
, uint32_t addr
)
373 m48t59_set_addr(nvram
, addr
);
374 tmp
= m48t59_read(nvram
) << 8;
375 m48t59_set_addr(nvram
, addr
+ 1);
376 tmp
|= m48t59_read(nvram
);
381 static inline void NVRAM_set_lword (m48t59_t
*nvram
, uint32_t addr
,
384 m48t59_set_addr(nvram
, addr
);
385 m48t59_write(nvram
, value
>> 24);
386 m48t59_set_addr(nvram
, addr
+ 1);
387 m48t59_write(nvram
, (value
>> 16) & 0xFF);
388 m48t59_set_addr(nvram
, addr
+ 2);
389 m48t59_write(nvram
, (value
>> 8) & 0xFF);
390 m48t59_set_addr(nvram
, addr
+ 3);
391 m48t59_write(nvram
, value
& 0xFF);
394 static inline uint32_t NVRAM_get_lword (m48t59_t
*nvram
, uint32_t addr
)
398 m48t59_set_addr(nvram
, addr
);
399 tmp
= m48t59_read(nvram
) << 24;
400 m48t59_set_addr(nvram
, addr
+ 1);
401 tmp
|= m48t59_read(nvram
) << 16;
402 m48t59_set_addr(nvram
, addr
+ 2);
403 tmp
|= m48t59_read(nvram
) << 8;
404 m48t59_set_addr(nvram
, addr
+ 3);
405 tmp
|= m48t59_read(nvram
);
410 static uint16_t NVRAM_crc_update (uint16_t prev
, uint16_t value
)
413 uint16_t pd
, pd1
, pd2
;
418 pd2
= ((pd
>> 4) & 0x000F) ^ pd1
;
419 tmp
^= (pd1
<< 3) | (pd1
<< 8);
420 tmp
^= pd2
| (pd2
<< 7) | (pd2
<< 12);
425 static void NVRAM_set_crc (m48t59_t
*nvram
, uint32_t addr
,
426 uint32_t start
, uint32_t count
)
429 uint16_t crc
= 0xFFFF;
435 for (i
= 0; i
!= count
; i
++) {
436 crc
= NVRAM_crc_update(crc
, NVRAM_get_word(nvram
, start
+ i
));
439 crc
= NVRAM_crc_update(crc
, NVRAM_get_byte(nvram
, start
+ i
) << 8);
441 NVRAM_set_word(nvram
, addr
, crc
);
444 static void prep_NVRAM_init (void)
448 nvram
= m48t59_init(8, 0x0074, NVRAM_SIZE
);
450 /* 0x00: NVRAM size in kB */
451 NVRAM_set_word(nvram
, 0x00, NVRAM_SIZE
>> 10);
452 /* 0x02: NVRAM version */
453 NVRAM_set_byte(nvram
, 0x02, 0x01);
454 /* 0x03: NVRAM revision */
455 NVRAM_set_byte(nvram
, 0x03, 0x01);
457 NVRAM_set_byte(nvram
, 0x08, 0x00); /* Unknown */
459 NVRAM_set_byte(nvram
, 0x09, 'B'); /* Big-endian */
460 /* 0x0A: OSArea usage */
461 NVRAM_set_byte(nvram
, 0x0A, 0x00); /* Empty */
463 NVRAM_set_byte(nvram
, 0x0B, 0x00); /* Normal */
464 /* Restart block description record */
465 /* 0x0C: restart block version */
466 NVRAM_set_word(nvram
, 0x0C, 0x01);
467 /* 0x0E: restart block revision */
468 NVRAM_set_word(nvram
, 0x0E, 0x01);
469 /* 0x20: restart address */
470 NVRAM_set_lword(nvram
, 0x20, 0x00);
471 /* 0x24: save area address */
472 NVRAM_set_lword(nvram
, 0x24, 0x00);
473 /* 0x28: save area length */
474 NVRAM_set_lword(nvram
, 0x28, 0x00);
475 /* 0x1C: checksum of restart block */
476 NVRAM_set_crc(nvram
, 0x1C, 0x0C, 32);
478 /* Security section */
479 /* Set all to zero */
480 /* 0xC4: pointer to global environment area */
481 NVRAM_set_lword(nvram
, 0xC4, 0x0100);
482 /* 0xC8: size of global environment area */
483 NVRAM_set_lword(nvram
, 0xC8,
484 NVRAM_END
- NVRAM_OSAREA_SIZE
- NVRAM_CONFSIZE
- 0x0100);
485 /* 0xD4: pointer to configuration area */
486 NVRAM_set_lword(nvram
, 0xD4, NVRAM_END
- NVRAM_CONFSIZE
);
487 /* 0xD8: size of configuration area */
488 NVRAM_set_lword(nvram
, 0xD8, NVRAM_CONFSIZE
);
489 /* 0xE8: pointer to OS specific area */
490 NVRAM_set_lword(nvram
, 0xE8,
491 NVRAM_END
- NVRAM_CONFSIZE
- NVRAM_OSAREA_SIZE
);
492 /* 0xD8: size of OS specific area */
493 NVRAM_set_lword(nvram
, 0xEC, NVRAM_OSAREA_SIZE
);
495 /* Configuration area */
497 // NVRAM_set_lword(nvram, 0x1FFC, 0x50);
499 /* 0x04: checksum 0 => OS area */
500 NVRAM_set_crc(nvram
, 0x04, 0x00,
501 NVRAM_END
- NVRAM_CONFSIZE
- NVRAM_OSAREA_SIZE
);
502 /* 0x06: checksum of config area */
503 NVRAM_set_crc(nvram
, 0x06, NVRAM_END
- NVRAM_CONFSIZE
, NVRAM_CONFSIZE
);
506 int load_initrd (const char *filename
, uint8_t *addr
)
510 printf("Load initrd\n");
511 fd
= open(filename
, O_RDONLY
);
514 size
= read(fd
, addr
, 16 * 1024 * 1024);
518 printf("Load initrd: %d\n", size
);
522 printf("Load initrd failed\n");
526 /* Quick hack for PPC memory infos... */
527 static void put_long (void *addr
, uint32_t l
)
530 pos
[0] = (l
>> 24) & 0xFF;
531 pos
[1] = (l
>> 16) & 0xFF;
532 pos
[2] = (l
>> 8) & 0xFF;
536 /* bootloader infos are in the form:
538 * uint32_t TAG_size (from TAG to next TAG).
542 #if !defined (USE_OPEN_FIRMWARE)
543 static void *set_bootinfo_tag (void *addr
, uint32_t tag
, uint32_t size
,
550 put_long(pos
, size
+ 8);
552 memcpy(pos
, data
, size
);
559 typedef struct boot_dev_t
{
560 const unsigned char *name
;
565 static boot_dev_t boot_devs
[] =
567 { "/dev/fd0", 2, 0, },
568 { "/dev/fd1", 2, 1, },
569 { "/dev/hda", 3, 1, },
570 // { "/dev/ide/host0/bus0/target0/lun0/part1", 3, 1, },
571 // { "/dev/hdc", 22, 0, },
572 { "/dev/hdc", 22, 1, },
573 { "/dev/ram0 init=/linuxrc", 1, 0, },
577 * BEPI : bloc virtual address
578 * BL : area size bits (128 kB is 0, 256 1, 512 3, ...
581 * BPRN : bloc real address align on 4MB boundary
582 * WIMG : cache access mode : not used
583 * PP : protection bits
585 static void setup_BAT (CPUPPCState
*env
, int BAT
,
586 uint32_t virtual, uint32_t physical
,
587 uint32_t size
, int Vs
, int Vp
, int PP
)
589 uint32_t sz_bits
, tmp_sz
, align
, tmp
;
593 for (tmp_sz
= size
/ 131072; tmp_sz
!= 1; tmp_sz
= tmp_sz
>> 1) {
594 sz_bits
= (sz_bits
<< 1) + 1;
597 tmp
= virtual & ~(align
- 1); /* Align virtual area start */
598 tmp
|= sz_bits
<< 2; /* Fix BAT size */
599 tmp
|= Vs
<< 1; /* Supervisor access */
600 tmp
|= Vp
; /* User access */
601 env
->DBAT
[0][BAT
] = tmp
;
602 env
->IBAT
[0][BAT
] = tmp
;
603 tmp
= physical
& ~(align
- 1); /* Align physical area start */
604 tmp
|= 0; /* Don't care about WIMG */
605 tmp
|= PP
; /* Protection */
606 env
->DBAT
[1][BAT
] = tmp
;
607 env
->IBAT
[1][BAT
] = tmp
;
608 printf("Set BATU0 to 0x%08x BATL0 to 0x%08x\n",
609 env
->DBAT
[0][BAT
], env
->DBAT
[1][BAT
]);
612 static void VGA_printf (uint8_t *s
)
615 unsigned int format_width
, i
;
617 uint16_t arg
, digit
, nibble
;
620 arg_ptr
= (uint16_t *)((void *)&s
);
623 while ((c
= *s
) != '\0') {
627 } else if (in_format
) {
628 if ((c
>= '0') && (c
<= '9')) {
629 format_width
= (format_width
* 10) + (c
- '0');
630 } else if (c
== 'x') {
631 arg_ptr
++; // increment to next arg
633 if (format_width
== 0)
635 digit
= format_width
- 1;
636 for (i
= 0; i
< format_width
; i
++) {
637 nibble
= (arg
>> (4 * digit
)) & 0x000f;
639 PPC_io_writeb(PPC_IO_BASE
+ 0x500, nibble
+ '0');
641 PPC_io_writeb(PPC_IO_BASE
+ 0x500, nibble
+ 'A');
646 //else if (c == 'd') {
650 PPC_io_writeb(PPC_IO_BASE
+ 0x500, c
);
656 static void VGA_init (void)
658 /* Basic VGA init, inspired by plex86 VGAbios */
659 printf("Init VGA...\n");
661 /* switch to color mode and enable CPU access 480 lines */
662 PPC_io_writeb(PPC_IO_BASE
+ 0x3C2, 0xC3);
663 /* more than 64k 3C4/04 */
664 PPC_io_writeb(PPC_IO_BASE
+ 0x3C4, 0x04);
665 PPC_io_writeb(PPC_IO_BASE
+ 0x3C5, 0x02);
667 VGA_printf("PPC VGA BIOS...\n");
670 extern CPUPPCState
*global_env
;
672 void PPC_init_hw (/*CPUPPCState *env,*/ uint32_t mem_size
,
673 uint32_t kernel_addr
, uint32_t kernel_size
,
674 uint32_t stack_addr
, int boot_device
,
675 const unsigned char *initrd_file
)
677 CPUPPCState
*env
= global_env
;
679 #if !defined (USE_OPEN_FIRMWARE)
684 printf("RAM size: %u 0x%08x (%u)\n", mem_size
, mem_size
, mem_size
>> 20);
685 #if defined (USE_OPEN_FIRMWARE)
686 setup_memory(env
, mem_size
);
689 /* Fake bootloader */
693 *((uint32_t *)(phys_ram_base
+ kernel_addr
));
695 uint32_t offset
= 12;
697 env
->nip
= kernel_addr
+ offset
;
698 printf("Start address: 0x%08x\n", env
->nip
);
700 /* Set up msr according to PREP specification */
703 msr_pr
= 0; /* Start in supervisor mode */
705 msr_fe0
= msr_fe1
= 0;
709 msr_le
= msr_ile
= 0;
710 env
->gpr
[1] = stack_addr
; /* Let's have a stack */
712 env
->gpr
[8] = kernel_addr
;
713 /* There is a bug in 2.4 kernels:
714 * if a decrementer exception is pending when it enables msr_ee,
715 * it's not ready to handle it...
717 env
->decr
= 0xFFFFFFFF;
718 p
= (void *)(phys_ram_base
+ kernel_addr
);
719 #if !defined (USE_OPEN_FIRMWARE)
720 /* Let's register the whole memory available only in supervisor mode */
721 setup_BAT(env
, 0, 0x00000000, 0x00000000, mem_size
, 1, 0, 2);
722 /* Avoid open firmware init call (to get a console)
723 * This will make the kernel think we are a PREP machine...
725 put_long(p
, 0xdeadc0de);
726 /* Build a real stack room */
727 p
= (void *)(phys_ram_base
+ stack_addr
);
728 put_long(p
, stack_addr
);
731 /* Pretend there are no residual data */
733 if (initrd_file
!= NULL
) {
735 env
->gpr
[4] = (kernel_addr
+ kernel_size
+ 4095) & ~4095;
736 size
= load_initrd(initrd_file
,
737 (void *)((uint32_t)phys_ram_base
+ env
->gpr
[4]));
740 env
->gpr
[4] = env
->gpr
[5] = 0;
745 printf("Initrd loaded at 0x%08x (%d) (0x%08x 0x%08x)\n",
746 env
->gpr
[4], env
->gpr
[5], kernel_addr
, kernel_size
);
748 env
->gpr
[4] = env
->gpr
[5] = 0;
750 /* We have to put bootinfos after the BSS
751 * The BSS starts after the kernel end.
754 p
= (void *)(((uint32_t)phys_ram_base
+ kernel_addr
+
755 kernel_size
+ (1 << 20) - 1) & ~((1 << 20) - 1));
757 p
= (void *)((uint32_t)phys_ram_base
+ kernel_addr
+ 0x400000);
760 fprintf(logfile
, "bootinfos: %p 0x%08x\n",
761 p
, (uint32_t)p
- (uint32_t)phys_ram_base
);
763 printf("bootinfos: %p 0x%08x\n",
764 p
, (uint32_t)p
- (uint32_t)phys_ram_base
);
766 /* Command line: let's put it after bootinfos */
768 sprintf(p
+ 0x1000, "console=ttyS0,9600 root=%02x%02x mem=%dM",
769 boot_devs
[boot_device
- 'a'].major
,
770 boot_devs
[boot_device
- 'a'].minor
,
773 sprintf(p
+ 0x1000, "console=ttyS0,9600 console=tty0 root=%s mem=%dM",
774 boot_devs
[boot_device
- 'a'].name
,
777 env
->gpr
[6] = (uint32_t)p
+ 0x1000 - (uint32_t)phys_ram_base
;
778 env
->gpr
[7] = env
->gpr
[6] + strlen(p
+ 0x1000);
780 fprintf(logfile
, "cmdline: %p 0x%08x [%s]\n",
781 p
+ 0x1000, env
->gpr
[6], p
+ 0x1000);
783 printf("cmdline: %p 0x%08x [%s]\n",
784 p
+ 0x1000, env
->gpr
[6], p
+ 0x1000);
787 p
= set_bootinfo_tag(p
, 0x1010, 0, 0);
789 p
= set_bootinfo_tag(p
, 0x1012, env
->gpr
[7] - env
->gpr
[6],
790 (void *)(env
->gpr
[6] + (uint32_t)phys_ram_base
));
793 tmp
[0] = (mem_size
>> 24) & 0xFF;
794 tmp
[1] = (mem_size
>> 16) & 0xFF;
795 tmp
[2] = (mem_size
>> 8) & 0xFF;
796 tmp
[3] = mem_size
& 0xFF;
797 p
= set_bootinfo_tag(p
, 0x1017, 4, tmpi
);
799 tmp
[0] = (env
->gpr
[4] >> 24) & 0xFF;
800 tmp
[1] = (env
->gpr
[4] >> 16) & 0xFF;
801 tmp
[2] = (env
->gpr
[4] >> 8) & 0xFF;
802 tmp
[3] = env
->gpr
[4] & 0xFF;
803 tmp
[4] = (env
->gpr
[5] >> 24) & 0xFF;
804 tmp
[5] = (env
->gpr
[5] >> 16) & 0xFF;
805 tmp
[6] = (env
->gpr
[5] >> 8) & 0xFF;
806 tmp
[7] = env
->gpr
[5] & 0xFF;
807 p
= set_bootinfo_tag(p
, 0x1014, 8, tmpi
);
808 env
->gpr
[4] = env
->gpr
[5] = 0;
810 p
= set_bootinfo_tag(p
, 0x1011, 0, 0);
813 * kernel is loaded at kernel_addr and wants to be seen at 0x01000000
815 setup_BAT(env
, 0, 0x01000000, kernel_addr
, 0x00400000, 1, 0, 2);
819 *((uint32_t *)(phys_ram_base
+ kernel_addr
));
821 uint32_t offset
= 12;
823 env
->nip
= 0x01000000 | (kernel_addr
+ offset
);
824 printf("Start address: 0x%08x\n", env
->nip
);
826 env
->gpr
[1] = env
->nip
+ (1 << 22);
827 p
= (void *)(phys_ram_base
+ stack_addr
);
828 put_long(p
- 32, stack_addr
);
830 printf("Kernel starts at 0x%08x stack 0x%08x\n", env
->nip
, env
->gpr
[1]);
831 /* We want all lower address not to be translated */
832 setup_BAT(env
, 1, 0x00000000, 0x00000000, 0x010000000, 1, 1, 2);
833 /* We also need a BAT to access OF */
834 setup_BAT(env
, 2, 0xFFFE0000, mem_size
- 131072, 131072, 1, 0, 1);
835 /* Setup OF entry point */
838 p
= (char *)phys_ram_base
+ mem_size
- 131072;
839 /* Special opcode to call OF */
840 *p
++ = 0x18; *p
++ = 0x00; *p
++ = 0x00; *p
++ = 0x02;
842 *p
++ = 0x4E; *p
++ = 0x80; *p
++ = 0x00; *p
++ = 0x20;
844 env
->gpr
[5] = 0xFFFE0000;
845 /* Register translations */
847 OF_transl_t translations
[3] = {
848 { 0x01000000, 0x00400000, kernel_addr
, 0x00000002, },
849 { 0x00000000, 0x01000000, 0x00000000, 0x00000002, },
850 { 0xFFFE0000, 0x00020000, mem_size
- (128 * 1024),
853 OF_register_translations(3, translations
);
855 /* Quite artificial, for now */
856 OF_register_bus("isa", "isa");
857 OF_register_serial("isa", "serial", 4, 0x3f8);
858 OF_register_stdio("serial", "serial");
859 /* Set up RTAS service */
861 /* Command line: let's put it just over the stack */
864 p
= (void *)(((uint32_t)phys_ram_base
+ kernel_addr
+
865 kernel_size
+ (1 << 20) - 1) & ~((1 << 20) - 1));
867 p
= (void *)((uint32_t)phys_ram_base
+ kernel_addr
+ 0x400000);
870 sprintf(p
, "console=ttyS0,9600 root=%02x%02x mem=%dM",
871 boot_devs
[boot_device
- 'a'].major
,
872 boot_devs
[boot_device
- 'a'].minor
,
875 sprintf(p
, "console=ttyS0,9600 root=%s mem=%dM ne2000=0x300,9",
876 boot_devs
[boot_device
- 'a'].name
,
879 OF_register_bootargs(p
);
884 void PPC_end_init (void)
889 /* PC hardware initialisation */
890 void ppc_prep_init(int ram_size
, int vga_ram_size
, int boot_device
,
891 DisplayState
*ds
, const char **fd_filename
, int snapshot
,
892 const char *kernel_filename
, const char *kernel_cmdline
,
893 const char *initrd_filename
)
897 int ret
, linux_boot
, initrd_size
, i
, nb_nics1
, fd
;
899 linux_boot
= (kernel_filename
!= NULL
);
902 cpu_register_physical_memory(0, ram_size
, 0);
905 /* now we can load the kernel */
906 ret
= load_image(kernel_filename
, phys_ram_base
+ KERNEL_LOAD_ADDR
);
908 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
915 if (initrd_filename
) {
916 initrd_size
= load_image(initrd_filename
, phys_ram_base
+ INITRD_LOAD_ADDR
);
917 if (initrd_size
< 0) {
918 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
924 PPC_init_hw(/*env,*/ ram_size
, KERNEL_LOAD_ADDR
, ret
,
925 KERNEL_STACK_ADDR
, boot_device
, initrd_filename
);
928 // snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
929 snprintf(buf
, sizeof(buf
), "%s", BIOS_FILENAME
);
930 printf("load BIOS at %p\n", phys_ram_base
+ 0x000f0000);
931 ret
= load_image(buf
, phys_ram_base
+ 0x000f0000);
932 if (ret
!= 0x10000) {
933 fprintf(stderr
, "qemu: could not load PPC bios '%s' (%d)\n%m\n",
939 /* init basic PC hardware */
940 vga_initialize(ds
, phys_ram_base
+ ram_size
, ram_size
,
944 // pit_init(0x40, 0);
946 fd
= serial_open_device();
947 serial_init(0x3f8, 4, fd
);
950 if (nb_nics1
> NE2000_NB_MAX
)
951 nb_nics1
= NE2000_NB_MAX
;
952 for(i
= 0; i
< nb_nics1
; i
++) {
953 ne2000_init(ne2000_io
[i
], ne2000_irq
[i
], &nd_table
[i
]);
957 for(i
= 0; i
< 2; i
++) {
958 ide_init(ide_iobase
[i
], ide_iobase2
[i
], ide_irq
[i
],
959 bs_table
[2 * i
], bs_table
[2 * i
+ 1]);
966 fdctrl_init(6, 2, 0, 0x3f0, fd_table
);
968 /* Register 64 kB of IO space */
969 PPC_io_memory
= cpu_register_io_memory(0, PPC_io_read
, PPC_io_write
);
970 cpu_register_physical_memory(0x80000000, 0x10000, PPC_io_memory
);
971 /* Register fake IO ports for PREP */
972 register_ioport_read(0x398, 2, 1, &PREP_io_read
, NULL
);
973 register_ioport_write(0x398, 2, 1, &PREP_io_write
, NULL
);
974 /* System control ports */
975 register_ioport_write(0x0092, 0x1, 1, &PREP_io_800_writeb
, NULL
);
976 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb
, NULL
);
977 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb
, NULL
);
978 /* PCI intack location (0xfef00000 / 0xbffffff0) */
979 PPC_io_memory
= cpu_register_io_memory(0, PPC_ioB_read
, PPC_ioB_write
);
980 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory
);
981 // cpu_register_physical_memory(0xFEF00000, 0x4, PPC_io_memory);