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[qemu.git] / hw / ppc_prep.c
1 /*
2 * QEMU PPC PREP hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "nvram.h"
26 #include "pc.h"
27 #include "fdc.h"
28 #include "net.h"
29 #include "sysemu.h"
30 #include "isa.h"
31 #include "pci.h"
32 #include "ppc.h"
33 #include "boards.h"
34 #include "qemu-log.h"
35 #include "ide.h"
36 #include "loader.h"
37
38 //#define HARD_DEBUG_PPC_IO
39 //#define DEBUG_PPC_IO
40
41 /* SMP is not enabled, for now */
42 #define MAX_CPUS 1
43
44 #define MAX_IDE_BUS 2
45
46 #define BIOS_SIZE (1024 * 1024)
47 #define BIOS_FILENAME "ppc_rom.bin"
48 #define KERNEL_LOAD_ADDR 0x01000000
49 #define INITRD_LOAD_ADDR 0x01800000
50
51 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
52 #define DEBUG_PPC_IO
53 #endif
54
55 #if defined (HARD_DEBUG_PPC_IO)
56 #define PPC_IO_DPRINTF(fmt, ...) \
57 do { \
58 if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
59 qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
60 } else { \
61 printf("%s : " fmt, __func__ , ## __VA_ARGS__); \
62 } \
63 } while (0)
64 #elif defined (DEBUG_PPC_IO)
65 #define PPC_IO_DPRINTF(fmt, ...) \
66 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
67 #else
68 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
69 #endif
70
71 /* Constants for devices init */
72 static const int ide_iobase[2] = { 0x1f0, 0x170 };
73 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
74 static const int ide_irq[2] = { 13, 13 };
75
76 #define NE2000_NB_MAX 6
77
78 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
79 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
80
81 //static PITState *pit;
82
83 /* ISA IO ports bridge */
84 #define PPC_IO_BASE 0x80000000
85
86 #if 0
87 /* Speaker port 0x61 */
88 static int speaker_data_on;
89 static int dummy_refresh_clock;
90 #endif
91
92 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
93 {
94 #if 0
95 speaker_data_on = (val >> 1) & 1;
96 pit_set_gate(pit, 2, val & 1);
97 #endif
98 }
99
100 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
101 {
102 #if 0
103 int out;
104 out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
105 dummy_refresh_clock ^= 1;
106 return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
107 (dummy_refresh_clock << 4);
108 #endif
109 return 0;
110 }
111
112 /* PCI intack register */
113 /* Read-only register (?) */
114 static void _PPC_intack_write (void *opaque,
115 target_phys_addr_t addr, uint32_t value)
116 {
117 #if 0
118 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
119 value);
120 #endif
121 }
122
123 static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
124 {
125 uint32_t retval = 0;
126
127 if ((addr & 0xf) == 0)
128 retval = pic_intack_read(isa_pic);
129 #if 0
130 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
131 retval);
132 #endif
133
134 return retval;
135 }
136
137 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
138 {
139 return _PPC_intack_read(addr);
140 }
141
142 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
143 {
144 #ifdef TARGET_WORDS_BIGENDIAN
145 return bswap16(_PPC_intack_read(addr));
146 #else
147 return _PPC_intack_read(addr);
148 #endif
149 }
150
151 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
152 {
153 #ifdef TARGET_WORDS_BIGENDIAN
154 return bswap32(_PPC_intack_read(addr));
155 #else
156 return _PPC_intack_read(addr);
157 #endif
158 }
159
160 static CPUWriteMemoryFunc * const PPC_intack_write[] = {
161 &_PPC_intack_write,
162 &_PPC_intack_write,
163 &_PPC_intack_write,
164 };
165
166 static CPUReadMemoryFunc * const PPC_intack_read[] = {
167 &PPC_intack_readb,
168 &PPC_intack_readw,
169 &PPC_intack_readl,
170 };
171
172 /* PowerPC control and status registers */
173 #if 0 // Not used
174 static struct {
175 /* IDs */
176 uint32_t veni_devi;
177 uint32_t revi;
178 /* Control and status */
179 uint32_t gcsr;
180 uint32_t xcfr;
181 uint32_t ct32;
182 uint32_t mcsr;
183 /* General purpose registers */
184 uint32_t gprg[6];
185 /* Exceptions */
186 uint32_t feen;
187 uint32_t fest;
188 uint32_t fema;
189 uint32_t fecl;
190 uint32_t eeen;
191 uint32_t eest;
192 uint32_t eecl;
193 uint32_t eeint;
194 uint32_t eemck0;
195 uint32_t eemck1;
196 /* Error diagnostic */
197 } XCSR;
198
199 static void PPC_XCSR_writeb (void *opaque,
200 target_phys_addr_t addr, uint32_t value)
201 {
202 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
203 value);
204 }
205
206 static void PPC_XCSR_writew (void *opaque,
207 target_phys_addr_t addr, uint32_t value)
208 {
209 #ifdef TARGET_WORDS_BIGENDIAN
210 value = bswap16(value);
211 #endif
212 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
213 value);
214 }
215
216 static void PPC_XCSR_writel (void *opaque,
217 target_phys_addr_t addr, uint32_t value)
218 {
219 #ifdef TARGET_WORDS_BIGENDIAN
220 value = bswap32(value);
221 #endif
222 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
223 value);
224 }
225
226 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
227 {
228 uint32_t retval = 0;
229
230 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
231 retval);
232
233 return retval;
234 }
235
236 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
237 {
238 uint32_t retval = 0;
239
240 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
241 retval);
242 #ifdef TARGET_WORDS_BIGENDIAN
243 retval = bswap16(retval);
244 #endif
245
246 return retval;
247 }
248
249 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
250 {
251 uint32_t retval = 0;
252
253 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
254 retval);
255 #ifdef TARGET_WORDS_BIGENDIAN
256 retval = bswap32(retval);
257 #endif
258
259 return retval;
260 }
261
262 static CPUWriteMemoryFunc * const PPC_XCSR_write[] = {
263 &PPC_XCSR_writeb,
264 &PPC_XCSR_writew,
265 &PPC_XCSR_writel,
266 };
267
268 static CPUReadMemoryFunc * const PPC_XCSR_read[] = {
269 &PPC_XCSR_readb,
270 &PPC_XCSR_readw,
271 &PPC_XCSR_readl,
272 };
273 #endif
274
275 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
276 typedef struct sysctrl_t {
277 qemu_irq reset_irq;
278 m48t59_t *nvram;
279 uint8_t state;
280 uint8_t syscontrol;
281 uint8_t fake_io[2];
282 int contiguous_map;
283 int endian;
284 } sysctrl_t;
285
286 enum {
287 STATE_HARDFILE = 0x01,
288 };
289
290 static sysctrl_t *sysctrl;
291
292 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
293 {
294 sysctrl_t *sysctrl = opaque;
295
296 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
297 val);
298 sysctrl->fake_io[addr - 0x0398] = val;
299 }
300
301 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
302 {
303 sysctrl_t *sysctrl = opaque;
304
305 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
306 sysctrl->fake_io[addr - 0x0398]);
307 return sysctrl->fake_io[addr - 0x0398];
308 }
309
310 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
311 {
312 sysctrl_t *sysctrl = opaque;
313
314 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
315 addr - PPC_IO_BASE, val);
316 switch (addr) {
317 case 0x0092:
318 /* Special port 92 */
319 /* Check soft reset asked */
320 if (val & 0x01) {
321 qemu_irq_raise(sysctrl->reset_irq);
322 } else {
323 qemu_irq_lower(sysctrl->reset_irq);
324 }
325 /* Check LE mode */
326 if (val & 0x02) {
327 sysctrl->endian = 1;
328 } else {
329 sysctrl->endian = 0;
330 }
331 break;
332 case 0x0800:
333 /* Motorola CPU configuration register : read-only */
334 break;
335 case 0x0802:
336 /* Motorola base module feature register : read-only */
337 break;
338 case 0x0803:
339 /* Motorola base module status register : read-only */
340 break;
341 case 0x0808:
342 /* Hardfile light register */
343 if (val & 1)
344 sysctrl->state |= STATE_HARDFILE;
345 else
346 sysctrl->state &= ~STATE_HARDFILE;
347 break;
348 case 0x0810:
349 /* Password protect 1 register */
350 if (sysctrl->nvram != NULL)
351 m48t59_toggle_lock(sysctrl->nvram, 1);
352 break;
353 case 0x0812:
354 /* Password protect 2 register */
355 if (sysctrl->nvram != NULL)
356 m48t59_toggle_lock(sysctrl->nvram, 2);
357 break;
358 case 0x0814:
359 /* L2 invalidate register */
360 // tlb_flush(first_cpu, 1);
361 break;
362 case 0x081C:
363 /* system control register */
364 sysctrl->syscontrol = val & 0x0F;
365 break;
366 case 0x0850:
367 /* I/O map type register */
368 sysctrl->contiguous_map = val & 0x01;
369 break;
370 default:
371 printf("ERROR: unaffected IO port write: %04" PRIx32
372 " => %02" PRIx32"\n", addr, val);
373 break;
374 }
375 }
376
377 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
378 {
379 sysctrl_t *sysctrl = opaque;
380 uint32_t retval = 0xFF;
381
382 switch (addr) {
383 case 0x0092:
384 /* Special port 92 */
385 retval = 0x00;
386 break;
387 case 0x0800:
388 /* Motorola CPU configuration register */
389 retval = 0xEF; /* MPC750 */
390 break;
391 case 0x0802:
392 /* Motorola Base module feature register */
393 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
394 break;
395 case 0x0803:
396 /* Motorola base module status register */
397 retval = 0xE0; /* Standard MPC750 */
398 break;
399 case 0x080C:
400 /* Equipment present register:
401 * no L2 cache
402 * no upgrade processor
403 * no cards in PCI slots
404 * SCSI fuse is bad
405 */
406 retval = 0x3C;
407 break;
408 case 0x0810:
409 /* Motorola base module extended feature register */
410 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
411 break;
412 case 0x0814:
413 /* L2 invalidate: don't care */
414 break;
415 case 0x0818:
416 /* Keylock */
417 retval = 0x00;
418 break;
419 case 0x081C:
420 /* system control register
421 * 7 - 6 / 1 - 0: L2 cache enable
422 */
423 retval = sysctrl->syscontrol;
424 break;
425 case 0x0823:
426 /* */
427 retval = 0x03; /* no L2 cache */
428 break;
429 case 0x0850:
430 /* I/O map type register */
431 retval = sysctrl->contiguous_map;
432 break;
433 default:
434 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
435 break;
436 }
437 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
438 addr - PPC_IO_BASE, retval);
439
440 return retval;
441 }
442
443 static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
444 target_phys_addr_t addr)
445 {
446 if (sysctrl->contiguous_map == 0) {
447 /* 64 KB contiguous space for IOs */
448 addr &= 0xFFFF;
449 } else {
450 /* 8 MB non-contiguous space for IOs */
451 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
452 }
453
454 return addr;
455 }
456
457 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
458 uint32_t value)
459 {
460 sysctrl_t *sysctrl = opaque;
461
462 addr = prep_IO_address(sysctrl, addr);
463 cpu_outb(addr, value);
464 }
465
466 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
467 {
468 sysctrl_t *sysctrl = opaque;
469 uint32_t ret;
470
471 addr = prep_IO_address(sysctrl, addr);
472 ret = cpu_inb(addr);
473
474 return ret;
475 }
476
477 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
478 uint32_t value)
479 {
480 sysctrl_t *sysctrl = opaque;
481
482 addr = prep_IO_address(sysctrl, addr);
483 #ifdef TARGET_WORDS_BIGENDIAN
484 value = bswap16(value);
485 #endif
486 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
487 cpu_outw(addr, value);
488 }
489
490 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
491 {
492 sysctrl_t *sysctrl = opaque;
493 uint32_t ret;
494
495 addr = prep_IO_address(sysctrl, addr);
496 ret = cpu_inw(addr);
497 #ifdef TARGET_WORDS_BIGENDIAN
498 ret = bswap16(ret);
499 #endif
500 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
501
502 return ret;
503 }
504
505 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
506 uint32_t value)
507 {
508 sysctrl_t *sysctrl = opaque;
509
510 addr = prep_IO_address(sysctrl, addr);
511 #ifdef TARGET_WORDS_BIGENDIAN
512 value = bswap32(value);
513 #endif
514 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
515 cpu_outl(addr, value);
516 }
517
518 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
519 {
520 sysctrl_t *sysctrl = opaque;
521 uint32_t ret;
522
523 addr = prep_IO_address(sysctrl, addr);
524 ret = cpu_inl(addr);
525 #ifdef TARGET_WORDS_BIGENDIAN
526 ret = bswap32(ret);
527 #endif
528 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
529
530 return ret;
531 }
532
533 static CPUWriteMemoryFunc * const PPC_prep_io_write[] = {
534 &PPC_prep_io_writeb,
535 &PPC_prep_io_writew,
536 &PPC_prep_io_writel,
537 };
538
539 static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
540 &PPC_prep_io_readb,
541 &PPC_prep_io_readw,
542 &PPC_prep_io_readl,
543 };
544
545 #define NVRAM_SIZE 0x2000
546
547 /* PowerPC PREP hardware initialisation */
548 static void ppc_prep_init (ram_addr_t ram_size,
549 const char *boot_device,
550 const char *kernel_filename,
551 const char *kernel_cmdline,
552 const char *initrd_filename,
553 const char *cpu_model)
554 {
555 CPUState *env = NULL, *envs[MAX_CPUS];
556 char *filename;
557 nvram_t nvram;
558 m48t59_t *m48t59;
559 int PPC_io_memory;
560 int linux_boot, i, nb_nics1, bios_size;
561 ram_addr_t ram_offset, bios_offset;
562 uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
563 PCIBus *pci_bus;
564 qemu_irq *i8259;
565 int ppc_boot_device;
566 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
567 DriveInfo *fd[MAX_FD];
568
569 sysctrl = qemu_mallocz(sizeof(sysctrl_t));
570
571 linux_boot = (kernel_filename != NULL);
572
573 /* init CPUs */
574 if (cpu_model == NULL)
575 cpu_model = "602";
576 for (i = 0; i < smp_cpus; i++) {
577 env = cpu_init(cpu_model);
578 if (!env) {
579 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
580 exit(1);
581 }
582 if (env->flags & POWERPC_FLAG_RTC_CLK) {
583 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
584 cpu_ppc_tb_init(env, 7812500UL);
585 } else {
586 /* Set time-base frequency to 100 Mhz */
587 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
588 }
589 qemu_register_reset(&cpu_ppc_reset, env);
590 envs[i] = env;
591 }
592
593 /* allocate RAM */
594 ram_offset = qemu_ram_alloc(ram_size);
595 cpu_register_physical_memory(0, ram_size, ram_offset);
596
597 /* allocate and load BIOS */
598 bios_offset = qemu_ram_alloc(BIOS_SIZE);
599 if (bios_name == NULL)
600 bios_name = BIOS_FILENAME;
601 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
602 if (filename) {
603 bios_size = get_image_size(filename);
604 } else {
605 bios_size = -1;
606 }
607 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
608 target_phys_addr_t bios_addr;
609 bios_size = (bios_size + 0xfff) & ~0xfff;
610 bios_addr = (uint32_t)(-bios_size);
611 cpu_register_physical_memory(bios_addr, bios_size,
612 bios_offset | IO_MEM_ROM);
613 bios_size = load_image_targphys(filename, bios_addr, bios_size);
614 }
615 if (bios_size < 0 || bios_size > BIOS_SIZE) {
616 hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
617 }
618 if (filename) {
619 qemu_free(filename);
620 }
621 if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
622 hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
623 }
624
625 if (linux_boot) {
626 kernel_base = KERNEL_LOAD_ADDR;
627 /* now we can load the kernel */
628 kernel_size = load_image_targphys(kernel_filename, kernel_base,
629 ram_size - kernel_base);
630 if (kernel_size < 0) {
631 hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
632 exit(1);
633 }
634 /* load initrd */
635 if (initrd_filename) {
636 initrd_base = INITRD_LOAD_ADDR;
637 initrd_size = load_image_targphys(initrd_filename, initrd_base,
638 ram_size - initrd_base);
639 if (initrd_size < 0) {
640 hw_error("qemu: could not load initial ram disk '%s'\n",
641 initrd_filename);
642 }
643 } else {
644 initrd_base = 0;
645 initrd_size = 0;
646 }
647 ppc_boot_device = 'm';
648 } else {
649 kernel_base = 0;
650 kernel_size = 0;
651 initrd_base = 0;
652 initrd_size = 0;
653 ppc_boot_device = '\0';
654 /* For now, OHW cannot boot from the network. */
655 for (i = 0; boot_device[i] != '\0'; i++) {
656 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
657 ppc_boot_device = boot_device[i];
658 break;
659 }
660 }
661 if (ppc_boot_device == '\0') {
662 fprintf(stderr, "No valid boot device for Mac99 machine\n");
663 exit(1);
664 }
665 }
666
667 isa_mem_base = 0xc0000000;
668 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
669 hw_error("Only 6xx bus is supported on PREP machine\n");
670 }
671 i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
672 pci_bus = pci_prep_init(i8259);
673 /* Hmm, prep has no pci-isa bridge ??? */
674 isa_bus_new(NULL);
675 isa_bus_irqs(i8259);
676 // pci_bus = i440fx_init();
677 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
678 PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
679 PPC_prep_io_write, sysctrl);
680 cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
681
682 /* init basic PC hardware */
683 pci_vga_init(pci_bus, 0, 0);
684 // openpic = openpic_init(0x00000000, 0xF0000000, 1);
685 // pit = pit_init(0x40, i8259[0]);
686 rtc_init(2000);
687
688 if (serial_hds[0])
689 serial_isa_init(0, serial_hds[0]);
690 nb_nics1 = nb_nics;
691 if (nb_nics1 > NE2000_NB_MAX)
692 nb_nics1 = NE2000_NB_MAX;
693 for(i = 0; i < nb_nics1; i++) {
694 if (nd_table[i].model == NULL) {
695 nd_table[i].model = "ne2k_isa";
696 }
697 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
698 isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
699 } else {
700 pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
701 }
702 }
703
704 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
705 fprintf(stderr, "qemu: too many IDE bus\n");
706 exit(1);
707 }
708
709 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
710 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
711 }
712
713 for(i = 0; i < MAX_IDE_BUS; i++) {
714 isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
715 hd[2 * i],
716 hd[2 * i + 1]);
717 }
718 isa_create_simple("i8042");
719 DMA_init(1);
720 // SB16_init();
721
722 for(i = 0; i < MAX_FD; i++) {
723 fd[i] = drive_get(IF_FLOPPY, 0, i);
724 }
725 fdctrl_init_isa(fd);
726
727 /* Register speaker port */
728 register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
729 register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
730 /* Register fake IO ports for PREP */
731 sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
732 register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
733 register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
734 /* System control ports */
735 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
736 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
737 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
738 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
739 /* PCI intack location */
740 PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
741 PPC_intack_write, NULL);
742 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
743 /* PowerPC control and status register group */
744 #if 0
745 PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
746 NULL);
747 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
748 #endif
749
750 if (usb_enabled) {
751 usb_ohci_init_pci(pci_bus, -1);
752 }
753
754 m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
755 if (m48t59 == NULL)
756 return;
757 sysctrl->nvram = m48t59;
758
759 /* Initialise NVRAM */
760 nvram.opaque = m48t59;
761 nvram.read_fn = &m48t59_read;
762 nvram.write_fn = &m48t59_write;
763 PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
764 kernel_base, kernel_size,
765 kernel_cmdline,
766 initrd_base, initrd_size,
767 /* XXX: need an option to load a NVRAM image */
768 0,
769 graphic_width, graphic_height, graphic_depth);
770
771 /* Special port to get debug messages from Open-Firmware */
772 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
773 }
774
775 static QEMUMachine prep_machine = {
776 .name = "prep",
777 .desc = "PowerPC PREP platform",
778 .init = ppc_prep_init,
779 .max_cpus = MAX_CPUS,
780 };
781
782 static void prep_machine_init(void)
783 {
784 qemu_register_machine(&prep_machine);
785 }
786
787 machine_init(prep_machine_init);
Qemu copy for testing