2 * QEMU PPC PREP hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
36 //#define HARD_DEBUG_PPC_IO
37 //#define DEBUG_PPC_IO
39 /* SMP is not enabled, for now */
44 #define BIOS_SIZE (1024 * 1024)
45 #define BIOS_FILENAME "ppc_rom.bin"
46 #define KERNEL_LOAD_ADDR 0x01000000
47 #define INITRD_LOAD_ADDR 0x01800000
49 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
53 #if defined (HARD_DEBUG_PPC_IO)
54 #define PPC_IO_DPRINTF(fmt, ...) \
56 if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
57 qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
59 printf("%s : " fmt, __func__ , ## __VA_ARGS__); \
62 #elif defined (DEBUG_PPC_IO)
63 #define PPC_IO_DPRINTF(fmt, ...) \
64 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
66 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
69 /* Constants for devices init */
70 static const int ide_iobase
[2] = { 0x1f0, 0x170 };
71 static const int ide_iobase2
[2] = { 0x3f6, 0x376 };
72 static const int ide_irq
[2] = { 13, 13 };
74 #define NE2000_NB_MAX 6
76 static uint32_t ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
77 static int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
79 //static PITState *pit;
81 /* ISA IO ports bridge */
82 #define PPC_IO_BASE 0x80000000
85 /* Speaker port 0x61 */
86 static int speaker_data_on
;
87 static int dummy_refresh_clock
;
90 static void speaker_ioport_write (void *opaque
, uint32_t addr
, uint32_t val
)
93 speaker_data_on
= (val
>> 1) & 1;
94 pit_set_gate(pit
, 2, val
& 1);
98 static uint32_t speaker_ioport_read (void *opaque
, uint32_t addr
)
102 out
= pit_get_out(pit
, 2, qemu_get_clock(vm_clock
));
103 dummy_refresh_clock
^= 1;
104 return (speaker_data_on
<< 1) | pit_get_gate(pit
, 2) | (out
<< 5) |
105 (dummy_refresh_clock
<< 4);
110 /* PCI intack register */
111 /* Read-only register (?) */
112 static void _PPC_intack_write (void *opaque
,
113 target_phys_addr_t addr
, uint32_t value
)
116 printf("%s: 0x" TARGET_FMT_plx
" => 0x%08" PRIx32
"\n", __func__
, addr
,
121 static inline uint32_t _PPC_intack_read(target_phys_addr_t addr
)
125 if ((addr
& 0xf) == 0)
126 retval
= pic_intack_read(isa_pic
);
128 printf("%s: 0x" TARGET_FMT_plx
" <= %08" PRIx32
"\n", __func__
, addr
,
135 static uint32_t PPC_intack_readb (void *opaque
, target_phys_addr_t addr
)
137 return _PPC_intack_read(addr
);
140 static uint32_t PPC_intack_readw (void *opaque
, target_phys_addr_t addr
)
142 #ifdef TARGET_WORDS_BIGENDIAN
143 return bswap16(_PPC_intack_read(addr
));
145 return _PPC_intack_read(addr
);
149 static uint32_t PPC_intack_readl (void *opaque
, target_phys_addr_t addr
)
151 #ifdef TARGET_WORDS_BIGENDIAN
152 return bswap32(_PPC_intack_read(addr
));
154 return _PPC_intack_read(addr
);
158 static CPUWriteMemoryFunc
* const PPC_intack_write
[] = {
164 static CPUReadMemoryFunc
* const PPC_intack_read
[] = {
170 /* PowerPC control and status registers */
176 /* Control and status */
181 /* General purpose registers */
194 /* Error diagnostic */
197 static void PPC_XCSR_writeb (void *opaque
,
198 target_phys_addr_t addr
, uint32_t value
)
200 printf("%s: 0x" TARGET_FMT_plx
" => 0x%08" PRIx32
"\n", __func__
, addr
,
204 static void PPC_XCSR_writew (void *opaque
,
205 target_phys_addr_t addr
, uint32_t value
)
207 #ifdef TARGET_WORDS_BIGENDIAN
208 value
= bswap16(value
);
210 printf("%s: 0x" TARGET_FMT_plx
" => 0x%08" PRIx32
"\n", __func__
, addr
,
214 static void PPC_XCSR_writel (void *opaque
,
215 target_phys_addr_t addr
, uint32_t value
)
217 #ifdef TARGET_WORDS_BIGENDIAN
218 value
= bswap32(value
);
220 printf("%s: 0x" TARGET_FMT_plx
" => 0x%08" PRIx32
"\n", __func__
, addr
,
224 static uint32_t PPC_XCSR_readb (void *opaque
, target_phys_addr_t addr
)
228 printf("%s: 0x" TARGET_FMT_plx
" <= %08" PRIx32
"\n", __func__
, addr
,
234 static uint32_t PPC_XCSR_readw (void *opaque
, target_phys_addr_t addr
)
238 printf("%s: 0x" TARGET_FMT_plx
" <= %08" PRIx32
"\n", __func__
, addr
,
240 #ifdef TARGET_WORDS_BIGENDIAN
241 retval
= bswap16(retval
);
247 static uint32_t PPC_XCSR_readl (void *opaque
, target_phys_addr_t addr
)
251 printf("%s: 0x" TARGET_FMT_plx
" <= %08" PRIx32
"\n", __func__
, addr
,
253 #ifdef TARGET_WORDS_BIGENDIAN
254 retval
= bswap32(retval
);
260 static CPUWriteMemoryFunc
* const PPC_XCSR_write
[] = {
266 static CPUReadMemoryFunc
* const PPC_XCSR_read
[] = {
273 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
274 typedef struct sysctrl_t
{
285 STATE_HARDFILE
= 0x01,
288 static sysctrl_t
*sysctrl
;
290 static void PREP_io_write (void *opaque
, uint32_t addr
, uint32_t val
)
292 sysctrl_t
*sysctrl
= opaque
;
294 PPC_IO_DPRINTF("0x%08" PRIx32
" => 0x%02" PRIx32
"\n", addr
- PPC_IO_BASE
,
296 sysctrl
->fake_io
[addr
- 0x0398] = val
;
299 static uint32_t PREP_io_read (void *opaque
, uint32_t addr
)
301 sysctrl_t
*sysctrl
= opaque
;
303 PPC_IO_DPRINTF("0x%08" PRIx32
" <= 0x%02" PRIx32
"\n", addr
- PPC_IO_BASE
,
304 sysctrl
->fake_io
[addr
- 0x0398]);
305 return sysctrl
->fake_io
[addr
- 0x0398];
308 static void PREP_io_800_writeb (void *opaque
, uint32_t addr
, uint32_t val
)
310 sysctrl_t
*sysctrl
= opaque
;
312 PPC_IO_DPRINTF("0x%08" PRIx32
" => 0x%02" PRIx32
"\n",
313 addr
- PPC_IO_BASE
, val
);
316 /* Special port 92 */
317 /* Check soft reset asked */
319 qemu_irq_raise(sysctrl
->reset_irq
);
321 qemu_irq_lower(sysctrl
->reset_irq
);
331 /* Motorola CPU configuration register : read-only */
334 /* Motorola base module feature register : read-only */
337 /* Motorola base module status register : read-only */
340 /* Hardfile light register */
342 sysctrl
->state
|= STATE_HARDFILE
;
344 sysctrl
->state
&= ~STATE_HARDFILE
;
347 /* Password protect 1 register */
348 if (sysctrl
->nvram
!= NULL
)
349 m48t59_toggle_lock(sysctrl
->nvram
, 1);
352 /* Password protect 2 register */
353 if (sysctrl
->nvram
!= NULL
)
354 m48t59_toggle_lock(sysctrl
->nvram
, 2);
357 /* L2 invalidate register */
358 // tlb_flush(first_cpu, 1);
361 /* system control register */
362 sysctrl
->syscontrol
= val
& 0x0F;
365 /* I/O map type register */
366 sysctrl
->contiguous_map
= val
& 0x01;
369 printf("ERROR: unaffected IO port write: %04" PRIx32
370 " => %02" PRIx32
"\n", addr
, val
);
375 static uint32_t PREP_io_800_readb (void *opaque
, uint32_t addr
)
377 sysctrl_t
*sysctrl
= opaque
;
378 uint32_t retval
= 0xFF;
382 /* Special port 92 */
386 /* Motorola CPU configuration register */
387 retval
= 0xEF; /* MPC750 */
390 /* Motorola Base module feature register */
391 retval
= 0xAD; /* No ESCC, PMC slot neither ethernet */
394 /* Motorola base module status register */
395 retval
= 0xE0; /* Standard MPC750 */
398 /* Equipment present register:
400 * no upgrade processor
401 * no cards in PCI slots
407 /* Motorola base module extended feature register */
408 retval
= 0x39; /* No USB, CF and PCI bridge. NVRAM present */
411 /* L2 invalidate: don't care */
418 /* system control register
419 * 7 - 6 / 1 - 0: L2 cache enable
421 retval
= sysctrl
->syscontrol
;
425 retval
= 0x03; /* no L2 cache */
428 /* I/O map type register */
429 retval
= sysctrl
->contiguous_map
;
432 printf("ERROR: unaffected IO port: %04" PRIx32
" read\n", addr
);
435 PPC_IO_DPRINTF("0x%08" PRIx32
" <= 0x%02" PRIx32
"\n",
436 addr
- PPC_IO_BASE
, retval
);
441 static inline target_phys_addr_t
prep_IO_address(sysctrl_t
*sysctrl
,
442 target_phys_addr_t addr
)
444 if (sysctrl
->contiguous_map
== 0) {
445 /* 64 KB contiguous space for IOs */
448 /* 8 MB non-contiguous space for IOs */
449 addr
= (addr
& 0x1F) | ((addr
& 0x007FFF000) >> 7);
455 static void PPC_prep_io_writeb (void *opaque
, target_phys_addr_t addr
,
458 sysctrl_t
*sysctrl
= opaque
;
460 addr
= prep_IO_address(sysctrl
, addr
);
461 cpu_outb(NULL
, addr
, value
);
464 static uint32_t PPC_prep_io_readb (void *opaque
, target_phys_addr_t addr
)
466 sysctrl_t
*sysctrl
= opaque
;
469 addr
= prep_IO_address(sysctrl
, addr
);
470 ret
= cpu_inb(NULL
, addr
);
475 static void PPC_prep_io_writew (void *opaque
, target_phys_addr_t addr
,
478 sysctrl_t
*sysctrl
= opaque
;
480 addr
= prep_IO_address(sysctrl
, addr
);
481 #ifdef TARGET_WORDS_BIGENDIAN
482 value
= bswap16(value
);
484 PPC_IO_DPRINTF("0x" TARGET_FMT_plx
" => 0x%08" PRIx32
"\n", addr
, value
);
485 cpu_outw(NULL
, addr
, value
);
488 static uint32_t PPC_prep_io_readw (void *opaque
, target_phys_addr_t addr
)
490 sysctrl_t
*sysctrl
= opaque
;
493 addr
= prep_IO_address(sysctrl
, addr
);
494 ret
= cpu_inw(NULL
, addr
);
495 #ifdef TARGET_WORDS_BIGENDIAN
498 PPC_IO_DPRINTF("0x" TARGET_FMT_plx
" <= 0x%08" PRIx32
"\n", addr
, ret
);
503 static void PPC_prep_io_writel (void *opaque
, target_phys_addr_t addr
,
506 sysctrl_t
*sysctrl
= opaque
;
508 addr
= prep_IO_address(sysctrl
, addr
);
509 #ifdef TARGET_WORDS_BIGENDIAN
510 value
= bswap32(value
);
512 PPC_IO_DPRINTF("0x" TARGET_FMT_plx
" => 0x%08" PRIx32
"\n", addr
, value
);
513 cpu_outl(NULL
, addr
, value
);
516 static uint32_t PPC_prep_io_readl (void *opaque
, target_phys_addr_t addr
)
518 sysctrl_t
*sysctrl
= opaque
;
521 addr
= prep_IO_address(sysctrl
, addr
);
522 ret
= cpu_inl(NULL
, addr
);
523 #ifdef TARGET_WORDS_BIGENDIAN
526 PPC_IO_DPRINTF("0x" TARGET_FMT_plx
" <= 0x%08" PRIx32
"\n", addr
, ret
);
531 static CPUWriteMemoryFunc
* const PPC_prep_io_write
[] = {
537 static CPUReadMemoryFunc
* const PPC_prep_io_read
[] = {
543 #define NVRAM_SIZE 0x2000
545 /* PowerPC PREP hardware initialisation */
546 static void ppc_prep_init (ram_addr_t ram_size
,
547 const char *boot_device
,
548 const char *kernel_filename
,
549 const char *kernel_cmdline
,
550 const char *initrd_filename
,
551 const char *cpu_model
)
553 CPUState
*env
= NULL
, *envs
[MAX_CPUS
];
558 int linux_boot
, i
, nb_nics1
, bios_size
;
559 ram_addr_t ram_offset
, bios_offset
;
560 uint32_t kernel_base
, kernel_size
, initrd_base
, initrd_size
;
565 BlockDriverState
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
566 BlockDriverState
*fd
[MAX_FD
];
568 sysctrl
= qemu_mallocz(sizeof(sysctrl_t
));
570 linux_boot
= (kernel_filename
!= NULL
);
573 if (cpu_model
== NULL
)
574 cpu_model
= "default";
575 for (i
= 0; i
< smp_cpus
; i
++) {
576 env
= cpu_init(cpu_model
);
578 fprintf(stderr
, "Unable to find PowerPC CPU definition\n");
581 if (env
->flags
& POWERPC_FLAG_RTC_CLK
) {
582 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
583 cpu_ppc_tb_init(env
, 7812500UL);
585 /* Set time-base frequency to 100 Mhz */
586 cpu_ppc_tb_init(env
, 100UL * 1000UL * 1000UL);
588 qemu_register_reset(&cpu_ppc_reset
, env
);
593 ram_offset
= qemu_ram_alloc(ram_size
);
594 cpu_register_physical_memory(0, ram_size
, ram_offset
);
596 /* allocate and load BIOS */
597 bios_offset
= qemu_ram_alloc(BIOS_SIZE
);
598 if (bios_name
== NULL
)
599 bios_name
= BIOS_FILENAME
;
600 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
602 bios_size
= get_image_size(filename
);
606 if (bios_size
> 0 && bios_size
<= BIOS_SIZE
) {
607 target_phys_addr_t bios_addr
;
608 bios_size
= (bios_size
+ 0xfff) & ~0xfff;
609 bios_addr
= (uint32_t)(-bios_size
);
610 cpu_register_physical_memory(bios_addr
, bios_size
,
611 bios_offset
| IO_MEM_ROM
);
612 bios_size
= load_image_targphys(filename
, bios_addr
, bios_size
);
614 if (bios_size
< 0 || bios_size
> BIOS_SIZE
) {
615 hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name
);
620 if (env
->nip
< 0xFFF80000 && bios_size
< 0x00100000) {
621 hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
625 kernel_base
= KERNEL_LOAD_ADDR
;
626 /* now we can load the kernel */
627 kernel_size
= load_image_targphys(kernel_filename
, kernel_base
,
628 ram_size
- kernel_base
);
629 if (kernel_size
< 0) {
630 hw_error("qemu: could not load kernel '%s'\n", kernel_filename
);
634 if (initrd_filename
) {
635 initrd_base
= INITRD_LOAD_ADDR
;
636 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
637 ram_size
- initrd_base
);
638 if (initrd_size
< 0) {
639 hw_error("qemu: could not load initial ram disk '%s'\n",
646 ppc_boot_device
= 'm';
652 ppc_boot_device
= '\0';
653 /* For now, OHW cannot boot from the network. */
654 for (i
= 0; boot_device
[i
] != '\0'; i
++) {
655 if (boot_device
[i
] >= 'a' && boot_device
[i
] <= 'f') {
656 ppc_boot_device
= boot_device
[i
];
660 if (ppc_boot_device
== '\0') {
661 fprintf(stderr
, "No valid boot device for Mac99 machine\n");
666 isa_mem_base
= 0xc0000000;
667 if (PPC_INPUT(env
) != PPC_FLAGS_INPUT_6xx
) {
668 hw_error("Only 6xx bus is supported on PREP machine\n");
670 i8259
= i8259_init(first_cpu
->irq_inputs
[PPC6xx_INPUT_INT
]);
671 pci_bus
= pci_prep_init(i8259
);
672 // pci_bus = i440fx_init();
673 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
674 PPC_io_memory
= cpu_register_io_memory(PPC_prep_io_read
,
675 PPC_prep_io_write
, sysctrl
);
676 cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory
);
678 /* init basic PC hardware */
679 pci_vga_init(pci_bus
, 0, 0);
680 // openpic = openpic_init(0x00000000, 0xF0000000, 1);
681 // pit = pit_init(0x40, i8259[0]);
682 rtc_init(0x70, i8259
[8], 2000);
684 serial_init(0x3f8, i8259
[4], 115200, serial_hds
[0]);
686 if (nb_nics1
> NE2000_NB_MAX
)
687 nb_nics1
= NE2000_NB_MAX
;
688 for(i
= 0; i
< nb_nics1
; i
++) {
689 if (nd_table
[i
].model
== NULL
) {
690 nd_table
[i
].model
= "ne2k_isa";
692 if (strcmp(nd_table
[i
].model
, "ne2k_isa") == 0) {
693 isa_ne2000_init(ne2000_io
[i
], i8259
[ne2000_irq
[i
]], &nd_table
[i
]);
695 pci_nic_init(&nd_table
[i
], "ne2k_pci", NULL
);
699 if (drive_get_max_bus(IF_IDE
) >= MAX_IDE_BUS
) {
700 fprintf(stderr
, "qemu: too many IDE bus\n");
704 for(i
= 0; i
< MAX_IDE_BUS
* MAX_IDE_DEVS
; i
++) {
705 dinfo
= drive_get(IF_IDE
, i
/ MAX_IDE_DEVS
, i
% MAX_IDE_DEVS
);
706 hd
[i
] = dinfo
? dinfo
->bdrv
: NULL
;
709 for(i
= 0; i
< MAX_IDE_BUS
; i
++) {
710 isa_ide_init(ide_iobase
[i
], ide_iobase2
[i
], i8259
[ide_irq
[i
]],
714 i8042_init(i8259
[1], i8259
[12], 0x60);
718 for(i
= 0; i
< MAX_FD
; i
++) {
719 dinfo
= drive_get(IF_FLOPPY
, 0, i
);
720 fd
[i
] = dinfo
? dinfo
->bdrv
: NULL
;
722 fdctrl_init(i8259
[6], 2, 0, 0x3f0, fd
);
724 /* Register speaker port */
725 register_ioport_read(0x61, 1, 1, speaker_ioport_read
, NULL
);
726 register_ioport_write(0x61, 1, 1, speaker_ioport_write
, NULL
);
727 /* Register fake IO ports for PREP */
728 sysctrl
->reset_irq
= first_cpu
->irq_inputs
[PPC6xx_INPUT_HRESET
];
729 register_ioport_read(0x398, 2, 1, &PREP_io_read
, sysctrl
);
730 register_ioport_write(0x398, 2, 1, &PREP_io_write
, sysctrl
);
731 /* System control ports */
732 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb
, sysctrl
);
733 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb
, sysctrl
);
734 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb
, sysctrl
);
735 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb
, sysctrl
);
736 /* PCI intack location */
737 PPC_io_memory
= cpu_register_io_memory(PPC_intack_read
,
738 PPC_intack_write
, NULL
);
739 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory
);
740 /* PowerPC control and status register group */
742 PPC_io_memory
= cpu_register_io_memory(PPC_XCSR_read
, PPC_XCSR_write
,
744 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory
);
748 usb_ohci_init_pci(pci_bus
, 3, -1);
751 m48t59
= m48t59_init(i8259
[8], 0, 0x0074, NVRAM_SIZE
, 59);
754 sysctrl
->nvram
= m48t59
;
756 /* Initialise NVRAM */
757 nvram
.opaque
= m48t59
;
758 nvram
.read_fn
= &m48t59_read
;
759 nvram
.write_fn
= &m48t59_write
;
760 PPC_NVRAM_set_params(&nvram
, NVRAM_SIZE
, "PREP", ram_size
, ppc_boot_device
,
761 kernel_base
, kernel_size
,
763 initrd_base
, initrd_size
,
764 /* XXX: need an option to load a NVRAM image */
766 graphic_width
, graphic_height
, graphic_depth
);
768 /* Special port to get debug messages from Open-Firmware */
769 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write
, NULL
);
772 static QEMUMachine prep_machine
= {
774 .desc
= "PowerPC PREP platform",
775 .init
= ppc_prep_init
,
776 .max_cpus
= MAX_CPUS
,
779 static void prep_machine_init(void)
781 qemu_register_machine(&prep_machine
);
784 machine_init(prep_machine_init
);