hw/ppce500_mpc8544ds.c

   1 /*
   2  * QEMU PowerPC MPC8544DS board emulation
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc440_bamboo.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "config.h"
  18 #include "qemu-common.h"
  19 #include "net.h"
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "pci.h"
  23 #include "boards.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "kvm_ppc.h"
  27 #include "device_tree.h"
  28 #include "openpic.h"
  29 #include "ppc.h"
  30 #include "loader.h"
  31 #include "elf.h"
  32 #include "sysbus.h"
  33 #include "exec-memory.h"
  34 #include "host-utils.h"
  35
  36 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
  37 #define UIMAGE_LOAD_BASE           0
  38 #define DTC_LOAD_PAD               0x500000
  39 #define DTC_PAD_MASK               0xFFFFF
  40 #define INITRD_LOAD_PAD            0x2000000
  41 #define INITRD_PAD_MASK            0xFFFFFF
  42
  43 #define RAM_SIZES_ALIGN            (64UL << 20)
  44
  45 #define MPC8544_CCSRBAR_BASE       0xE0000000ULL
  46 #define MPC8544_CCSRBAR_SIZE       0x00100000ULL
  47 #define MPC8544_MPIC_REGS_BASE     (MPC8544_CCSRBAR_BASE + 0x40000ULL)
  48 #define MPC8544_SERIAL0_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4500ULL)
  49 #define MPC8544_SERIAL1_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4600ULL)
  50 #define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + 0x8000ULL)
  51 #define MPC8544_PCI_REGS_SIZE      0x1000ULL
  52 #define MPC8544_PCI_IO             0xE1000000ULL
  53 #define MPC8544_PCI_IOLEN          0x10000ULL
  54 #define MPC8544_UTIL_BASE          (MPC8544_CCSRBAR_BASE + 0xe0000ULL)
  55 #define MPC8544_SPIN_BASE          0xEF000000ULL
  56
  57 struct boot_info
  58 {
  59     uint32_t dt_base;
  60     uint32_t dt_size;
  61     uint32_t entry;
  62 };
  63
  64 static void pci_map_create(void *fdt, uint32_t *pci_map, uint32_t mpic)
  65 {
  66     int i;
  67     const uint32_t tmp[] = {
  68                              /* IDSEL 0x11 J17 Slot 1 */
  69                              0x8800, 0x0, 0x0, 0x1, mpic, 0x2, 0x1, 0x0, 0x0,
  70                              0x8800, 0x0, 0x0, 0x2, mpic, 0x3, 0x1, 0x0, 0x0,
  71                              0x8800, 0x0, 0x0, 0x3, mpic, 0x4, 0x1, 0x0, 0x0,
  72                              0x8800, 0x0, 0x0, 0x4, mpic, 0x1, 0x1, 0x0, 0x0,
  73
  74                              /* IDSEL 0x12 J16 Slot 2 */
  75                              0x9000, 0x0, 0x0, 0x1, mpic, 0x3, 0x1, 0x0, 0x0,
  76                              0x9000, 0x0, 0x0, 0x2, mpic, 0x4, 0x1, 0x0, 0x0,
  77                              0x9000, 0x0, 0x0, 0x3, mpic, 0x2, 0x1, 0x0, 0x0,
  78                              0x9000, 0x0, 0x0, 0x4, mpic, 0x1, 0x1, 0x0, 0x0,
  79                            };
  80     for (i = 0; i < ARRAY_SIZE(tmp); i++) {
  81         pci_map[i] = cpu_to_be32(tmp[i]);
  82     }
  83 }
  84
  85 static int mpc8544_load_device_tree(CPUPPCState *env,
  86                                     target_phys_addr_t addr,
  87                                     target_phys_addr_t ramsize,
  88                                     target_phys_addr_t initrd_base,
  89                                     target_phys_addr_t initrd_size,
  90                                     const char *kernel_cmdline)
  91 {
  92     int ret = -1;
  93     uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) };
  94     int fdt_size;
  95     void *fdt;
  96     uint8_t hypercall[16];
  97     uint32_t clock_freq = 400000000;
  98     uint32_t tb_freq = 400000000;
  99     int i;
 100     char compatible[] = "MPC8544DS\0MPC85xxDS";
 101     char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
 102     char model[] = "MPC8544DS";
 103     char soc[128];
 104     char ser0[128];
 105     char ser1[128];
 106     char mpic[128];
 107     uint32_t mpic_ph;
 108     char gutil[128];
 109     char pci[128];
 110     uint32_t pci_map[9 * 8];
 111     uint32_t pci_ranges[14] =
 112         {
 113             0x2000000, 0x0, 0xc0000000,
 114             0x0, 0xc0000000,
 115             0x0, 0x20000000,
 116
 117             0x1000000, 0x0, 0x0,
 118             0x0, 0xe1000000,
 119             0x0, 0x10000,
 120         };
 121     QemuOpts *machine_opts;
 122     const char *dumpdtb = NULL;
 123     const char *dtb_file = NULL;
 124
 125     machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
 126     if (machine_opts) {
 127         dumpdtb = qemu_opt_get(machine_opts, "dumpdtb");
 128         dtb_file = qemu_opt_get(machine_opts, "dtb");
 129     }
 130
 131     if (dtb_file) {
 132         char *filename;
 133         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
 134         if (!filename) {
 135             goto out;
 136         }
 137
 138         fdt = load_device_tree(filename, &fdt_size);
 139         if (!fdt) {
 140             goto out;
 141         }
 142         goto done;
 143     }
 144
 145     fdt = create_device_tree(&fdt_size);
 146     if (fdt == NULL) {
 147         goto out;
 148     }
 149
 150     /* Manipulate device tree in memory. */
 151     qemu_devtree_setprop_string(fdt, "/", "model", model);
 152     qemu_devtree_setprop(fdt, "/", "compatible", compatible,
 153                          sizeof(compatible));
 154     qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2);
 155     qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2);
 156
 157     qemu_devtree_add_subnode(fdt, "/memory");
 158     qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");
 159     qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
 160                          sizeof(mem_reg_property));
 161
 162     qemu_devtree_add_subnode(fdt, "/chosen");
 163     if (initrd_size) {
 164         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
 165                                         initrd_base);
 166         if (ret < 0) {
 167             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
 168         }
 169
 170         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 171                                         (initrd_base + initrd_size));
 172         if (ret < 0) {
 173             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
 174         }
 175     }
 176
 177     ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
 178                                       kernel_cmdline);
 179     if (ret < 0)
 180         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 181
 182     if (kvm_enabled()) {
 183         /* Read out host's frequencies */
 184         clock_freq = kvmppc_get_clockfreq();
 185         tb_freq = kvmppc_get_tbfreq();
 186
 187         /* indicate KVM hypercall interface */
 188         qemu_devtree_add_subnode(fdt, "/hypervisor");
 189         qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
 190                                     "linux,kvm");
 191         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
 192         qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
 193                              hypercall, sizeof(hypercall));
 194     }
 195
 196     /* Create CPU nodes */
 197     qemu_devtree_add_subnode(fdt, "/cpus");
 198     qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1);
 199     qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0);
 200
 201     /* We need to generate the cpu nodes in reverse order, so Linux can pick
 202        the first node as boot node and be happy */
 203     for (i = smp_cpus - 1; i >= 0; i--) {
 204         char cpu_name[128];
 205         uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
 206
 207         for (env = first_cpu; env != NULL; env = env->next_cpu) {
 208             if (env->cpu_index == i) {
 209                 break;
 210             }
 211         }
 212
 213         if (!env) {
 214             continue;
 215         }
 216
 217         snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index);
 218         qemu_devtree_add_subnode(fdt, cpu_name);
 219         qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
 220         qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
 221         qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
 222         qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);
 223         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
 224                                   env->dcache_line_size);
 225         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
 226                                   env->icache_line_size);
 227         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
 228         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
 229         qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
 230         if (env->cpu_index) {
 231             qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
 232             qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
 233             qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr",
 234                                      cpu_release_addr);
 235         } else {
 236             qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
 237         }
 238     }
 239
 240     qemu_devtree_add_subnode(fdt, "/aliases");
 241     /* XXX These should go into their respective devices' code */
 242     snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);
 243     qemu_devtree_add_subnode(fdt, soc);
 244     qemu_devtree_setprop_string(fdt, soc, "device_type", "soc");
 245     qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb,
 246                          sizeof(compatible_sb));
 247     qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);
 248     qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);
 249     qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0,
 250                                MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
 251                                MPC8544_CCSRBAR_SIZE);
 252     /* XXX should contain a reasonable value */
 253     qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
 254
 255     snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc,
 256              MPC8544_MPIC_REGS_BASE - MPC8544_CCSRBAR_BASE);
 257     qemu_devtree_add_subnode(fdt, mpic);
 258     qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");
 259     qemu_devtree_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
 260     qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_BASE -
 261                                MPC8544_CCSRBAR_BASE, 0x40000);
 262     qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);
 263     qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 4);
 264     mpic_ph = qemu_devtree_alloc_phandle(fdt);
 265     qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph);
 266     qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
 267     qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
 268     qemu_devtree_setprop(fdt, mpic, "big-endian", NULL, 0);
 269     qemu_devtree_setprop(fdt, mpic, "single-cpu-affinity", NULL, 0);
 270     qemu_devtree_setprop_cell(fdt, mpic, "last-interrupt-source", 255);
 271
 272     /*
 273      * We have to generate ser1 first, because Linux takes the first
 274      * device it finds in the dt as serial output device. And we generate
 275      * devices in reverse order to the dt.
 276      */
 277     snprintf(ser1, sizeof(ser1), "%s/serial@%llx", soc,
 278              MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_BASE);
 279     qemu_devtree_add_subnode(fdt, ser1);
 280     qemu_devtree_setprop_string(fdt, ser1, "device_type", "serial");
 281     qemu_devtree_setprop_string(fdt, ser1, "compatible", "ns16550");
 282     qemu_devtree_setprop_cells(fdt, ser1, "reg", MPC8544_SERIAL1_REGS_BASE -
 283                                MPC8544_CCSRBAR_BASE, 0x100);
 284     qemu_devtree_setprop_cell(fdt, ser1, "cell-index", 1);
 285     qemu_devtree_setprop_cell(fdt, ser1, "clock-frequency", 0);
 286     qemu_devtree_setprop_cells(fdt, ser1, "interrupts", 42, 2, 0, 0);
 287     qemu_devtree_setprop_phandle(fdt, ser1, "interrupt-parent", mpic);
 288     qemu_devtree_setprop_string(fdt, "/aliases", "serial1", ser1);
 289
 290     snprintf(ser0, sizeof(ser0), "%s/serial@%llx", soc,
 291              MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_BASE);
 292     qemu_devtree_add_subnode(fdt, ser0);
 293     qemu_devtree_setprop_string(fdt, ser0, "device_type", "serial");
 294     qemu_devtree_setprop_string(fdt, ser0, "compatible", "ns16550");
 295     qemu_devtree_setprop_cells(fdt, ser0, "reg", MPC8544_SERIAL0_REGS_BASE -
 296                                MPC8544_CCSRBAR_BASE, 0x100);
 297     qemu_devtree_setprop_cell(fdt, ser0, "cell-index", 0);
 298     qemu_devtree_setprop_cell(fdt, ser0, "clock-frequency", 0);
 299     qemu_devtree_setprop_cells(fdt, ser0, "interrupts", 42, 2, 0, 0);
 300     qemu_devtree_setprop_phandle(fdt, ser0, "interrupt-parent", mpic);
 301     qemu_devtree_setprop_string(fdt, "/aliases", "serial0", ser0);
 302     qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser0);
 303
 304     snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
 305              MPC8544_UTIL_BASE - MPC8544_CCSRBAR_BASE);
 306     qemu_devtree_add_subnode(fdt, gutil);
 307     qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
 308     qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_BASE -
 309                                MPC8544_CCSRBAR_BASE, 0x1000);
 310     qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
 311
 312     snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
 313     qemu_devtree_add_subnode(fdt, pci);
 314     qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);
 315     qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
 316     qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");
 317     qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
 318                                0x0, 0x7);
 319     pci_map_create(fdt, pci_map, qemu_devtree_get_phandle(fdt, mpic));
 320     qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, sizeof(pci_map));
 321     qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
 322     qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2, 0, 0);
 323     qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);
 324     for (i = 0; i < 14; i++) {
 325         pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
 326     }
 327     qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
 328     qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
 329                                MPC8544_PCI_REGS_BASE, 0, 0x1000);
 330     qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);
 331     qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);
 332     qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);
 333     qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3);
 334     qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci);
 335
 336 done:
 337     if (dumpdtb) {
 338         /* Dump the dtb to a file and quit */
 339         FILE *f = fopen(dumpdtb, "wb");
 340         size_t len;
 341         len = fwrite(fdt, fdt_size, 1, f);
 342         fclose(f);
 343         if (len != fdt_size) {
 344             exit(1);
 345         }
 346         exit(0);
 347     }
 348
 349     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 350     if (ret < 0) {
 351         goto out;
 352     }
 353     g_free(fdt);
 354     ret = fdt_size;
 355
 356 out:
 357
 358     return ret;
 359 }
 360
 361 /* Create -kernel TLB entries for BookE.  */
 362 static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
 363 {
 364     return 63 - clz64(size >> 10);
 365 }
 366
 367 static void mmubooke_create_initial_mapping(CPUPPCState *env)
 368 {
 369     struct boot_info *bi = env->load_info;
 370     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
 371     target_phys_addr_t size, dt_end;
 372     int ps;
 373
 374     /* Our initial TLB entry needs to cover everything from 0 to
 375        the device tree top */
 376     dt_end = bi->dt_base + bi->dt_size;
 377     ps = booke206_page_size_to_tlb(dt_end) + 1;
 378     size = (ps << MAS1_TSIZE_SHIFT);
 379     tlb->mas1 = MAS1_VALID | size;
 380     tlb->mas2 = 0;
 381     tlb->mas7_3 = 0;
 382     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
 383
 384     env->tlb_dirty = true;
 385 }
 386
 387 static void mpc8544ds_cpu_reset_sec(void *opaque)
 388 {
 389     PowerPCCPU *cpu = opaque;
 390     CPUPPCState *env = &cpu->env;
 391
 392     cpu_reset(CPU(cpu));
 393
 394     /* Secondary CPU starts in halted state for now. Needs to change when
 395        implementing non-kernel boot. */
 396     env->halted = 1;
 397     env->exception_index = EXCP_HLT;
 398 }
 399
 400 static void mpc8544ds_cpu_reset(void *opaque)
 401 {
 402     PowerPCCPU *cpu = opaque;
 403     CPUPPCState *env = &cpu->env;
 404     struct boot_info *bi = env->load_info;
 405
 406     cpu_reset(CPU(cpu));
 407
 408     /* Set initial guest state. */
 409     env->halted = 0;
 410     env->gpr[1] = (16<<20) - 8;
 411     env->gpr[3] = bi->dt_base;
 412     env->nip = bi->entry;
 413     mmubooke_create_initial_mapping(env);
 414 }
 415
 416 static void mpc8544ds_init(ram_addr_t ram_size,
 417                          const char *boot_device,
 418                          const char *kernel_filename,
 419                          const char *kernel_cmdline,
 420                          const char *initrd_filename,
 421                          const char *cpu_model)
 422 {
 423     MemoryRegion *address_space_mem = get_system_memory();
 424     MemoryRegion *ram = g_new(MemoryRegion, 1);
 425     PCIBus *pci_bus;
 426     CPUPPCState *env = NULL;
 427     uint64_t elf_entry;
 428     uint64_t elf_lowaddr;
 429     target_phys_addr_t entry=0;
 430     target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
 431     target_long kernel_size=0;
 432     target_ulong dt_base = 0;
 433     target_ulong initrd_base = 0;
 434     target_long initrd_size=0;
 435     int i=0;
 436     unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
 437     qemu_irq **irqs, *mpic;
 438     DeviceState *dev;
 439     CPUPPCState *firstenv = NULL;
 440
 441     /* Setup CPUs */
 442     if (cpu_model == NULL) {
 443         cpu_model = "e500v2_v30";
 444     }
 445
 446     irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 447     irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 448     for (i = 0; i < smp_cpus; i++) {
 449         PowerPCCPU *cpu;
 450         qemu_irq *input;
 451
 452         cpu = cpu_ppc_init(cpu_model);
 453         if (cpu == NULL) {
 454             fprintf(stderr, "Unable to initialize CPU!\n");
 455             exit(1);
 456         }
 457         env = &cpu->env;
 458
 459         if (!firstenv) {
 460             firstenv = env;
 461         }
 462
 463         irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
 464         input = (qemu_irq *)env->irq_inputs;
 465         irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
 466         irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
 467         env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
 468
 469         ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500);
 470
 471         /* Register reset handler */
 472         if (!i) {
 473             /* Primary CPU */
 474             struct boot_info *boot_info;
 475             boot_info = g_malloc0(sizeof(struct boot_info));
 476             qemu_register_reset(mpc8544ds_cpu_reset, cpu);
 477             env->load_info = boot_info;
 478         } else {
 479             /* Secondary CPUs */
 480             qemu_register_reset(mpc8544ds_cpu_reset_sec, cpu);
 481         }
 482     }
 483
 484     env = firstenv;
 485
 486     /* Fixup Memory size on a alignment boundary */
 487     ram_size &= ~(RAM_SIZES_ALIGN - 1);
 488
 489     /* Register Memory */
 490     memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
 491     vmstate_register_ram_global(ram);
 492     memory_region_add_subregion(address_space_mem, 0, ram);
 493
 494     /* MPIC */
 495     mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE,
 496                      smp_cpus, irqs, NULL);
 497
 498     if (!mpic) {
 499         cpu_abort(env, "MPIC failed to initialize\n");
 500     }
 501
 502     /* Serial */
 503     if (serial_hds[0]) {
 504         serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE,
 505                        0, mpic[12+26], 399193,
 506                        serial_hds[0], DEVICE_BIG_ENDIAN);
 507     }
 508
 509     if (serial_hds[1]) {
 510         serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE,
 511                        0, mpic[12+26], 399193,
 512                        serial_hds[0], DEVICE_BIG_ENDIAN);
 513     }
 514
 515     /* General Utility device */
 516     sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL);
 517
 518     /* PCI */
 519     dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
 520                                 mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]],
 521                                 mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]],
 522                                 NULL);
 523     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 524     if (!pci_bus)
 525         printf("couldn't create PCI controller!\n");
 526
 527     isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN);
 528
 529     if (pci_bus) {
 530         /* Register network interfaces. */
 531         for (i = 0; i < nb_nics; i++) {
 532             pci_nic_init_nofail(&nd_table[i], "virtio", NULL);
 533         }
 534     }
 535
 536     /* Register spinning region */
 537     sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
 538
 539     /* Load kernel. */
 540     if (kernel_filename) {
 541         kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
 542         if (kernel_size < 0) {
 543             kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
 544                                    &elf_lowaddr, NULL, 1, ELF_MACHINE, 0);
 545             entry = elf_entry;
 546             loadaddr = elf_lowaddr;
 547         }
 548         /* XXX try again as binary */
 549         if (kernel_size < 0) {
 550             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 551                     kernel_filename);
 552             exit(1);
 553         }
 554     }
 555
 556     /* Load initrd. */
 557     if (initrd_filename) {
 558         initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
 559         initrd_size = load_image_targphys(initrd_filename, initrd_base,
 560                                           ram_size - initrd_base);
 561
 562         if (initrd_size < 0) {
 563             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 564                     initrd_filename);
 565             exit(1);
 566         }
 567     }
 568
 569     /* If we're loading a kernel directly, we must load the device tree too. */
 570     if (kernel_filename) {
 571         struct boot_info *boot_info;
 572         int dt_size;
 573
 574         dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
 575         dt_size = mpc8544_load_device_tree(env, dt_base, ram_size, initrd_base,
 576                                            initrd_size, kernel_cmdline);
 577         if (dt_size < 0) {
 578             fprintf(stderr, "couldn't load device tree\n");
 579             exit(1);
 580         }
 581
 582         boot_info = env->load_info;
 583         boot_info->entry = entry;
 584         boot_info->dt_base = dt_base;
 585         boot_info->dt_size = dt_size;
 586     }
 587
 588     if (kvm_enabled()) {
 589         kvmppc_init();
 590     }
 591 }
 592
 593 static QEMUMachine mpc8544ds_machine = {
 594     .name = "mpc8544ds",
 595     .desc = "mpc8544ds",
 596     .init = mpc8544ds_init,
 597     .max_cpus = 15,
 598 };
 599
 600 static void mpc8544ds_machine_init(void)
 601 {
 602     qemu_register_machine(&mpc8544ds_machine);
 603 }
 604
 605 machine_init(mpc8544ds_machine_init);