2 * Qemu PowerPC MPC8544DS board emualtion
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Yu Liu, <yu.liu@freescale.com>
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
18 #include "qemu-common.h"
27 #include "device_tree.h"
34 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
35 #define UIMAGE_LOAD_BASE 0
36 #define DTC_LOAD_PAD 0x500000
37 #define DTC_PAD_MASK 0xFFFFF
38 #define INITRD_LOAD_PAD 0x2000000
39 #define INITRD_PAD_MASK 0xFFFFFF
41 #define RAM_SIZES_ALIGN (64UL << 20)
43 #define MPC8544_CCSRBAR_BASE 0xE0000000
44 #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000)
45 #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500)
46 #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600)
47 #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000)
48 #define MPC8544_PCI_REGS_SIZE 0x1000
49 #define MPC8544_PCI_IO 0xE1000000
50 #define MPC8544_PCI_IOLEN 0x10000
51 #define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000)
52 #define MPC8544_SPIN_BASE 0xEF000000
60 static int mpc8544_load_device_tree(CPUState
*env
,
61 target_phys_addr_t addr
,
63 target_phys_addr_t initrd_base
,
64 target_phys_addr_t initrd_size
,
65 const char *kernel_cmdline
)
69 uint32_t mem_reg_property
[] = {0, cpu_to_be32(ramsize
)};
73 uint8_t hypercall
[16];
74 uint32_t clock_freq
= 400000000;
75 uint32_t tb_freq
= 400000000;
78 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, BINARY_DEVICE_TREE_FILE
);
82 fdt
= load_device_tree(filename
, &fdt_size
);
88 /* Manipulate device tree in memory. */
89 ret
= qemu_devtree_setprop(fdt
, "/memory", "reg", mem_reg_property
,
90 sizeof(mem_reg_property
));
92 fprintf(stderr
, "couldn't set /memory/reg\n");
95 ret
= qemu_devtree_setprop_cell(fdt
, "/chosen", "linux,initrd-start",
98 fprintf(stderr
, "couldn't set /chosen/linux,initrd-start\n");
101 ret
= qemu_devtree_setprop_cell(fdt
, "/chosen", "linux,initrd-end",
102 (initrd_base
+ initrd_size
));
104 fprintf(stderr
, "couldn't set /chosen/linux,initrd-end\n");
108 ret
= qemu_devtree_setprop_string(fdt
, "/chosen", "bootargs",
111 fprintf(stderr
, "couldn't set /chosen/bootargs\n");
114 /* Read out host's frequencies */
115 clock_freq
= kvmppc_get_clockfreq();
116 tb_freq
= kvmppc_get_tbfreq();
118 /* indicate KVM hypercall interface */
119 qemu_devtree_setprop_string(fdt
, "/hypervisor", "compatible",
121 kvmppc_get_hypercall(env
, hypercall
, sizeof(hypercall
));
122 qemu_devtree_setprop(fdt
, "/hypervisor", "hcall-instructions",
123 hypercall
, sizeof(hypercall
));
126 /* We need to generate the cpu nodes in reverse order, so Linux can pick
127 the first node as boot node and be happy */
128 for (i
= smp_cpus
- 1; i
>= 0; i
--) {
130 uint64_t cpu_release_addr
= cpu_to_be64(MPC8544_SPIN_BASE
+ (i
* 0x20));
132 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
133 if (env
->cpu_index
== i
) {
142 snprintf(cpu_name
, sizeof(cpu_name
), "/cpus/PowerPC,8544@%x", env
->cpu_index
);
143 qemu_devtree_add_subnode(fdt
, cpu_name
);
144 qemu_devtree_setprop_cell(fdt
, cpu_name
, "clock-frequency", clock_freq
);
145 qemu_devtree_setprop_cell(fdt
, cpu_name
, "timebase-frequency", tb_freq
);
146 qemu_devtree_setprop_string(fdt
, cpu_name
, "device_type", "cpu");
147 qemu_devtree_setprop_cell(fdt
, cpu_name
, "reg", env
->cpu_index
);
148 qemu_devtree_setprop_cell(fdt
, cpu_name
, "d-cache-line-size",
149 env
->dcache_line_size
);
150 qemu_devtree_setprop_cell(fdt
, cpu_name
, "i-cache-line-size",
151 env
->icache_line_size
);
152 qemu_devtree_setprop_cell(fdt
, cpu_name
, "d-cache-size", 0x8000);
153 qemu_devtree_setprop_cell(fdt
, cpu_name
, "i-cache-size", 0x8000);
154 qemu_devtree_setprop_cell(fdt
, cpu_name
, "bus-frequency", 0);
155 if (env
->cpu_index
) {
156 qemu_devtree_setprop_string(fdt
, cpu_name
, "status", "disabled");
157 qemu_devtree_setprop_string(fdt
, cpu_name
, "enable-method", "spin-table");
158 qemu_devtree_setprop(fdt
, cpu_name
, "cpu-release-addr",
159 &cpu_release_addr
, sizeof(cpu_release_addr
));
161 qemu_devtree_setprop_string(fdt
, cpu_name
, "status", "okay");
165 ret
= rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE
, fdt
, fdt_size
, addr
);
174 /* Create -kernel TLB entries for BookE, linearly spanning 256MB. */
175 static inline target_phys_addr_t
booke206_page_size_to_tlb(uint64_t size
)
177 return ffs(size
>> 10) - 1;
180 static void mmubooke_create_initial_mapping(CPUState
*env
,
182 target_phys_addr_t pa
)
184 ppcmas_tlb_t
*tlb
= booke206_get_tlbm(env
, 1, 0, 0);
185 target_phys_addr_t size
;
187 size
= (booke206_page_size_to_tlb(256 * 1024 * 1024) << MAS1_TSIZE_SHIFT
);
188 tlb
->mas1
= MAS1_VALID
| size
;
189 tlb
->mas2
= va
& TARGET_PAGE_MASK
;
190 tlb
->mas7_3
= pa
& TARGET_PAGE_MASK
;
191 tlb
->mas7_3
|= MAS3_UR
| MAS3_UW
| MAS3_UX
| MAS3_SR
| MAS3_SW
| MAS3_SX
;
193 env
->tlb_dirty
= true;
196 static void mpc8544ds_cpu_reset_sec(void *opaque
)
198 CPUState
*env
= opaque
;
202 /* Secondary CPU starts in halted state for now. Needs to change when
203 implementing non-kernel boot. */
205 env
->exception_index
= EXCP_HLT
;
208 static void mpc8544ds_cpu_reset(void *opaque
)
210 CPUState
*env
= opaque
;
211 struct boot_info
*bi
= env
->load_info
;
215 /* Set initial guest state. */
217 env
->gpr
[1] = (16<<20) - 8;
218 env
->gpr
[3] = bi
->dt_base
;
219 env
->nip
= bi
->entry
;
220 mmubooke_create_initial_mapping(env
, 0, 0);
223 static void mpc8544ds_init(ram_addr_t ram_size
,
224 const char *boot_device
,
225 const char *kernel_filename
,
226 const char *kernel_cmdline
,
227 const char *initrd_filename
,
228 const char *cpu_model
)
231 CPUState
*env
= NULL
;
233 uint64_t elf_lowaddr
;
234 target_phys_addr_t entry
=0;
235 target_phys_addr_t loadaddr
=UIMAGE_LOAD_BASE
;
236 target_long kernel_size
=0;
237 target_ulong dt_base
= 0;
238 target_ulong initrd_base
= 0;
239 target_long initrd_size
=0;
241 unsigned int pci_irq_nrs
[4] = {1, 2, 3, 4};
242 qemu_irq
**irqs
, *mpic
;
244 CPUState
*firstenv
= NULL
;
247 if (cpu_model
== NULL
) {
248 cpu_model
= "e500v2_v30";
251 irqs
= g_malloc0(smp_cpus
* sizeof(qemu_irq
*));
252 irqs
[0] = g_malloc0(smp_cpus
* sizeof(qemu_irq
) * OPENPIC_OUTPUT_NB
);
253 for (i
= 0; i
< smp_cpus
; i
++) {
255 env
= cpu_ppc_init(cpu_model
);
257 fprintf(stderr
, "Unable to initialize CPU!\n");
265 irqs
[i
] = irqs
[0] + (i
* OPENPIC_OUTPUT_NB
);
266 input
= (qemu_irq
*)env
->irq_inputs
;
267 irqs
[i
][OPENPIC_OUTPUT_INT
] = input
[PPCE500_INPUT_INT
];
268 irqs
[i
][OPENPIC_OUTPUT_CINT
] = input
[PPCE500_INPUT_CINT
];
269 env
->spr
[SPR_BOOKE_PIR
] = env
->cpu_index
= i
;
271 ppc_booke_timers_init(env
, 400000000, PPC_TIMER_E500
);
273 /* Register reset handler */
276 struct boot_info
*boot_info
;
277 boot_info
= g_malloc0(sizeof(struct boot_info
));
278 qemu_register_reset(mpc8544ds_cpu_reset
, env
);
279 env
->load_info
= boot_info
;
282 qemu_register_reset(mpc8544ds_cpu_reset_sec
, env
);
288 /* Fixup Memory size on a alignment boundary */
289 ram_size
&= ~(RAM_SIZES_ALIGN
- 1);
291 /* Register Memory */
292 cpu_register_physical_memory(0, ram_size
, qemu_ram_alloc(NULL
,
293 "mpc8544ds.ram", ram_size
));
296 mpic
= mpic_init(MPC8544_MPIC_REGS_BASE
, smp_cpus
, irqs
, NULL
);
299 cpu_abort(env
, "MPIC failed to initialize\n");
304 serial_mm_init(MPC8544_SERIAL0_REGS_BASE
,
305 0, mpic
[12+26], 399193,
306 serial_hds
[0], 1, 1);
310 serial_mm_init(MPC8544_SERIAL1_REGS_BASE
,
311 0, mpic
[12+26], 399193,
312 serial_hds
[0], 1, 1);
315 /* General Utility device */
316 sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE
, NULL
);
319 dev
= sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE
,
320 mpic
[pci_irq_nrs
[0]], mpic
[pci_irq_nrs
[1]],
321 mpic
[pci_irq_nrs
[2]], mpic
[pci_irq_nrs
[3]],
323 pci_bus
= (PCIBus
*)qdev_get_child_bus(dev
, "pci.0");
325 printf("couldn't create PCI controller!\n");
327 isa_mmio_init(MPC8544_PCI_IO
, MPC8544_PCI_IOLEN
);
330 /* Register network interfaces. */
331 for (i
= 0; i
< nb_nics
; i
++) {
332 pci_nic_init_nofail(&nd_table
[i
], "virtio", NULL
);
336 /* Register spinning region */
337 sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE
, NULL
);
340 if (kernel_filename
) {
341 kernel_size
= load_uimage(kernel_filename
, &entry
, &loadaddr
, NULL
);
342 if (kernel_size
< 0) {
343 kernel_size
= load_elf(kernel_filename
, NULL
, NULL
, &elf_entry
,
344 &elf_lowaddr
, NULL
, 1, ELF_MACHINE
, 0);
346 loadaddr
= elf_lowaddr
;
348 /* XXX try again as binary */
349 if (kernel_size
< 0) {
350 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
357 if (initrd_filename
) {
358 initrd_base
= (kernel_size
+ INITRD_LOAD_PAD
) & ~INITRD_PAD_MASK
;
359 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
360 ram_size
- initrd_base
);
362 if (initrd_size
< 0) {
363 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
369 /* If we're loading a kernel directly, we must load the device tree too. */
370 if (kernel_filename
) {
371 struct boot_info
*boot_info
;
374 cpu_abort(env
, "Compiled without FDT support - can't load kernel\n");
376 dt_base
= (kernel_size
+ DTC_LOAD_PAD
) & ~DTC_PAD_MASK
;
377 if (mpc8544_load_device_tree(env
, dt_base
, ram_size
,
378 initrd_base
, initrd_size
, kernel_cmdline
) < 0) {
379 fprintf(stderr
, "couldn't load device tree\n");
383 boot_info
= env
->load_info
;
384 boot_info
->entry
= entry
;
385 boot_info
->dt_base
= dt_base
;
393 static QEMUMachine mpc8544ds_machine
= {
396 .init
= mpc8544ds_init
,
400 static void mpc8544ds_machine_init(void)
402 qemu_register_machine(&mpc8544ds_machine
);
405 machine_init(mpc8544ds_machine_init
);