hw/prep_pci.c

   1 /*
   2  * QEMU PREP PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28 #include "prep_pci.h"
  29
  30 typedef PCIHostState PREPPCIState;
  31
  32 typedef struct RavenPCIState {
  33     PCIDevice dev;
  34 } RavenPCIState;
  35
  36 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
  37 {
  38     int i;
  39
  40     for(i = 0; i < 11; i++) {
  41         if ((addr & (1 << (11 + i))) != 0)
  42             break;
  43     }
  44     return (addr & 0x7ff) |  (i << 11);
  45 }
  46
  47 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
  48 {
  49     PREPPCIState *s = opaque;
  50     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
  51 }
  52
  53 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
  54 {
  55     PREPPCIState *s = opaque;
  56     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
  57 }
  58
  59 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
  60 {
  61     PREPPCIState *s = opaque;
  62     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
  63 }
  64
  65 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
  66 {
  67     PREPPCIState *s = opaque;
  68     uint32_t val;
  69     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
  70     return val;
  71 }
  72
  73 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
  74 {
  75     PREPPCIState *s = opaque;
  76     uint32_t val;
  77     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
  78     return val;
  79 }
  80
  81 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
  82 {
  83     PREPPCIState *s = opaque;
  84     uint32_t val;
  85     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
  86     return val;
  87 }
  88
  89 static const MemoryRegionOps PPC_PCIIO_ops = {
  90     .old_mmio = {
  91         .read = { PPC_PCIIO_readb, PPC_PCIIO_readw, PPC_PCIIO_readl, },
  92         .write = { PPC_PCIIO_writeb, PPC_PCIIO_writew, PPC_PCIIO_writel, },
  93     },
  94     .endianness = DEVICE_LITTLE_ENDIAN,
  95 };
  96
  97 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
  98 {
  99     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 100 }
 101
 102 static void prep_set_irq(void *opaque, int irq_num, int level)
 103 {
 104     qemu_irq *pic = opaque;
 105
 106     qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
 107 }
 108
 109 PCIBus *pci_prep_init(qemu_irq *pic,
 110                       MemoryRegion *address_space_mem,
 111                       MemoryRegion *address_space_io)
 112 {
 113     PREPPCIState *s;
 114
 115     s = g_malloc0(sizeof(PREPPCIState));
 116     s->bus = pci_register_bus(NULL, "pci",
 117                               prep_set_irq, prep_map_irq, pic,
 118                               address_space_mem,
 119                               address_space_io,
 120                               0, 4);
 121
 122     memory_region_init_io(&s->conf_mem, &pci_host_conf_be_ops, s,
 123                           "pci-conf-idx", 1);
 124     memory_region_add_subregion(address_space_io, 0xcf8, &s->conf_mem);
 125     sysbus_init_ioports(&s->busdev, 0xcf8, 1);
 126
 127     memory_region_init_io(&s->data_mem, &pci_host_data_be_ops, s,
 128                           "pci-conf-data", 1);
 129     memory_region_add_subregion(address_space_io, 0xcfc, &s->data_mem);
 130     sysbus_init_ioports(&s->busdev, 0xcfc, 1);
 131
 132     memory_region_init_io(&s->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
 133     memory_region_add_subregion(address_space_mem, 0x80800000, &s->mmcfg);
 134
 135     pci_create_simple(s->bus, 0, "raven");
 136
 137     return s->bus;
 138 }
 139
 140 static int raven_init(PCIDevice *d)
 141 {
 142     d->config[0x0C] = 0x08; // cache_line_size
 143     d->config[0x0D] = 0x10; // latency_timer
 144     d->config[0x34] = 0x00; // capabilities_pointer
 145
 146     return 0;
 147 }
 148
 149 static const VMStateDescription vmstate_raven = {
 150     .name = "raven",
 151     .version_id = 0,
 152     .minimum_version_id = 0,
 153     .fields = (VMStateField[]) {
 154         VMSTATE_PCI_DEVICE(dev, RavenPCIState),
 155         VMSTATE_END_OF_LIST()
 156     },
 157 };
 158
 159 static PCIDeviceInfo raven_info = {
 160     .qdev.name = "raven",
 161     .qdev.desc = "PReP Host Bridge - Motorola Raven",
 162     .qdev.size = sizeof(RavenPCIState),
 163     .qdev.vmsd = &vmstate_raven,
 164     .qdev.no_user = 1,
 165     .no_hotplug = 1,
 166     .init = raven_init,
 167     .vendor_id = PCI_VENDOR_ID_MOTOROLA,
 168     .device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN,
 169     .revision = 0x00,
 170     .class_id = PCI_CLASS_BRIDGE_HOST,
 171     .qdev.props = (Property[]) {
 172         DEFINE_PROP_END_OF_LIST()
 173     },
 174 };
 175
 176 static void raven_register_devices(void)
 177 {
 178     pci_qdev_register(&raven_info);
 179 }
 180
 181 device_init(raven_register_devices)