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1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licenced under the GPL.
8 */
9
10 #include "sysbus.h"
11 #include "pxa.h"
12 #include "sysemu.h"
13 #include "pc.h"
14 #include "i2c.h"
15 #include "ssi.h"
16 #include "qemu-char.h"
17 #include "blockdev.h"
18
19 static struct {
20 target_phys_addr_t io_base;
21 int irqn;
22 } pxa255_serial[] = {
23 { 0x40100000, PXA2XX_PIC_FFUART },
24 { 0x40200000, PXA2XX_PIC_BTUART },
25 { 0x40700000, PXA2XX_PIC_STUART },
26 { 0x41600000, PXA25X_PIC_HWUART },
27 { 0, 0 }
28 }, pxa270_serial[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART },
30 { 0x40200000, PXA2XX_PIC_BTUART },
31 { 0x40700000, PXA2XX_PIC_STUART },
32 { 0, 0 }
33 };
34
35 typedef struct PXASSPDef {
36 target_phys_addr_t io_base;
37 int irqn;
38 } PXASSPDef;
39
40 #if 0
41 static PXASSPDef pxa250_ssp[] = {
42 { 0x41000000, PXA2XX_PIC_SSP },
43 { 0, 0 }
44 };
45 #endif
46
47 static PXASSPDef pxa255_ssp[] = {
48 { 0x41000000, PXA2XX_PIC_SSP },
49 { 0x41400000, PXA25X_PIC_NSSP },
50 { 0, 0 }
51 };
52
53 #if 0
54 static PXASSPDef pxa26x_ssp[] = {
55 { 0x41000000, PXA2XX_PIC_SSP },
56 { 0x41400000, PXA25X_PIC_NSSP },
57 { 0x41500000, PXA26X_PIC_ASSP },
58 { 0, 0 }
59 };
60 #endif
61
62 static PXASSPDef pxa27x_ssp[] = {
63 { 0x41000000, PXA2XX_PIC_SSP },
64 { 0x41700000, PXA27X_PIC_SSP2 },
65 { 0x41900000, PXA2XX_PIC_SSP3 },
66 { 0, 0 }
67 };
68
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
90
91 static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
92 {
93 PXA2xxState *s = (PXA2xxState *) opaque;
94
95 switch (addr) {
96 case PMCR ... PCMD31:
97 if (addr & 3)
98 goto fail;
99
100 return s->pm_regs[addr >> 2];
101 default:
102 fail:
103 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
104 break;
105 }
106 return 0;
107 }
108
109 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
110 uint32_t value)
111 {
112 PXA2xxState *s = (PXA2xxState *) opaque;
113
114 switch (addr) {
115 case PMCR:
116 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
117 s->pm_regs[addr >> 2] |= value & 0x15;
118 break;
119
120 case PSSR: /* Read-clean registers */
121 case RCSR:
122 case PKSR:
123 s->pm_regs[addr >> 2] &= ~value;
124 break;
125
126 default: /* Read-write registers */
127 if (!(addr & 3)) {
128 s->pm_regs[addr >> 2] = value;
129 break;
130 }
131
132 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
133 break;
134 }
135 }
136
137 static CPUReadMemoryFunc * const pxa2xx_pm_readfn[] = {
138 pxa2xx_pm_read,
139 pxa2xx_pm_read,
140 pxa2xx_pm_read,
141 };
142
143 static CPUWriteMemoryFunc * const pxa2xx_pm_writefn[] = {
144 pxa2xx_pm_write,
145 pxa2xx_pm_write,
146 pxa2xx_pm_write,
147 };
148
149 static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
150 {
151 PXA2xxState *s = (PXA2xxState *) opaque;
152 int i;
153
154 for (i = 0; i < 0x40; i ++)
155 qemu_put_be32s(f, &s->pm_regs[i]);
156 }
157
158 static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
159 {
160 PXA2xxState *s = (PXA2xxState *) opaque;
161 int i;
162
163 for (i = 0; i < 0x40; i ++)
164 qemu_get_be32s(f, &s->pm_regs[i]);
165
166 return 0;
167 }
168
169 #define CCCR 0x00 /* Core Clock Configuration register */
170 #define CKEN 0x04 /* Clock Enable register */
171 #define OSCC 0x08 /* Oscillator Configuration register */
172 #define CCSR 0x0c /* Core Clock Status register */
173
174 static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
175 {
176 PXA2xxState *s = (PXA2xxState *) opaque;
177
178 switch (addr) {
179 case CCCR:
180 case CKEN:
181 case OSCC:
182 return s->cm_regs[addr >> 2];
183
184 case CCSR:
185 return s->cm_regs[CCCR >> 2] | (3 << 28);
186
187 default:
188 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
189 break;
190 }
191 return 0;
192 }
193
194 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
195 uint32_t value)
196 {
197 PXA2xxState *s = (PXA2xxState *) opaque;
198
199 switch (addr) {
200 case CCCR:
201 case CKEN:
202 s->cm_regs[addr >> 2] = value;
203 break;
204
205 case OSCC:
206 s->cm_regs[addr >> 2] &= ~0x6c;
207 s->cm_regs[addr >> 2] |= value & 0x6e;
208 if ((value >> 1) & 1) /* OON */
209 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
210 break;
211
212 default:
213 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
214 break;
215 }
216 }
217
218 static CPUReadMemoryFunc * const pxa2xx_cm_readfn[] = {
219 pxa2xx_cm_read,
220 pxa2xx_cm_read,
221 pxa2xx_cm_read,
222 };
223
224 static CPUWriteMemoryFunc * const pxa2xx_cm_writefn[] = {
225 pxa2xx_cm_write,
226 pxa2xx_cm_write,
227 pxa2xx_cm_write,
228 };
229
230 static const VMStateDescription vmstate_pxa2xx_cm = {
231 .name = "pxa2xx_cm",
232 .version_id = 0,
233 .minimum_version_id = 0,
234 .minimum_version_id_old = 0,
235 .fields = (VMStateField[]) {
236 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
237 VMSTATE_UINT32(clkcfg, PXA2xxState),
238 VMSTATE_UINT32(pmnc, PXA2xxState),
239 VMSTATE_END_OF_LIST()
240 }
241 };
242
243 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
244 {
245 PXA2xxState *s = (PXA2xxState *) opaque;
246
247 switch (reg) {
248 case 6: /* Clock Configuration register */
249 return s->clkcfg;
250
251 case 7: /* Power Mode register */
252 return 0;
253
254 default:
255 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
256 break;
257 }
258 return 0;
259 }
260
261 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
262 uint32_t value)
263 {
264 PXA2xxState *s = (PXA2xxState *) opaque;
265 static const char *pwrmode[8] = {
266 "Normal", "Idle", "Deep-idle", "Standby",
267 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
268 };
269
270 switch (reg) {
271 case 6: /* Clock Configuration register */
272 s->clkcfg = value & 0xf;
273 if (value & 2)
274 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
275 break;
276
277 case 7: /* Power Mode register */
278 if (value & 8)
279 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
280 switch (value & 7) {
281 case 0:
282 /* Do nothing */
283 break;
284
285 case 1:
286 /* Idle */
287 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
288 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
289 break;
290 }
291 /* Fall through. */
292
293 case 2:
294 /* Deep-Idle */
295 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
296 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
297 goto message;
298
299 case 3:
300 s->env->uncached_cpsr =
301 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
302 s->env->cp15.c1_sys = 0;
303 s->env->cp15.c1_coproc = 0;
304 s->env->cp15.c2_base0 = 0;
305 s->env->cp15.c3 = 0;
306 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
307 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
308
309 /*
310 * The scratch-pad register is almost universally used
311 * for storing the return address on suspend. For the
312 * lack of a resuming bootloader, perform a jump
313 * directly to that address.
314 */
315 memset(s->env->regs, 0, 4 * 15);
316 s->env->regs[15] = s->pm_regs[PSPR >> 2];
317
318 #if 0
319 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
320 cpu_physical_memory_write(0, &buffer, 4);
321 buffer = s->pm_regs[PSPR >> 2];
322 cpu_physical_memory_write(8, &buffer, 4);
323 #endif
324
325 /* Suspend */
326 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
327
328 goto message;
329
330 default:
331 message:
332 printf("%s: machine entered %s mode\n", __FUNCTION__,
333 pwrmode[value & 7]);
334 }
335 break;
336
337 default:
338 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
339 break;
340 }
341 }
342
343 /* Performace Monitoring Registers */
344 #define CPPMNC 0 /* Performance Monitor Control register */
345 #define CPCCNT 1 /* Clock Counter register */
346 #define CPINTEN 4 /* Interrupt Enable register */
347 #define CPFLAG 5 /* Overflow Flag register */
348 #define CPEVTSEL 8 /* Event Selection register */
349
350 #define CPPMN0 0 /* Performance Count register 0 */
351 #define CPPMN1 1 /* Performance Count register 1 */
352 #define CPPMN2 2 /* Performance Count register 2 */
353 #define CPPMN3 3 /* Performance Count register 3 */
354
355 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
356 {
357 PXA2xxState *s = (PXA2xxState *) opaque;
358
359 switch (reg) {
360 case CPPMNC:
361 return s->pmnc;
362 case CPCCNT:
363 if (s->pmnc & 1)
364 return qemu_get_clock_ns(vm_clock);
365 else
366 return 0;
367 case CPINTEN:
368 case CPFLAG:
369 case CPEVTSEL:
370 return 0;
371
372 default:
373 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
374 break;
375 }
376 return 0;
377 }
378
379 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
380 uint32_t value)
381 {
382 PXA2xxState *s = (PXA2xxState *) opaque;
383
384 switch (reg) {
385 case CPPMNC:
386 s->pmnc = value;
387 break;
388
389 case CPCCNT:
390 case CPINTEN:
391 case CPFLAG:
392 case CPEVTSEL:
393 break;
394
395 default:
396 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
397 break;
398 }
399 }
400
401 static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
402 {
403 switch (crm) {
404 case 0:
405 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
406 case 1:
407 return pxa2xx_perf_read(opaque, op2, reg, crm);
408 case 2:
409 switch (reg) {
410 case CPPMN0:
411 case CPPMN1:
412 case CPPMN2:
413 case CPPMN3:
414 return 0;
415 }
416 /* Fall through */
417 default:
418 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
419 break;
420 }
421 return 0;
422 }
423
424 static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
425 uint32_t value)
426 {
427 switch (crm) {
428 case 0:
429 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
430 break;
431 case 1:
432 pxa2xx_perf_write(opaque, op2, reg, crm, value);
433 break;
434 case 2:
435 switch (reg) {
436 case CPPMN0:
437 case CPPMN1:
438 case CPPMN2:
439 case CPPMN3:
440 return;
441 }
442 /* Fall through */
443 default:
444 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
445 break;
446 }
447 }
448
449 #define MDCNFG 0x00 /* SDRAM Configuration register */
450 #define MDREFR 0x04 /* SDRAM Refresh Control register */
451 #define MSC0 0x08 /* Static Memory Control register 0 */
452 #define MSC1 0x0c /* Static Memory Control register 1 */
453 #define MSC2 0x10 /* Static Memory Control register 2 */
454 #define MECR 0x14 /* Expansion Memory Bus Config register */
455 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
456 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
457 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
458 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
459 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
460 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
461 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
462 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
463 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
464 #define ARB_CNTL 0x48 /* Arbiter Control register */
465 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
466 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
467 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
468 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
469 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
470 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
471 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
472
473 static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
474 {
475 PXA2xxState *s = (PXA2xxState *) opaque;
476
477 switch (addr) {
478 case MDCNFG ... SA1110:
479 if ((addr & 3) == 0)
480 return s->mm_regs[addr >> 2];
481
482 default:
483 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
484 break;
485 }
486 return 0;
487 }
488
489 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
490 uint32_t value)
491 {
492 PXA2xxState *s = (PXA2xxState *) opaque;
493
494 switch (addr) {
495 case MDCNFG ... SA1110:
496 if ((addr & 3) == 0) {
497 s->mm_regs[addr >> 2] = value;
498 break;
499 }
500
501 default:
502 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
503 break;
504 }
505 }
506
507 static CPUReadMemoryFunc * const pxa2xx_mm_readfn[] = {
508 pxa2xx_mm_read,
509 pxa2xx_mm_read,
510 pxa2xx_mm_read,
511 };
512
513 static CPUWriteMemoryFunc * const pxa2xx_mm_writefn[] = {
514 pxa2xx_mm_write,
515 pxa2xx_mm_write,
516 pxa2xx_mm_write,
517 };
518
519 static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
520 {
521 PXA2xxState *s = (PXA2xxState *) opaque;
522 int i;
523
524 for (i = 0; i < 0x1a; i ++)
525 qemu_put_be32s(f, &s->mm_regs[i]);
526 }
527
528 static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
529 {
530 PXA2xxState *s = (PXA2xxState *) opaque;
531 int i;
532
533 for (i = 0; i < 0x1a; i ++)
534 qemu_get_be32s(f, &s->mm_regs[i]);
535
536 return 0;
537 }
538
539 /* Synchronous Serial Ports */
540 typedef struct {
541 SysBusDevice busdev;
542 qemu_irq irq;
543 int enable;
544 SSIBus *bus;
545
546 uint32_t sscr[2];
547 uint32_t sspsp;
548 uint32_t ssto;
549 uint32_t ssitr;
550 uint32_t sssr;
551 uint8_t sstsa;
552 uint8_t ssrsa;
553 uint8_t ssacd;
554
555 uint32_t rx_fifo[16];
556 int rx_level;
557 int rx_start;
558 } PXA2xxSSPState;
559
560 #define SSCR0 0x00 /* SSP Control register 0 */
561 #define SSCR1 0x04 /* SSP Control register 1 */
562 #define SSSR 0x08 /* SSP Status register */
563 #define SSITR 0x0c /* SSP Interrupt Test register */
564 #define SSDR 0x10 /* SSP Data register */
565 #define SSTO 0x28 /* SSP Time-Out register */
566 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
567 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
568 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
569 #define SSTSS 0x38 /* SSP Time Slot Status register */
570 #define SSACD 0x3c /* SSP Audio Clock Divider register */
571
572 /* Bitfields for above registers */
573 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
574 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
575 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
576 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
577 #define SSCR0_SSE (1 << 7)
578 #define SSCR0_RIM (1 << 22)
579 #define SSCR0_TIM (1 << 23)
580 #define SSCR0_MOD (1 << 31)
581 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
582 #define SSCR1_RIE (1 << 0)
583 #define SSCR1_TIE (1 << 1)
584 #define SSCR1_LBM (1 << 2)
585 #define SSCR1_MWDS (1 << 5)
586 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
587 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
588 #define SSCR1_EFWR (1 << 14)
589 #define SSCR1_PINTE (1 << 18)
590 #define SSCR1_TINTE (1 << 19)
591 #define SSCR1_RSRE (1 << 20)
592 #define SSCR1_TSRE (1 << 21)
593 #define SSCR1_EBCEI (1 << 29)
594 #define SSITR_INT (7 << 5)
595 #define SSSR_TNF (1 << 2)
596 #define SSSR_RNE (1 << 3)
597 #define SSSR_TFS (1 << 5)
598 #define SSSR_RFS (1 << 6)
599 #define SSSR_ROR (1 << 7)
600 #define SSSR_PINT (1 << 18)
601 #define SSSR_TINT (1 << 19)
602 #define SSSR_EOC (1 << 20)
603 #define SSSR_TUR (1 << 21)
604 #define SSSR_BCE (1 << 23)
605 #define SSSR_RW 0x00bc0080
606
607 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
608 {
609 int level = 0;
610
611 level |= s->ssitr & SSITR_INT;
612 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
613 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
614 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
615 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
616 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
617 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
618 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
619 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
620 qemu_set_irq(s->irq, !!level);
621 }
622
623 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
624 {
625 s->sssr &= ~(0xf << 12); /* Clear RFL */
626 s->sssr &= ~(0xf << 8); /* Clear TFL */
627 s->sssr &= ~SSSR_TFS;
628 s->sssr &= ~SSSR_TNF;
629 if (s->enable) {
630 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
631 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
632 s->sssr |= SSSR_RFS;
633 else
634 s->sssr &= ~SSSR_RFS;
635 if (s->rx_level)
636 s->sssr |= SSSR_RNE;
637 else
638 s->sssr &= ~SSSR_RNE;
639 /* TX FIFO is never filled, so it is always in underrun
640 condition if SSP is enabled */
641 s->sssr |= SSSR_TFS;
642 s->sssr |= SSSR_TNF;
643 }
644
645 pxa2xx_ssp_int_update(s);
646 }
647
648 static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
649 {
650 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
651 uint32_t retval;
652
653 switch (addr) {
654 case SSCR0:
655 return s->sscr[0];
656 case SSCR1:
657 return s->sscr[1];
658 case SSPSP:
659 return s->sspsp;
660 case SSTO:
661 return s->ssto;
662 case SSITR:
663 return s->ssitr;
664 case SSSR:
665 return s->sssr | s->ssitr;
666 case SSDR:
667 if (!s->enable)
668 return 0xffffffff;
669 if (s->rx_level < 1) {
670 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
671 return 0xffffffff;
672 }
673 s->rx_level --;
674 retval = s->rx_fifo[s->rx_start ++];
675 s->rx_start &= 0xf;
676 pxa2xx_ssp_fifo_update(s);
677 return retval;
678 case SSTSA:
679 return s->sstsa;
680 case SSRSA:
681 return s->ssrsa;
682 case SSTSS:
683 return 0;
684 case SSACD:
685 return s->ssacd;
686 default:
687 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
688 break;
689 }
690 return 0;
691 }
692
693 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
694 uint32_t value)
695 {
696 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
697
698 switch (addr) {
699 case SSCR0:
700 s->sscr[0] = value & 0xc7ffffff;
701 s->enable = value & SSCR0_SSE;
702 if (value & SSCR0_MOD)
703 printf("%s: Attempt to use network mode\n", __FUNCTION__);
704 if (s->enable && SSCR0_DSS(value) < 4)
705 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
706 SSCR0_DSS(value));
707 if (!(value & SSCR0_SSE)) {
708 s->sssr = 0;
709 s->ssitr = 0;
710 s->rx_level = 0;
711 }
712 pxa2xx_ssp_fifo_update(s);
713 break;
714
715 case SSCR1:
716 s->sscr[1] = value;
717 if (value & (SSCR1_LBM | SSCR1_EFWR))
718 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
719 pxa2xx_ssp_fifo_update(s);
720 break;
721
722 case SSPSP:
723 s->sspsp = value;
724 break;
725
726 case SSTO:
727 s->ssto = value;
728 break;
729
730 case SSITR:
731 s->ssitr = value & SSITR_INT;
732 pxa2xx_ssp_int_update(s);
733 break;
734
735 case SSSR:
736 s->sssr &= ~(value & SSSR_RW);
737 pxa2xx_ssp_int_update(s);
738 break;
739
740 case SSDR:
741 if (SSCR0_UWIRE(s->sscr[0])) {
742 if (s->sscr[1] & SSCR1_MWDS)
743 value &= 0xffff;
744 else
745 value &= 0xff;
746 } else
747 /* Note how 32bits overflow does no harm here */
748 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
749
750 /* Data goes from here to the Tx FIFO and is shifted out from
751 * there directly to the slave, no need to buffer it.
752 */
753 if (s->enable) {
754 uint32_t readval;
755 readval = ssi_transfer(s->bus, value);
756 if (s->rx_level < 0x10) {
757 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
758 } else {
759 s->sssr |= SSSR_ROR;
760 }
761 }
762 pxa2xx_ssp_fifo_update(s);
763 break;
764
765 case SSTSA:
766 s->sstsa = value;
767 break;
768
769 case SSRSA:
770 s->ssrsa = value;
771 break;
772
773 case SSACD:
774 s->ssacd = value;
775 break;
776
777 default:
778 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
779 break;
780 }
781 }
782
783 static CPUReadMemoryFunc * const pxa2xx_ssp_readfn[] = {
784 pxa2xx_ssp_read,
785 pxa2xx_ssp_read,
786 pxa2xx_ssp_read,
787 };
788
789 static CPUWriteMemoryFunc * const pxa2xx_ssp_writefn[] = {
790 pxa2xx_ssp_write,
791 pxa2xx_ssp_write,
792 pxa2xx_ssp_write,
793 };
794
795 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
796 {
797 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
798 int i;
799
800 qemu_put_be32(f, s->enable);
801
802 qemu_put_be32s(f, &s->sscr[0]);
803 qemu_put_be32s(f, &s->sscr[1]);
804 qemu_put_be32s(f, &s->sspsp);
805 qemu_put_be32s(f, &s->ssto);
806 qemu_put_be32s(f, &s->ssitr);
807 qemu_put_be32s(f, &s->sssr);
808 qemu_put_8s(f, &s->sstsa);
809 qemu_put_8s(f, &s->ssrsa);
810 qemu_put_8s(f, &s->ssacd);
811
812 qemu_put_byte(f, s->rx_level);
813 for (i = 0; i < s->rx_level; i ++)
814 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
815 }
816
817 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
818 {
819 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
820 int i;
821
822 s->enable = qemu_get_be32(f);
823
824 qemu_get_be32s(f, &s->sscr[0]);
825 qemu_get_be32s(f, &s->sscr[1]);
826 qemu_get_be32s(f, &s->sspsp);
827 qemu_get_be32s(f, &s->ssto);
828 qemu_get_be32s(f, &s->ssitr);
829 qemu_get_be32s(f, &s->sssr);
830 qemu_get_8s(f, &s->sstsa);
831 qemu_get_8s(f, &s->ssrsa);
832 qemu_get_8s(f, &s->ssacd);
833
834 s->rx_level = qemu_get_byte(f);
835 s->rx_start = 0;
836 for (i = 0; i < s->rx_level; i ++)
837 s->rx_fifo[i] = qemu_get_byte(f);
838
839 return 0;
840 }
841
842 static int pxa2xx_ssp_init(SysBusDevice *dev)
843 {
844 int iomemtype;
845 PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);
846
847 sysbus_init_irq(dev, &s->irq);
848
849 iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,
850 pxa2xx_ssp_writefn, s,
851 DEVICE_NATIVE_ENDIAN);
852 sysbus_init_mmio(dev, 0x1000, iomemtype);
853 register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
854 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
855
856 s->bus = ssi_create_bus(&dev->qdev, "ssi");
857 return 0;
858 }
859
860 /* Real-Time Clock */
861 #define RCNR 0x00 /* RTC Counter register */
862 #define RTAR 0x04 /* RTC Alarm register */
863 #define RTSR 0x08 /* RTC Status register */
864 #define RTTR 0x0c /* RTC Timer Trim register */
865 #define RDCR 0x10 /* RTC Day Counter register */
866 #define RYCR 0x14 /* RTC Year Counter register */
867 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
868 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
869 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
870 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
871 #define SWCR 0x28 /* RTC Stopwatch Counter register */
872 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
873 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
874 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
875 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
876
877 typedef struct {
878 SysBusDevice busdev;
879 uint32_t rttr;
880 uint32_t rtsr;
881 uint32_t rtar;
882 uint32_t rdar1;
883 uint32_t rdar2;
884 uint32_t ryar1;
885 uint32_t ryar2;
886 uint32_t swar1;
887 uint32_t swar2;
888 uint32_t piar;
889 uint32_t last_rcnr;
890 uint32_t last_rdcr;
891 uint32_t last_rycr;
892 uint32_t last_swcr;
893 uint32_t last_rtcpicr;
894 int64_t last_hz;
895 int64_t last_sw;
896 int64_t last_pi;
897 QEMUTimer *rtc_hz;
898 QEMUTimer *rtc_rdal1;
899 QEMUTimer *rtc_rdal2;
900 QEMUTimer *rtc_swal1;
901 QEMUTimer *rtc_swal2;
902 QEMUTimer *rtc_pi;
903 qemu_irq rtc_irq;
904 } PXA2xxRTCState;
905
906 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
907 {
908 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
909 }
910
911 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
912 {
913 int64_t rt = qemu_get_clock_ms(rt_clock);
914 s->last_rcnr += ((rt - s->last_hz) << 15) /
915 (1000 * ((s->rttr & 0xffff) + 1));
916 s->last_rdcr += ((rt - s->last_hz) << 15) /
917 (1000 * ((s->rttr & 0xffff) + 1));
918 s->last_hz = rt;
919 }
920
921 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
922 {
923 int64_t rt = qemu_get_clock_ms(rt_clock);
924 if (s->rtsr & (1 << 12))
925 s->last_swcr += (rt - s->last_sw) / 10;
926 s->last_sw = rt;
927 }
928
929 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
930 {
931 int64_t rt = qemu_get_clock_ms(rt_clock);
932 if (s->rtsr & (1 << 15))
933 s->last_swcr += rt - s->last_pi;
934 s->last_pi = rt;
935 }
936
937 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
938 uint32_t rtsr)
939 {
940 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
941 qemu_mod_timer(s->rtc_hz, s->last_hz +
942 (((s->rtar - s->last_rcnr) * 1000 *
943 ((s->rttr & 0xffff) + 1)) >> 15));
944 else
945 qemu_del_timer(s->rtc_hz);
946
947 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
948 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
949 (((s->rdar1 - s->last_rdcr) * 1000 *
950 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
951 else
952 qemu_del_timer(s->rtc_rdal1);
953
954 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
955 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
956 (((s->rdar2 - s->last_rdcr) * 1000 *
957 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
958 else
959 qemu_del_timer(s->rtc_rdal2);
960
961 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
962 qemu_mod_timer(s->rtc_swal1, s->last_sw +
963 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
964 else
965 qemu_del_timer(s->rtc_swal1);
966
967 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
968 qemu_mod_timer(s->rtc_swal2, s->last_sw +
969 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
970 else
971 qemu_del_timer(s->rtc_swal2);
972
973 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
974 qemu_mod_timer(s->rtc_pi, s->last_pi +
975 (s->piar & 0xffff) - s->last_rtcpicr);
976 else
977 qemu_del_timer(s->rtc_pi);
978 }
979
980 static inline void pxa2xx_rtc_hz_tick(void *opaque)
981 {
982 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
983 s->rtsr |= (1 << 0);
984 pxa2xx_rtc_alarm_update(s, s->rtsr);
985 pxa2xx_rtc_int_update(s);
986 }
987
988 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
989 {
990 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
991 s->rtsr |= (1 << 4);
992 pxa2xx_rtc_alarm_update(s, s->rtsr);
993 pxa2xx_rtc_int_update(s);
994 }
995
996 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
997 {
998 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
999 s->rtsr |= (1 << 6);
1000 pxa2xx_rtc_alarm_update(s, s->rtsr);
1001 pxa2xx_rtc_int_update(s);
1002 }
1003
1004 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
1005 {
1006 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1007 s->rtsr |= (1 << 8);
1008 pxa2xx_rtc_alarm_update(s, s->rtsr);
1009 pxa2xx_rtc_int_update(s);
1010 }
1011
1012 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
1013 {
1014 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1015 s->rtsr |= (1 << 10);
1016 pxa2xx_rtc_alarm_update(s, s->rtsr);
1017 pxa2xx_rtc_int_update(s);
1018 }
1019
1020 static inline void pxa2xx_rtc_pi_tick(void *opaque)
1021 {
1022 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1023 s->rtsr |= (1 << 13);
1024 pxa2xx_rtc_piupdate(s);
1025 s->last_rtcpicr = 0;
1026 pxa2xx_rtc_alarm_update(s, s->rtsr);
1027 pxa2xx_rtc_int_update(s);
1028 }
1029
1030 static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1031 {
1032 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1033
1034 switch (addr) {
1035 case RTTR:
1036 return s->rttr;
1037 case RTSR:
1038 return s->rtsr;
1039 case RTAR:
1040 return s->rtar;
1041 case RDAR1:
1042 return s->rdar1;
1043 case RDAR2:
1044 return s->rdar2;
1045 case RYAR1:
1046 return s->ryar1;
1047 case RYAR2:
1048 return s->ryar2;
1049 case SWAR1:
1050 return s->swar1;
1051 case SWAR2:
1052 return s->swar2;
1053 case PIAR:
1054 return s->piar;
1055 case RCNR:
1056 return s->last_rcnr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
1057 (1000 * ((s->rttr & 0xffff) + 1));
1058 case RDCR:
1059 return s->last_rdcr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
1060 (1000 * ((s->rttr & 0xffff) + 1));
1061 case RYCR:
1062 return s->last_rycr;
1063 case SWCR:
1064 if (s->rtsr & (1 << 12))
1065 return s->last_swcr + (qemu_get_clock_ms(rt_clock) - s->last_sw) / 10;
1066 else
1067 return s->last_swcr;
1068 default:
1069 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1070 break;
1071 }
1072 return 0;
1073 }
1074
1075 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1076 uint32_t value)
1077 {
1078 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1079
1080 switch (addr) {
1081 case RTTR:
1082 if (!(s->rttr & (1 << 31))) {
1083 pxa2xx_rtc_hzupdate(s);
1084 s->rttr = value;
1085 pxa2xx_rtc_alarm_update(s, s->rtsr);
1086 }
1087 break;
1088
1089 case RTSR:
1090 if ((s->rtsr ^ value) & (1 << 15))
1091 pxa2xx_rtc_piupdate(s);
1092
1093 if ((s->rtsr ^ value) & (1 << 12))
1094 pxa2xx_rtc_swupdate(s);
1095
1096 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1097 pxa2xx_rtc_alarm_update(s, value);
1098
1099 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1100 pxa2xx_rtc_int_update(s);
1101 break;
1102
1103 case RTAR:
1104 s->rtar = value;
1105 pxa2xx_rtc_alarm_update(s, s->rtsr);
1106 break;
1107
1108 case RDAR1:
1109 s->rdar1 = value;
1110 pxa2xx_rtc_alarm_update(s, s->rtsr);
1111 break;
1112
1113 case RDAR2:
1114 s->rdar2 = value;
1115 pxa2xx_rtc_alarm_update(s, s->rtsr);
1116 break;
1117
1118 case RYAR1:
1119 s->ryar1 = value;
1120 pxa2xx_rtc_alarm_update(s, s->rtsr);
1121 break;
1122
1123 case RYAR2:
1124 s->ryar2 = value;
1125 pxa2xx_rtc_alarm_update(s, s->rtsr);
1126 break;
1127
1128 case SWAR1:
1129 pxa2xx_rtc_swupdate(s);
1130 s->swar1 = value;
1131 s->last_swcr = 0;
1132 pxa2xx_rtc_alarm_update(s, s->rtsr);
1133 break;
1134
1135 case SWAR2:
1136 s->swar2 = value;
1137 pxa2xx_rtc_alarm_update(s, s->rtsr);
1138 break;
1139
1140 case PIAR:
1141 s->piar = value;
1142 pxa2xx_rtc_alarm_update(s, s->rtsr);
1143 break;
1144
1145 case RCNR:
1146 pxa2xx_rtc_hzupdate(s);
1147 s->last_rcnr = value;
1148 pxa2xx_rtc_alarm_update(s, s->rtsr);
1149 break;
1150
1151 case RDCR:
1152 pxa2xx_rtc_hzupdate(s);
1153 s->last_rdcr = value;
1154 pxa2xx_rtc_alarm_update(s, s->rtsr);
1155 break;
1156
1157 case RYCR:
1158 s->last_rycr = value;
1159 break;
1160
1161 case SWCR:
1162 pxa2xx_rtc_swupdate(s);
1163 s->last_swcr = value;
1164 pxa2xx_rtc_alarm_update(s, s->rtsr);
1165 break;
1166
1167 case RTCPICR:
1168 pxa2xx_rtc_piupdate(s);
1169 s->last_rtcpicr = value & 0xffff;
1170 pxa2xx_rtc_alarm_update(s, s->rtsr);
1171 break;
1172
1173 default:
1174 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1175 }
1176 }
1177
1178 static CPUReadMemoryFunc * const pxa2xx_rtc_readfn[] = {
1179 pxa2xx_rtc_read,
1180 pxa2xx_rtc_read,
1181 pxa2xx_rtc_read,
1182 };
1183
1184 static CPUWriteMemoryFunc * const pxa2xx_rtc_writefn[] = {
1185 pxa2xx_rtc_write,
1186 pxa2xx_rtc_write,
1187 pxa2xx_rtc_write,
1188 };
1189
1190 static int pxa2xx_rtc_init(SysBusDevice *dev)
1191 {
1192 PXA2xxRTCState *s = FROM_SYSBUS(PXA2xxRTCState, dev);
1193 struct tm tm;
1194 int wom;
1195 int iomemtype;
1196
1197 s->rttr = 0x7fff;
1198 s->rtsr = 0;
1199
1200 qemu_get_timedate(&tm, 0);
1201 wom = ((tm.tm_mday - 1) / 7) + 1;
1202
1203 s->last_rcnr = (uint32_t) mktimegm(&tm);
1204 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1205 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1206 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1207 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1208 s->last_swcr = (tm.tm_hour << 19) |
1209 (tm.tm_min << 13) | (tm.tm_sec << 7);
1210 s->last_rtcpicr = 0;
1211 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rt_clock);
1212
1213 s->rtc_hz = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_hz_tick, s);
1214 s->rtc_rdal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1215 s->rtc_rdal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1216 s->rtc_swal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal1_tick, s);
1217 s->rtc_swal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal2_tick, s);
1218 s->rtc_pi = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_pi_tick, s);
1219
1220 sysbus_init_irq(dev, &s->rtc_irq);
1221
1222 iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
1223 pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
1224 sysbus_init_mmio(dev, 0x10000, iomemtype);
1225
1226 return 0;
1227 }
1228
1229 static void pxa2xx_rtc_pre_save(void *opaque)
1230 {
1231 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1232
1233 pxa2xx_rtc_hzupdate(s);
1234 pxa2xx_rtc_piupdate(s);
1235 pxa2xx_rtc_swupdate(s);
1236 }
1237
1238 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1239 {
1240 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1241
1242 pxa2xx_rtc_alarm_update(s, s->rtsr);
1243
1244 return 0;
1245 }
1246
1247 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1248 .name = "pxa2xx_rtc",
1249 .version_id = 0,
1250 .minimum_version_id = 0,
1251 .minimum_version_id_old = 0,
1252 .pre_save = pxa2xx_rtc_pre_save,
1253 .post_load = pxa2xx_rtc_post_load,
1254 .fields = (VMStateField[]) {
1255 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1256 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1257 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1258 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1259 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1260 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1261 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1262 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1263 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1264 VMSTATE_UINT32(piar, PXA2xxRTCState),
1265 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1266 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1267 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1268 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1269 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1270 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1271 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1272 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1273 VMSTATE_END_OF_LIST(),
1274 },
1275 };
1276
1277 static SysBusDeviceInfo pxa2xx_rtc_sysbus_info = {
1278 .init = pxa2xx_rtc_init,
1279 .qdev.name = "pxa2xx_rtc",
1280 .qdev.desc = "PXA2xx RTC Controller",
1281 .qdev.size = sizeof(PXA2xxRTCState),
1282 .qdev.vmsd = &vmstate_pxa2xx_rtc_regs,
1283 };
1284
1285 /* I2C Interface */
1286 typedef struct {
1287 i2c_slave i2c;
1288 PXA2xxI2CState *host;
1289 } PXA2xxI2CSlaveState;
1290
1291 struct PXA2xxI2CState {
1292 SysBusDevice busdev;
1293 PXA2xxI2CSlaveState *slave;
1294 i2c_bus *bus;
1295 qemu_irq irq;
1296 uint32_t offset;
1297 uint32_t region_size;
1298
1299 uint16_t control;
1300 uint16_t status;
1301 uint8_t ibmr;
1302 uint8_t data;
1303 };
1304
1305 #define IBMR 0x80 /* I2C Bus Monitor register */
1306 #define IDBR 0x88 /* I2C Data Buffer register */
1307 #define ICR 0x90 /* I2C Control register */
1308 #define ISR 0x98 /* I2C Status register */
1309 #define ISAR 0xa0 /* I2C Slave Address register */
1310
1311 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1312 {
1313 uint16_t level = 0;
1314 level |= s->status & s->control & (1 << 10); /* BED */
1315 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1316 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1317 level |= s->status & (1 << 9); /* SAD */
1318 qemu_set_irq(s->irq, !!level);
1319 }
1320
1321 /* These are only stubs now. */
1322 static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1323 {
1324 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1325 PXA2xxI2CState *s = slave->host;
1326
1327 switch (event) {
1328 case I2C_START_SEND:
1329 s->status |= (1 << 9); /* set SAD */
1330 s->status &= ~(1 << 0); /* clear RWM */
1331 break;
1332 case I2C_START_RECV:
1333 s->status |= (1 << 9); /* set SAD */
1334 s->status |= 1 << 0; /* set RWM */
1335 break;
1336 case I2C_FINISH:
1337 s->status |= (1 << 4); /* set SSD */
1338 break;
1339 case I2C_NACK:
1340 s->status |= 1 << 1; /* set ACKNAK */
1341 break;
1342 }
1343 pxa2xx_i2c_update(s);
1344 }
1345
1346 static int pxa2xx_i2c_rx(i2c_slave *i2c)
1347 {
1348 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1349 PXA2xxI2CState *s = slave->host;
1350 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1351 return 0;
1352
1353 if (s->status & (1 << 0)) { /* RWM */
1354 s->status |= 1 << 6; /* set ITE */
1355 }
1356 pxa2xx_i2c_update(s);
1357
1358 return s->data;
1359 }
1360
1361 static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1362 {
1363 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1364 PXA2xxI2CState *s = slave->host;
1365 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1366 return 1;
1367
1368 if (!(s->status & (1 << 0))) { /* RWM */
1369 s->status |= 1 << 7; /* set IRF */
1370 s->data = data;
1371 }
1372 pxa2xx_i2c_update(s);
1373
1374 return 1;
1375 }
1376
1377 static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1378 {
1379 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1380
1381 addr -= s->offset;
1382 switch (addr) {
1383 case ICR:
1384 return s->control;
1385 case ISR:
1386 return s->status | (i2c_bus_busy(s->bus) << 2);
1387 case ISAR:
1388 return s->slave->i2c.address;
1389 case IDBR:
1390 return s->data;
1391 case IBMR:
1392 if (s->status & (1 << 2))
1393 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1394 else
1395 s->ibmr = 0;
1396 return s->ibmr;
1397 default:
1398 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1399 break;
1400 }
1401 return 0;
1402 }
1403
1404 static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1405 uint32_t value)
1406 {
1407 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1408 int ack;
1409
1410 addr -= s->offset;
1411 switch (addr) {
1412 case ICR:
1413 s->control = value & 0xfff7;
1414 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1415 /* TODO: slave mode */
1416 if (value & (1 << 0)) { /* START condition */
1417 if (s->data & 1)
1418 s->status |= 1 << 0; /* set RWM */
1419 else
1420 s->status &= ~(1 << 0); /* clear RWM */
1421 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1422 } else {
1423 if (s->status & (1 << 0)) { /* RWM */
1424 s->data = i2c_recv(s->bus);
1425 if (value & (1 << 2)) /* ACKNAK */
1426 i2c_nack(s->bus);
1427 ack = 1;
1428 } else
1429 ack = !i2c_send(s->bus, s->data);
1430 }
1431
1432 if (value & (1 << 1)) /* STOP condition */
1433 i2c_end_transfer(s->bus);
1434
1435 if (ack) {
1436 if (value & (1 << 0)) /* START condition */
1437 s->status |= 1 << 6; /* set ITE */
1438 else
1439 if (s->status & (1 << 0)) /* RWM */
1440 s->status |= 1 << 7; /* set IRF */
1441 else
1442 s->status |= 1 << 6; /* set ITE */
1443 s->status &= ~(1 << 1); /* clear ACKNAK */
1444 } else {
1445 s->status |= 1 << 6; /* set ITE */
1446 s->status |= 1 << 10; /* set BED */
1447 s->status |= 1 << 1; /* set ACKNAK */
1448 }
1449 }
1450 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1451 if (value & (1 << 4)) /* MA */
1452 i2c_end_transfer(s->bus);
1453 pxa2xx_i2c_update(s);
1454 break;
1455
1456 case ISR:
1457 s->status &= ~(value & 0x07f0);
1458 pxa2xx_i2c_update(s);
1459 break;
1460
1461 case ISAR:
1462 i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
1463 break;
1464
1465 case IDBR:
1466 s->data = value & 0xff;
1467 break;
1468
1469 default:
1470 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1471 }
1472 }
1473
1474 static CPUReadMemoryFunc * const pxa2xx_i2c_readfn[] = {
1475 pxa2xx_i2c_read,
1476 pxa2xx_i2c_read,
1477 pxa2xx_i2c_read,
1478 };
1479
1480 static CPUWriteMemoryFunc * const pxa2xx_i2c_writefn[] = {
1481 pxa2xx_i2c_write,
1482 pxa2xx_i2c_write,
1483 pxa2xx_i2c_write,
1484 };
1485
1486 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1487 .name = "pxa2xx_i2c_slave",
1488 .version_id = 1,
1489 .minimum_version_id = 1,
1490 .minimum_version_id_old = 1,
1491 .fields = (VMStateField []) {
1492 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState),
1493 VMSTATE_END_OF_LIST()
1494 }
1495 };
1496
1497 static const VMStateDescription vmstate_pxa2xx_i2c = {
1498 .name = "pxa2xx_i2c",
1499 .version_id = 1,
1500 .minimum_version_id = 1,
1501 .minimum_version_id_old = 1,
1502 .fields = (VMStateField []) {
1503 VMSTATE_UINT16(control, PXA2xxI2CState),
1504 VMSTATE_UINT16(status, PXA2xxI2CState),
1505 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1506 VMSTATE_UINT8(data, PXA2xxI2CState),
1507 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1508 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *),
1509 VMSTATE_END_OF_LIST()
1510 }
1511 };
1512
1513 static int pxa2xx_i2c_slave_init(i2c_slave *i2c)
1514 {
1515 /* Nothing to do. */
1516 return 0;
1517 }
1518
1519 static I2CSlaveInfo pxa2xx_i2c_slave_info = {
1520 .qdev.name = "pxa2xx-i2c-slave",
1521 .qdev.size = sizeof(PXA2xxI2CSlaveState),
1522 .init = pxa2xx_i2c_slave_init,
1523 .event = pxa2xx_i2c_event,
1524 .recv = pxa2xx_i2c_rx,
1525 .send = pxa2xx_i2c_tx
1526 };
1527
1528 PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
1529 qemu_irq irq, uint32_t region_size)
1530 {
1531 DeviceState *dev;
1532 SysBusDevice *i2c_dev;
1533 PXA2xxI2CState *s;
1534
1535 i2c_dev = sysbus_from_qdev(qdev_create(NULL, "pxa2xx_i2c"));
1536 qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1);
1537 qdev_prop_set_uint32(&i2c_dev->qdev, "offset",
1538 base - (base & (~region_size) & TARGET_PAGE_MASK));
1539
1540 qdev_init_nofail(&i2c_dev->qdev);
1541
1542 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1543 sysbus_connect_irq(i2c_dev, 0, irq);
1544
1545 s = FROM_SYSBUS(PXA2xxI2CState, i2c_dev);
1546 /* FIXME: Should the slave device really be on a separate bus? */
1547 dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0);
1548 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev));
1549 s->slave->host = s;
1550
1551 return s;
1552 }
1553
1554 static int pxa2xx_i2c_initfn(SysBusDevice *dev)
1555 {
1556 PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev);
1557 int iomemtype;
1558
1559 s->bus = i2c_init_bus(&dev->qdev, "i2c");
1560
1561 iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn,
1562 pxa2xx_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
1563 sysbus_init_mmio(dev, s->region_size, iomemtype);
1564 sysbus_init_irq(dev, &s->irq);
1565
1566 return 0;
1567 }
1568
1569 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1570 {
1571 return s->bus;
1572 }
1573
1574 static SysBusDeviceInfo pxa2xx_i2c_info = {
1575 .init = pxa2xx_i2c_initfn,
1576 .qdev.name = "pxa2xx_i2c",
1577 .qdev.desc = "PXA2xx I2C Bus Controller",
1578 .qdev.size = sizeof(PXA2xxI2CState),
1579 .qdev.vmsd = &vmstate_pxa2xx_i2c,
1580 .qdev.props = (Property[]) {
1581 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1582 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1583 DEFINE_PROP_END_OF_LIST(),
1584 },
1585 };
1586
1587 /* PXA Inter-IC Sound Controller */
1588 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1589 {
1590 i2s->rx_len = 0;
1591 i2s->tx_len = 0;
1592 i2s->fifo_len = 0;
1593 i2s->clk = 0x1a;
1594 i2s->control[0] = 0x00;
1595 i2s->control[1] = 0x00;
1596 i2s->status = 0x00;
1597 i2s->mask = 0x00;
1598 }
1599
1600 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1601 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1602 #define SACR_DREC(val) (val & (1 << 3))
1603 #define SACR_DPRL(val) (val & (1 << 4))
1604
1605 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1606 {
1607 int rfs, tfs;
1608 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1609 !SACR_DREC(i2s->control[1]);
1610 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1611 i2s->enable && !SACR_DPRL(i2s->control[1]);
1612
1613 qemu_set_irq(i2s->rx_dma, rfs);
1614 qemu_set_irq(i2s->tx_dma, tfs);
1615
1616 i2s->status &= 0xe0;
1617 if (i2s->fifo_len < 16 || !i2s->enable)
1618 i2s->status |= 1 << 0; /* TNF */
1619 if (i2s->rx_len)
1620 i2s->status |= 1 << 1; /* RNE */
1621 if (i2s->enable)
1622 i2s->status |= 1 << 2; /* BSY */
1623 if (tfs)
1624 i2s->status |= 1 << 3; /* TFS */
1625 if (rfs)
1626 i2s->status |= 1 << 4; /* RFS */
1627 if (!(i2s->tx_len && i2s->enable))
1628 i2s->status |= i2s->fifo_len << 8; /* TFL */
1629 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1630
1631 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1632 }
1633
1634 #define SACR0 0x00 /* Serial Audio Global Control register */
1635 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1636 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1637 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1638 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1639 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1640 #define SADR 0x80 /* Serial Audio Data register */
1641
1642 static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1643 {
1644 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1645
1646 switch (addr) {
1647 case SACR0:
1648 return s->control[0];
1649 case SACR1:
1650 return s->control[1];
1651 case SASR0:
1652 return s->status;
1653 case SAIMR:
1654 return s->mask;
1655 case SAICR:
1656 return 0;
1657 case SADIV:
1658 return s->clk;
1659 case SADR:
1660 if (s->rx_len > 0) {
1661 s->rx_len --;
1662 pxa2xx_i2s_update(s);
1663 return s->codec_in(s->opaque);
1664 }
1665 return 0;
1666 default:
1667 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1668 break;
1669 }
1670 return 0;
1671 }
1672
1673 static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1674 uint32_t value)
1675 {
1676 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1677 uint32_t *sample;
1678
1679 switch (addr) {
1680 case SACR0:
1681 if (value & (1 << 3)) /* RST */
1682 pxa2xx_i2s_reset(s);
1683 s->control[0] = value & 0xff3d;
1684 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1685 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1686 s->codec_out(s->opaque, *sample);
1687 s->status &= ~(1 << 7); /* I2SOFF */
1688 }
1689 if (value & (1 << 4)) /* EFWR */
1690 printf("%s: Attempt to use special function\n", __FUNCTION__);
1691 s->enable = (value & 9) == 1; /* ENB && !RST*/
1692 pxa2xx_i2s_update(s);
1693 break;
1694 case SACR1:
1695 s->control[1] = value & 0x0039;
1696 if (value & (1 << 5)) /* ENLBF */
1697 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1698 if (value & (1 << 4)) /* DPRL */
1699 s->fifo_len = 0;
1700 pxa2xx_i2s_update(s);
1701 break;
1702 case SAIMR:
1703 s->mask = value & 0x0078;
1704 pxa2xx_i2s_update(s);
1705 break;
1706 case SAICR:
1707 s->status &= ~(value & (3 << 5));
1708 pxa2xx_i2s_update(s);
1709 break;
1710 case SADIV:
1711 s->clk = value & 0x007f;
1712 break;
1713 case SADR:
1714 if (s->tx_len && s->enable) {
1715 s->tx_len --;
1716 pxa2xx_i2s_update(s);
1717 s->codec_out(s->opaque, value);
1718 } else if (s->fifo_len < 16) {
1719 s->fifo[s->fifo_len ++] = value;
1720 pxa2xx_i2s_update(s);
1721 }
1722 break;
1723 default:
1724 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1725 }
1726 }
1727
1728 static CPUReadMemoryFunc * const pxa2xx_i2s_readfn[] = {
1729 pxa2xx_i2s_read,
1730 pxa2xx_i2s_read,
1731 pxa2xx_i2s_read,
1732 };
1733
1734 static CPUWriteMemoryFunc * const pxa2xx_i2s_writefn[] = {
1735 pxa2xx_i2s_write,
1736 pxa2xx_i2s_write,
1737 pxa2xx_i2s_write,
1738 };
1739
1740 static const VMStateDescription vmstate_pxa2xx_i2s = {
1741 .name = "pxa2xx_i2s",
1742 .version_id = 0,
1743 .minimum_version_id = 0,
1744 .minimum_version_id_old = 0,
1745 .fields = (VMStateField[]) {
1746 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1747 VMSTATE_UINT32(status, PXA2xxI2SState),
1748 VMSTATE_UINT32(mask, PXA2xxI2SState),
1749 VMSTATE_UINT32(clk, PXA2xxI2SState),
1750 VMSTATE_INT32(enable, PXA2xxI2SState),
1751 VMSTATE_INT32(rx_len, PXA2xxI2SState),
1752 VMSTATE_INT32(tx_len, PXA2xxI2SState),
1753 VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1754 VMSTATE_END_OF_LIST()
1755 }
1756 };
1757
1758 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1759 {
1760 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1761 uint32_t *sample;
1762
1763 /* Signal FIFO errors */
1764 if (s->enable && s->tx_len)
1765 s->status |= 1 << 5; /* TUR */
1766 if (s->enable && s->rx_len)
1767 s->status |= 1 << 6; /* ROR */
1768
1769 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1770 * handle the cases where it makes a difference. */
1771 s->tx_len = tx - s->fifo_len;
1772 s->rx_len = rx;
1773 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1774 if (s->enable)
1775 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1776 s->codec_out(s->opaque, *sample);
1777 pxa2xx_i2s_update(s);
1778 }
1779
1780 static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
1781 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1782 {
1783 int iomemtype;
1784 PXA2xxI2SState *s = (PXA2xxI2SState *)
1785 qemu_mallocz(sizeof(PXA2xxI2SState));
1786
1787 s->irq = irq;
1788 s->rx_dma = rx_dma;
1789 s->tx_dma = tx_dma;
1790 s->data_req = pxa2xx_i2s_data_req;
1791
1792 pxa2xx_i2s_reset(s);
1793
1794 iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn,
1795 pxa2xx_i2s_writefn, s, DEVICE_NATIVE_ENDIAN);
1796 cpu_register_physical_memory(base, 0x100000, iomemtype);
1797
1798 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1799
1800 return s;
1801 }
1802
1803 /* PXA Fast Infra-red Communications Port */
1804 struct PXA2xxFIrState {
1805 qemu_irq irq;
1806 qemu_irq rx_dma;
1807 qemu_irq tx_dma;
1808 int enable;
1809 CharDriverState *chr;
1810
1811 uint8_t control[3];
1812 uint8_t status[2];
1813
1814 int rx_len;
1815 int rx_start;
1816 uint8_t rx_fifo[64];
1817 };
1818
1819 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1820 {
1821 s->control[0] = 0x00;
1822 s->control[1] = 0x00;
1823 s->control[2] = 0x00;
1824 s->status[0] = 0x00;
1825 s->status[1] = 0x00;
1826 s->enable = 0;
1827 }
1828
1829 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1830 {
1831 static const int tresh[4] = { 8, 16, 32, 0 };
1832 int intr = 0;
1833 if ((s->control[0] & (1 << 4)) && /* RXE */
1834 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1835 s->status[0] |= 1 << 4; /* RFS */
1836 else
1837 s->status[0] &= ~(1 << 4); /* RFS */
1838 if (s->control[0] & (1 << 3)) /* TXE */
1839 s->status[0] |= 1 << 3; /* TFS */
1840 else
1841 s->status[0] &= ~(1 << 3); /* TFS */
1842 if (s->rx_len)
1843 s->status[1] |= 1 << 2; /* RNE */
1844 else
1845 s->status[1] &= ~(1 << 2); /* RNE */
1846 if (s->control[0] & (1 << 4)) /* RXE */
1847 s->status[1] |= 1 << 0; /* RSY */
1848 else
1849 s->status[1] &= ~(1 << 0); /* RSY */
1850
1851 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1852 (s->status[0] & (1 << 4)); /* RFS */
1853 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1854 (s->status[0] & (1 << 3)); /* TFS */
1855 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1856 (s->status[0] & (1 << 6)); /* EOC */
1857 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1858 (s->status[0] & (1 << 1)); /* TUR */
1859 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1860
1861 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1862 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1863
1864 qemu_set_irq(s->irq, intr && s->enable);
1865 }
1866
1867 #define ICCR0 0x00 /* FICP Control register 0 */
1868 #define ICCR1 0x04 /* FICP Control register 1 */
1869 #define ICCR2 0x08 /* FICP Control register 2 */
1870 #define ICDR 0x0c /* FICP Data register */
1871 #define ICSR0 0x14 /* FICP Status register 0 */
1872 #define ICSR1 0x18 /* FICP Status register 1 */
1873 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1874
1875 static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1876 {
1877 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1878 uint8_t ret;
1879
1880 switch (addr) {
1881 case ICCR0:
1882 return s->control[0];
1883 case ICCR1:
1884 return s->control[1];
1885 case ICCR2:
1886 return s->control[2];
1887 case ICDR:
1888 s->status[0] &= ~0x01;
1889 s->status[1] &= ~0x72;
1890 if (s->rx_len) {
1891 s->rx_len --;
1892 ret = s->rx_fifo[s->rx_start ++];
1893 s->rx_start &= 63;
1894 pxa2xx_fir_update(s);
1895 return ret;
1896 }
1897 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1898 break;
1899 case ICSR0:
1900 return s->status[0];
1901 case ICSR1:
1902 return s->status[1] | (1 << 3); /* TNF */
1903 case ICFOR:
1904 return s->rx_len;
1905 default:
1906 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1907 break;
1908 }
1909 return 0;
1910 }
1911
1912 static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1913 uint32_t value)
1914 {
1915 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1916 uint8_t ch;
1917
1918 switch (addr) {
1919 case ICCR0:
1920 s->control[0] = value;
1921 if (!(value & (1 << 4))) /* RXE */
1922 s->rx_len = s->rx_start = 0;
1923 if (!(value & (1 << 3))) { /* TXE */
1924 /* Nop */
1925 }
1926 s->enable = value & 1; /* ITR */
1927 if (!s->enable)
1928 s->status[0] = 0;
1929 pxa2xx_fir_update(s);
1930 break;
1931 case ICCR1:
1932 s->control[1] = value;
1933 break;
1934 case ICCR2:
1935 s->control[2] = value & 0x3f;
1936 pxa2xx_fir_update(s);
1937 break;
1938 case ICDR:
1939 if (s->control[2] & (1 << 2)) /* TXP */
1940 ch = value;
1941 else
1942 ch = ~value;
1943 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1944 qemu_chr_write(s->chr, &ch, 1);
1945 break;
1946 case ICSR0:
1947 s->status[0] &= ~(value & 0x66);
1948 pxa2xx_fir_update(s);
1949 break;
1950 case ICFOR:
1951 break;
1952 default:
1953 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1954 }
1955 }
1956
1957 static CPUReadMemoryFunc * const pxa2xx_fir_readfn[] = {
1958 pxa2xx_fir_read,
1959 pxa2xx_fir_read,
1960 pxa2xx_fir_read,
1961 };
1962
1963 static CPUWriteMemoryFunc * const pxa2xx_fir_writefn[] = {
1964 pxa2xx_fir_write,
1965 pxa2xx_fir_write,
1966 pxa2xx_fir_write,
1967 };
1968
1969 static int pxa2xx_fir_is_empty(void *opaque)
1970 {
1971 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1972 return (s->rx_len < 64);
1973 }
1974
1975 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1976 {
1977 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1978 if (!(s->control[0] & (1 << 4))) /* RXE */
1979 return;
1980
1981 while (size --) {
1982 s->status[1] |= 1 << 4; /* EOF */
1983 if (s->rx_len >= 64) {
1984 s->status[1] |= 1 << 6; /* ROR */
1985 break;
1986 }
1987
1988 if (s->control[2] & (1 << 3)) /* RXP */
1989 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1990 else
1991 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1992 }
1993
1994 pxa2xx_fir_update(s);
1995 }
1996
1997 static void pxa2xx_fir_event(void *opaque, int event)
1998 {
1999 }
2000
2001 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
2002 {
2003 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
2004 int i;
2005
2006 qemu_put_be32(f, s->enable);
2007
2008 qemu_put_8s(f, &s->control[0]);
2009 qemu_put_8s(f, &s->control[1]);
2010 qemu_put_8s(f, &s->control[2]);
2011 qemu_put_8s(f, &s->status[0]);
2012 qemu_put_8s(f, &s->status[1]);
2013
2014 qemu_put_byte(f, s->rx_len);
2015 for (i = 0; i < s->rx_len; i ++)
2016 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
2017 }
2018
2019 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
2020 {
2021 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
2022 int i;
2023
2024 s->enable = qemu_get_be32(f);
2025
2026 qemu_get_8s(f, &s->control[0]);
2027 qemu_get_8s(f, &s->control[1]);
2028 qemu_get_8s(f, &s->control[2]);
2029 qemu_get_8s(f, &s->status[0]);
2030 qemu_get_8s(f, &s->status[1]);
2031
2032 s->rx_len = qemu_get_byte(f);
2033 s->rx_start = 0;
2034 for (i = 0; i < s->rx_len; i ++)
2035 s->rx_fifo[i] = qemu_get_byte(f);
2036
2037 return 0;
2038 }
2039
2040 static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
2041 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
2042 CharDriverState *chr)
2043 {
2044 int iomemtype;
2045 PXA2xxFIrState *s = (PXA2xxFIrState *)
2046 qemu_mallocz(sizeof(PXA2xxFIrState));
2047
2048 s->irq = irq;
2049 s->rx_dma = rx_dma;
2050 s->tx_dma = tx_dma;
2051 s->chr = chr;
2052
2053 pxa2xx_fir_reset(s);
2054
2055 iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn,
2056 pxa2xx_fir_writefn, s, DEVICE_NATIVE_ENDIAN);
2057 cpu_register_physical_memory(base, 0x1000, iomemtype);
2058
2059 if (chr)
2060 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2061 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2062
2063 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
2064 pxa2xx_fir_load, s);
2065
2066 return s;
2067 }
2068
2069 static void pxa2xx_reset(void *opaque, int line, int level)
2070 {
2071 PXA2xxState *s = (PXA2xxState *) opaque;
2072
2073 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2074 cpu_reset(s->env);
2075 /* TODO: reset peripherals */
2076 }
2077 }
2078
2079 /* Initialise a PXA270 integrated chip (ARM based core). */
2080 PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
2081 {
2082 PXA2xxState *s;
2083 int iomemtype, i;
2084 DriveInfo *dinfo;
2085 s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2086
2087 if (revision && strncmp(revision, "pxa27", 5)) {
2088 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2089 exit(1);
2090 }
2091 if (!revision)
2092 revision = "pxa270";
2093
2094 s->env = cpu_init(revision);
2095 if (!s->env) {
2096 fprintf(stderr, "Unable to find CPU definition\n");
2097 exit(1);
2098 }
2099 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2100
2101 /* SDRAM & Internal Memory Storage */
2102 cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
2103 sdram_size, qemu_ram_alloc(NULL, "pxa270.sdram",
2104 sdram_size) | IO_MEM_RAM);
2105 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
2106 0x40000, qemu_ram_alloc(NULL, "pxa270.internal",
2107 0x40000) | IO_MEM_RAM);
2108
2109 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2110
2111 s->dma = pxa27x_dma_init(0x40000000,
2112 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2113
2114 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2115 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2116 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2117 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2118 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2119 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2120 NULL);
2121
2122 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2123
2124 dinfo = drive_get(IF_SD, 0, 0);
2125 if (!dinfo) {
2126 fprintf(stderr, "qemu: missing SecureDigital device\n");
2127 exit(1);
2128 }
2129 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2130 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2131 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2132 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2133
2134 for (i = 0; pxa270_serial[i].io_base; i ++)
2135 if (serial_hds[i])
2136 #ifdef TARGET_WORDS_BIGENDIAN
2137 serial_mm_init(pxa270_serial[i].io_base, 2,
2138 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2139 14857000 / 16, serial_hds[i], 1, 1);
2140 #else
2141 serial_mm_init(pxa270_serial[i].io_base, 2,
2142 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2143 14857000 / 16, serial_hds[i], 1, 0);
2144 #endif
2145 else
2146 break;
2147 if (serial_hds[i])
2148 s->fir = pxa2xx_fir_init(0x40800000,
2149 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2150 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2151 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2152 serial_hds[i]);
2153
2154 s->lcd = pxa2xx_lcdc_init(0x44000000,
2155 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2156
2157 s->cm_base = 0x41300000;
2158 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2159 s->clkcfg = 0x00000009; /* Turbo mode active */
2160 iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2161 pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
2162 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2163 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2164
2165 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2166
2167 s->mm_base = 0x48000000;
2168 s->mm_regs[MDMRS >> 2] = 0x00020002;
2169 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2170 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2171 iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2172 pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
2173 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2174 register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2175
2176 s->pm_base = 0x40f00000;
2177 iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2178 pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
2179 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2180 register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2181
2182 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2183 s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
2184 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2185 DeviceState *dev;
2186 dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
2187 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2188 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2189 }
2190
2191 if (usb_enabled) {
2192 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2193 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2194 }
2195
2196 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2197 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2198
2199 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2200 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2201
2202 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2203 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2204 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2205 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2206
2207 s->i2s = pxa2xx_i2s_init(0x40400000,
2208 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2209 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2210 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2211
2212 s->kp = pxa27x_keypad_init(0x41500000,
2213 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2214
2215 /* GPIO1 resets the processor */
2216 /* The handler can be overridden by board-specific code */
2217 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2218 return s;
2219 }
2220
2221 /* Initialise a PXA255 integrated chip (ARM based core). */
2222 PXA2xxState *pxa255_init(unsigned int sdram_size)
2223 {
2224 PXA2xxState *s;
2225 int iomemtype, i;
2226 DriveInfo *dinfo;
2227
2228 s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2229
2230 s->env = cpu_init("pxa255");
2231 if (!s->env) {
2232 fprintf(stderr, "Unable to find CPU definition\n");
2233 exit(1);
2234 }
2235 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2236
2237 /* SDRAM & Internal Memory Storage */
2238 cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
2239 qemu_ram_alloc(NULL, "pxa255.sdram",
2240 sdram_size) | IO_MEM_RAM);
2241 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
2242 qemu_ram_alloc(NULL, "pxa255.internal",
2243 PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
2244
2245 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2246
2247 s->dma = pxa255_dma_init(0x40000000,
2248 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2249
2250 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2251 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2252 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2253 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2254 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2255 NULL);
2256
2257 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
2258
2259 dinfo = drive_get(IF_SD, 0, 0);
2260 if (!dinfo) {
2261 fprintf(stderr, "qemu: missing SecureDigital device\n");
2262 exit(1);
2263 }
2264 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2265 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2266 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2267 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2268
2269 for (i = 0; pxa255_serial[i].io_base; i ++)
2270 if (serial_hds[i]) {
2271 #ifdef TARGET_WORDS_BIGENDIAN
2272 serial_mm_init(pxa255_serial[i].io_base, 2,
2273 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2274 14745600 / 16, serial_hds[i], 1, 1);
2275 #else
2276 serial_mm_init(pxa255_serial[i].io_base, 2,
2277 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2278 14745600 / 16, serial_hds[i], 1, 0);
2279 #endif
2280 } else {
2281 break;
2282 }
2283 if (serial_hds[i])
2284 s->fir = pxa2xx_fir_init(0x40800000,
2285 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2286 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2287 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2288 serial_hds[i]);
2289
2290 s->lcd = pxa2xx_lcdc_init(0x44000000,
2291 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2292
2293 s->cm_base = 0x41300000;
2294 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2295 s->clkcfg = 0x00000009; /* Turbo mode active */
2296 iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2297 pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
2298 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2299 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2300
2301 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2302
2303 s->mm_base = 0x48000000;
2304 s->mm_regs[MDMRS >> 2] = 0x00020002;
2305 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2306 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2307 iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2308 pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
2309 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2310 register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2311
2312 s->pm_base = 0x40f00000;
2313 iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2314 pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
2315 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2316 register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2317
2318 for (i = 0; pxa255_ssp[i].io_base; i ++);
2319 s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
2320 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2321 DeviceState *dev;
2322 dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
2323 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2324 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2325 }
2326
2327 if (usb_enabled) {
2328 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2329 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2330 }
2331
2332 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2333 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2334
2335 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2336 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2337
2338 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2339 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2340 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2341 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2342
2343 s->i2s = pxa2xx_i2s_init(0x40400000,
2344 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2345 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2346 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2347
2348 /* GPIO1 resets the processor */
2349 /* The handler can be overridden by board-specific code */
2350 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2351 return s;
2352 }
2353
2354 static void pxa2xx_register_devices(void)
2355 {
2356 i2c_register_slave(&pxa2xx_i2c_slave_info);
2357 sysbus_register_dev("pxa2xx-ssp", sizeof(PXA2xxSSPState), pxa2xx_ssp_init);
2358 sysbus_register_withprop(&pxa2xx_i2c_info);
2359 sysbus_register_withprop(&pxa2xx_rtc_sysbus_info);
2360 }
2361
2362 device_init(pxa2xx_register_devices)
Qemu copy for testing