2 * Intel XScale PXA255/270 processor support.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licensed under the GPL.
16 #include "qemu-char.h"
18 #include "exec-memory.h"
21 target_phys_addr_t io_base
;
24 { 0x40100000, PXA2XX_PIC_FFUART
},
25 { 0x40200000, PXA2XX_PIC_BTUART
},
26 { 0x40700000, PXA2XX_PIC_STUART
},
27 { 0x41600000, PXA25X_PIC_HWUART
},
29 }, pxa270_serial
[] = {
30 { 0x40100000, PXA2XX_PIC_FFUART
},
31 { 0x40200000, PXA2XX_PIC_BTUART
},
32 { 0x40700000, PXA2XX_PIC_STUART
},
36 typedef struct PXASSPDef
{
37 target_phys_addr_t io_base
;
42 static PXASSPDef pxa250_ssp
[] = {
43 { 0x41000000, PXA2XX_PIC_SSP
},
48 static PXASSPDef pxa255_ssp
[] = {
49 { 0x41000000, PXA2XX_PIC_SSP
},
50 { 0x41400000, PXA25X_PIC_NSSP
},
55 static PXASSPDef pxa26x_ssp
[] = {
56 { 0x41000000, PXA2XX_PIC_SSP
},
57 { 0x41400000, PXA25X_PIC_NSSP
},
58 { 0x41500000, PXA26X_PIC_ASSP
},
63 static PXASSPDef pxa27x_ssp
[] = {
64 { 0x41000000, PXA2XX_PIC_SSP
},
65 { 0x41700000, PXA27X_PIC_SSP2
},
66 { 0x41900000, PXA2XX_PIC_SSP3
},
70 #define PMCR 0x00 /* Power Manager Control register */
71 #define PSSR 0x04 /* Power Manager Sleep Status register */
72 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
73 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
74 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
75 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
76 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
77 #define PCFR 0x1c /* Power Manager General Configuration register */
78 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
79 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
80 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
81 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
82 #define RCSR 0x30 /* Reset Controller Status register */
83 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
84 #define PTSR 0x38 /* Power Manager Standby Configuration register */
85 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
86 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
87 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
88 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
89 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
90 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
92 static uint32_t pxa2xx_pm_read(void *opaque
, target_phys_addr_t addr
)
94 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
101 return s
->pm_regs
[addr
>> 2];
104 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
110 static void pxa2xx_pm_write(void *opaque
, target_phys_addr_t addr
,
113 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
117 s
->pm_regs
[addr
>> 2] &= 0x15 & ~(value
& 0x2a);
118 s
->pm_regs
[addr
>> 2] |= value
& 0x15;
121 case PSSR
: /* Read-clean registers */
124 s
->pm_regs
[addr
>> 2] &= ~value
;
127 default: /* Read-write registers */
129 s
->pm_regs
[addr
>> 2] = value
;
133 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
138 static CPUReadMemoryFunc
* const pxa2xx_pm_readfn
[] = {
144 static CPUWriteMemoryFunc
* const pxa2xx_pm_writefn
[] = {
150 static const VMStateDescription vmstate_pxa2xx_pm
= {
153 .minimum_version_id
= 0,
154 .minimum_version_id_old
= 0,
155 .fields
= (VMStateField
[]) {
156 VMSTATE_UINT32_ARRAY(pm_regs
, PXA2xxState
, 0x40),
157 VMSTATE_END_OF_LIST()
161 #define CCCR 0x00 /* Core Clock Configuration register */
162 #define CKEN 0x04 /* Clock Enable register */
163 #define OSCC 0x08 /* Oscillator Configuration register */
164 #define CCSR 0x0c /* Core Clock Status register */
166 static uint32_t pxa2xx_cm_read(void *opaque
, target_phys_addr_t addr
)
168 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
174 return s
->cm_regs
[addr
>> 2];
177 return s
->cm_regs
[CCCR
>> 2] | (3 << 28);
180 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
186 static void pxa2xx_cm_write(void *opaque
, target_phys_addr_t addr
,
189 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
194 s
->cm_regs
[addr
>> 2] = value
;
198 s
->cm_regs
[addr
>> 2] &= ~0x6c;
199 s
->cm_regs
[addr
>> 2] |= value
& 0x6e;
200 if ((value
>> 1) & 1) /* OON */
201 s
->cm_regs
[addr
>> 2] |= 1 << 0; /* Oscillator is now stable */
205 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
210 static CPUReadMemoryFunc
* const pxa2xx_cm_readfn
[] = {
216 static CPUWriteMemoryFunc
* const pxa2xx_cm_writefn
[] = {
222 static const VMStateDescription vmstate_pxa2xx_cm
= {
225 .minimum_version_id
= 0,
226 .minimum_version_id_old
= 0,
227 .fields
= (VMStateField
[]) {
228 VMSTATE_UINT32_ARRAY(cm_regs
, PXA2xxState
, 4),
229 VMSTATE_UINT32(clkcfg
, PXA2xxState
),
230 VMSTATE_UINT32(pmnc
, PXA2xxState
),
231 VMSTATE_END_OF_LIST()
235 static uint32_t pxa2xx_clkpwr_read(void *opaque
, int op2
, int reg
, int crm
)
237 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
240 case 6: /* Clock Configuration register */
243 case 7: /* Power Mode register */
247 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
253 static void pxa2xx_clkpwr_write(void *opaque
, int op2
, int reg
, int crm
,
256 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
257 static const char *pwrmode
[8] = {
258 "Normal", "Idle", "Deep-idle", "Standby",
259 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
263 case 6: /* Clock Configuration register */
264 s
->clkcfg
= value
& 0xf;
266 printf("%s: CPU frequency change attempt\n", __FUNCTION__
);
269 case 7: /* Power Mode register */
271 printf("%s: CPU voltage change attempt\n", __FUNCTION__
);
279 if (!(s
->cm_regs
[CCCR
>> 2] & (1 << 31))) { /* CPDIS */
280 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
287 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
288 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
292 s
->env
->uncached_cpsr
=
293 ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
294 s
->env
->cp15
.c1_sys
= 0;
295 s
->env
->cp15
.c1_coproc
= 0;
296 s
->env
->cp15
.c2_base0
= 0;
298 s
->pm_regs
[PSSR
>> 2] |= 0x8; /* Set STS */
299 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
302 * The scratch-pad register is almost universally used
303 * for storing the return address on suspend. For the
304 * lack of a resuming bootloader, perform a jump
305 * directly to that address.
307 memset(s
->env
->regs
, 0, 4 * 15);
308 s
->env
->regs
[15] = s
->pm_regs
[PSPR
>> 2];
311 buffer
= 0xe59ff000; /* ldr pc, [pc, #0] */
312 cpu_physical_memory_write(0, &buffer
, 4);
313 buffer
= s
->pm_regs
[PSPR
>> 2];
314 cpu_physical_memory_write(8, &buffer
, 4);
318 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HALT
);
324 printf("%s: machine entered %s mode\n", __FUNCTION__
,
330 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
335 /* Performace Monitoring Registers */
336 #define CPPMNC 0 /* Performance Monitor Control register */
337 #define CPCCNT 1 /* Clock Counter register */
338 #define CPINTEN 4 /* Interrupt Enable register */
339 #define CPFLAG 5 /* Overflow Flag register */
340 #define CPEVTSEL 8 /* Event Selection register */
342 #define CPPMN0 0 /* Performance Count register 0 */
343 #define CPPMN1 1 /* Performance Count register 1 */
344 #define CPPMN2 2 /* Performance Count register 2 */
345 #define CPPMN3 3 /* Performance Count register 3 */
347 static uint32_t pxa2xx_perf_read(void *opaque
, int op2
, int reg
, int crm
)
349 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
356 return qemu_get_clock_ns(vm_clock
);
365 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
371 static void pxa2xx_perf_write(void *opaque
, int op2
, int reg
, int crm
,
374 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
388 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
393 static uint32_t pxa2xx_cp14_read(void *opaque
, int op2
, int reg
, int crm
)
397 return pxa2xx_clkpwr_read(opaque
, op2
, reg
, crm
);
399 return pxa2xx_perf_read(opaque
, op2
, reg
, crm
);
410 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
416 static void pxa2xx_cp14_write(void *opaque
, int op2
, int reg
, int crm
,
421 pxa2xx_clkpwr_write(opaque
, op2
, reg
, crm
, value
);
424 pxa2xx_perf_write(opaque
, op2
, reg
, crm
, value
);
436 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
441 #define MDCNFG 0x00 /* SDRAM Configuration register */
442 #define MDREFR 0x04 /* SDRAM Refresh Control register */
443 #define MSC0 0x08 /* Static Memory Control register 0 */
444 #define MSC1 0x0c /* Static Memory Control register 1 */
445 #define MSC2 0x10 /* Static Memory Control register 2 */
446 #define MECR 0x14 /* Expansion Memory Bus Config register */
447 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
448 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
449 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
450 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
451 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
452 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
453 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
454 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
455 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
456 #define ARB_CNTL 0x48 /* Arbiter Control register */
457 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
458 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
459 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
460 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
461 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
462 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
463 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
465 static uint32_t pxa2xx_mm_read(void *opaque
, target_phys_addr_t addr
)
467 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
470 case MDCNFG
... SA1110
:
472 return s
->mm_regs
[addr
>> 2];
475 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
481 static void pxa2xx_mm_write(void *opaque
, target_phys_addr_t addr
,
484 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
487 case MDCNFG
... SA1110
:
488 if ((addr
& 3) == 0) {
489 s
->mm_regs
[addr
>> 2] = value
;
494 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
499 static CPUReadMemoryFunc
* const pxa2xx_mm_readfn
[] = {
505 static CPUWriteMemoryFunc
* const pxa2xx_mm_writefn
[] = {
511 static const VMStateDescription vmstate_pxa2xx_mm
= {
514 .minimum_version_id
= 0,
515 .minimum_version_id_old
= 0,
516 .fields
= (VMStateField
[]) {
517 VMSTATE_UINT32_ARRAY(mm_regs
, PXA2xxState
, 0x1a),
518 VMSTATE_END_OF_LIST()
522 /* Synchronous Serial Ports */
538 uint32_t rx_fifo
[16];
543 #define SSCR0 0x00 /* SSP Control register 0 */
544 #define SSCR1 0x04 /* SSP Control register 1 */
545 #define SSSR 0x08 /* SSP Status register */
546 #define SSITR 0x0c /* SSP Interrupt Test register */
547 #define SSDR 0x10 /* SSP Data register */
548 #define SSTO 0x28 /* SSP Time-Out register */
549 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
550 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
551 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
552 #define SSTSS 0x38 /* SSP Time Slot Status register */
553 #define SSACD 0x3c /* SSP Audio Clock Divider register */
555 /* Bitfields for above registers */
556 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
557 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
558 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
559 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
560 #define SSCR0_SSE (1 << 7)
561 #define SSCR0_RIM (1 << 22)
562 #define SSCR0_TIM (1 << 23)
563 #define SSCR0_MOD (1 << 31)
564 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
565 #define SSCR1_RIE (1 << 0)
566 #define SSCR1_TIE (1 << 1)
567 #define SSCR1_LBM (1 << 2)
568 #define SSCR1_MWDS (1 << 5)
569 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
570 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
571 #define SSCR1_EFWR (1 << 14)
572 #define SSCR1_PINTE (1 << 18)
573 #define SSCR1_TINTE (1 << 19)
574 #define SSCR1_RSRE (1 << 20)
575 #define SSCR1_TSRE (1 << 21)
576 #define SSCR1_EBCEI (1 << 29)
577 #define SSITR_INT (7 << 5)
578 #define SSSR_TNF (1 << 2)
579 #define SSSR_RNE (1 << 3)
580 #define SSSR_TFS (1 << 5)
581 #define SSSR_RFS (1 << 6)
582 #define SSSR_ROR (1 << 7)
583 #define SSSR_PINT (1 << 18)
584 #define SSSR_TINT (1 << 19)
585 #define SSSR_EOC (1 << 20)
586 #define SSSR_TUR (1 << 21)
587 #define SSSR_BCE (1 << 23)
588 #define SSSR_RW 0x00bc0080
590 static void pxa2xx_ssp_int_update(PXA2xxSSPState
*s
)
594 level
|= s
->ssitr
& SSITR_INT
;
595 level
|= (s
->sssr
& SSSR_BCE
) && (s
->sscr
[1] & SSCR1_EBCEI
);
596 level
|= (s
->sssr
& SSSR_TUR
) && !(s
->sscr
[0] & SSCR0_TIM
);
597 level
|= (s
->sssr
& SSSR_EOC
) && (s
->sssr
& (SSSR_TINT
| SSSR_PINT
));
598 level
|= (s
->sssr
& SSSR_TINT
) && (s
->sscr
[1] & SSCR1_TINTE
);
599 level
|= (s
->sssr
& SSSR_PINT
) && (s
->sscr
[1] & SSCR1_PINTE
);
600 level
|= (s
->sssr
& SSSR_ROR
) && !(s
->sscr
[0] & SSCR0_RIM
);
601 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
602 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
603 qemu_set_irq(s
->irq
, !!level
);
606 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState
*s
)
608 s
->sssr
&= ~(0xf << 12); /* Clear RFL */
609 s
->sssr
&= ~(0xf << 8); /* Clear TFL */
610 s
->sssr
&= ~SSSR_TFS
;
611 s
->sssr
&= ~SSSR_TNF
;
613 s
->sssr
|= ((s
->rx_level
- 1) & 0xf) << 12;
614 if (s
->rx_level
>= SSCR1_RFT(s
->sscr
[1]))
617 s
->sssr
&= ~SSSR_RFS
;
621 s
->sssr
&= ~SSSR_RNE
;
622 /* TX FIFO is never filled, so it is always in underrun
623 condition if SSP is enabled */
628 pxa2xx_ssp_int_update(s
);
631 static uint32_t pxa2xx_ssp_read(void *opaque
, target_phys_addr_t addr
)
633 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
648 return s
->sssr
| s
->ssitr
;
652 if (s
->rx_level
< 1) {
653 printf("%s: SSP Rx Underrun\n", __FUNCTION__
);
657 retval
= s
->rx_fifo
[s
->rx_start
++];
659 pxa2xx_ssp_fifo_update(s
);
670 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
676 static void pxa2xx_ssp_write(void *opaque
, target_phys_addr_t addr
,
679 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
683 s
->sscr
[0] = value
& 0xc7ffffff;
684 s
->enable
= value
& SSCR0_SSE
;
685 if (value
& SSCR0_MOD
)
686 printf("%s: Attempt to use network mode\n", __FUNCTION__
);
687 if (s
->enable
&& SSCR0_DSS(value
) < 4)
688 printf("%s: Wrong data size: %i bits\n", __FUNCTION__
,
690 if (!(value
& SSCR0_SSE
)) {
695 pxa2xx_ssp_fifo_update(s
);
700 if (value
& (SSCR1_LBM
| SSCR1_EFWR
))
701 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__
);
702 pxa2xx_ssp_fifo_update(s
);
714 s
->ssitr
= value
& SSITR_INT
;
715 pxa2xx_ssp_int_update(s
);
719 s
->sssr
&= ~(value
& SSSR_RW
);
720 pxa2xx_ssp_int_update(s
);
724 if (SSCR0_UWIRE(s
->sscr
[0])) {
725 if (s
->sscr
[1] & SSCR1_MWDS
)
730 /* Note how 32bits overflow does no harm here */
731 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
733 /* Data goes from here to the Tx FIFO and is shifted out from
734 * there directly to the slave, no need to buffer it.
738 readval
= ssi_transfer(s
->bus
, value
);
739 if (s
->rx_level
< 0x10) {
740 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0xf] = readval
;
745 pxa2xx_ssp_fifo_update(s
);
761 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
766 static CPUReadMemoryFunc
* const pxa2xx_ssp_readfn
[] = {
772 static CPUWriteMemoryFunc
* const pxa2xx_ssp_writefn
[] = {
778 static void pxa2xx_ssp_save(QEMUFile
*f
, void *opaque
)
780 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
783 qemu_put_be32(f
, s
->enable
);
785 qemu_put_be32s(f
, &s
->sscr
[0]);
786 qemu_put_be32s(f
, &s
->sscr
[1]);
787 qemu_put_be32s(f
, &s
->sspsp
);
788 qemu_put_be32s(f
, &s
->ssto
);
789 qemu_put_be32s(f
, &s
->ssitr
);
790 qemu_put_be32s(f
, &s
->sssr
);
791 qemu_put_8s(f
, &s
->sstsa
);
792 qemu_put_8s(f
, &s
->ssrsa
);
793 qemu_put_8s(f
, &s
->ssacd
);
795 qemu_put_byte(f
, s
->rx_level
);
796 for (i
= 0; i
< s
->rx_level
; i
++)
797 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 0xf]);
800 static int pxa2xx_ssp_load(QEMUFile
*f
, void *opaque
, int version_id
)
802 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
805 s
->enable
= qemu_get_be32(f
);
807 qemu_get_be32s(f
, &s
->sscr
[0]);
808 qemu_get_be32s(f
, &s
->sscr
[1]);
809 qemu_get_be32s(f
, &s
->sspsp
);
810 qemu_get_be32s(f
, &s
->ssto
);
811 qemu_get_be32s(f
, &s
->ssitr
);
812 qemu_get_be32s(f
, &s
->sssr
);
813 qemu_get_8s(f
, &s
->sstsa
);
814 qemu_get_8s(f
, &s
->ssrsa
);
815 qemu_get_8s(f
, &s
->ssacd
);
817 s
->rx_level
= qemu_get_byte(f
);
819 for (i
= 0; i
< s
->rx_level
; i
++)
820 s
->rx_fifo
[i
] = qemu_get_byte(f
);
825 static int pxa2xx_ssp_init(SysBusDevice
*dev
)
828 PXA2xxSSPState
*s
= FROM_SYSBUS(PXA2xxSSPState
, dev
);
830 sysbus_init_irq(dev
, &s
->irq
);
832 iomemtype
= cpu_register_io_memory(pxa2xx_ssp_readfn
,
833 pxa2xx_ssp_writefn
, s
,
834 DEVICE_NATIVE_ENDIAN
);
835 sysbus_init_mmio(dev
, 0x1000, iomemtype
);
836 register_savevm(&dev
->qdev
, "pxa2xx_ssp", -1, 0,
837 pxa2xx_ssp_save
, pxa2xx_ssp_load
, s
);
839 s
->bus
= ssi_create_bus(&dev
->qdev
, "ssi");
843 /* Real-Time Clock */
844 #define RCNR 0x00 /* RTC Counter register */
845 #define RTAR 0x04 /* RTC Alarm register */
846 #define RTSR 0x08 /* RTC Status register */
847 #define RTTR 0x0c /* RTC Timer Trim register */
848 #define RDCR 0x10 /* RTC Day Counter register */
849 #define RYCR 0x14 /* RTC Year Counter register */
850 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
851 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
852 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
853 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
854 #define SWCR 0x28 /* RTC Stopwatch Counter register */
855 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
856 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
857 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
858 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
876 uint32_t last_rtcpicr
;
881 QEMUTimer
*rtc_rdal1
;
882 QEMUTimer
*rtc_rdal2
;
883 QEMUTimer
*rtc_swal1
;
884 QEMUTimer
*rtc_swal2
;
889 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState
*s
)
891 qemu_set_irq(s
->rtc_irq
, !!(s
->rtsr
& 0x2553));
894 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState
*s
)
896 int64_t rt
= qemu_get_clock_ms(rt_clock
);
897 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
898 (1000 * ((s
->rttr
& 0xffff) + 1));
899 s
->last_rdcr
+= ((rt
- s
->last_hz
) << 15) /
900 (1000 * ((s
->rttr
& 0xffff) + 1));
904 static void pxa2xx_rtc_swupdate(PXA2xxRTCState
*s
)
906 int64_t rt
= qemu_get_clock_ms(rt_clock
);
907 if (s
->rtsr
& (1 << 12))
908 s
->last_swcr
+= (rt
- s
->last_sw
) / 10;
912 static void pxa2xx_rtc_piupdate(PXA2xxRTCState
*s
)
914 int64_t rt
= qemu_get_clock_ms(rt_clock
);
915 if (s
->rtsr
& (1 << 15))
916 s
->last_swcr
+= rt
- s
->last_pi
;
920 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState
*s
,
923 if ((rtsr
& (1 << 2)) && !(rtsr
& (1 << 0)))
924 qemu_mod_timer(s
->rtc_hz
, s
->last_hz
+
925 (((s
->rtar
- s
->last_rcnr
) * 1000 *
926 ((s
->rttr
& 0xffff) + 1)) >> 15));
928 qemu_del_timer(s
->rtc_hz
);
930 if ((rtsr
& (1 << 5)) && !(rtsr
& (1 << 4)))
931 qemu_mod_timer(s
->rtc_rdal1
, s
->last_hz
+
932 (((s
->rdar1
- s
->last_rdcr
) * 1000 *
933 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
935 qemu_del_timer(s
->rtc_rdal1
);
937 if ((rtsr
& (1 << 7)) && !(rtsr
& (1 << 6)))
938 qemu_mod_timer(s
->rtc_rdal2
, s
->last_hz
+
939 (((s
->rdar2
- s
->last_rdcr
) * 1000 *
940 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
942 qemu_del_timer(s
->rtc_rdal2
);
944 if ((rtsr
& 0x1200) == 0x1200 && !(rtsr
& (1 << 8)))
945 qemu_mod_timer(s
->rtc_swal1
, s
->last_sw
+
946 (s
->swar1
- s
->last_swcr
) * 10); /* TODO: fixup */
948 qemu_del_timer(s
->rtc_swal1
);
950 if ((rtsr
& 0x1800) == 0x1800 && !(rtsr
& (1 << 10)))
951 qemu_mod_timer(s
->rtc_swal2
, s
->last_sw
+
952 (s
->swar2
- s
->last_swcr
) * 10); /* TODO: fixup */
954 qemu_del_timer(s
->rtc_swal2
);
956 if ((rtsr
& 0xc000) == 0xc000 && !(rtsr
& (1 << 13)))
957 qemu_mod_timer(s
->rtc_pi
, s
->last_pi
+
958 (s
->piar
& 0xffff) - s
->last_rtcpicr
);
960 qemu_del_timer(s
->rtc_pi
);
963 static inline void pxa2xx_rtc_hz_tick(void *opaque
)
965 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
967 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
968 pxa2xx_rtc_int_update(s
);
971 static inline void pxa2xx_rtc_rdal1_tick(void *opaque
)
973 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
975 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
976 pxa2xx_rtc_int_update(s
);
979 static inline void pxa2xx_rtc_rdal2_tick(void *opaque
)
981 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
983 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
984 pxa2xx_rtc_int_update(s
);
987 static inline void pxa2xx_rtc_swal1_tick(void *opaque
)
989 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
991 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
992 pxa2xx_rtc_int_update(s
);
995 static inline void pxa2xx_rtc_swal2_tick(void *opaque
)
997 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
998 s
->rtsr
|= (1 << 10);
999 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1000 pxa2xx_rtc_int_update(s
);
1003 static inline void pxa2xx_rtc_pi_tick(void *opaque
)
1005 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1006 s
->rtsr
|= (1 << 13);
1007 pxa2xx_rtc_piupdate(s
);
1008 s
->last_rtcpicr
= 0;
1009 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1010 pxa2xx_rtc_int_update(s
);
1013 static uint32_t pxa2xx_rtc_read(void *opaque
, target_phys_addr_t addr
)
1015 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1039 return s
->last_rcnr
+ ((qemu_get_clock_ms(rt_clock
) - s
->last_hz
) << 15) /
1040 (1000 * ((s
->rttr
& 0xffff) + 1));
1042 return s
->last_rdcr
+ ((qemu_get_clock_ms(rt_clock
) - s
->last_hz
) << 15) /
1043 (1000 * ((s
->rttr
& 0xffff) + 1));
1045 return s
->last_rycr
;
1047 if (s
->rtsr
& (1 << 12))
1048 return s
->last_swcr
+ (qemu_get_clock_ms(rt_clock
) - s
->last_sw
) / 10;
1050 return s
->last_swcr
;
1052 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1058 static void pxa2xx_rtc_write(void *opaque
, target_phys_addr_t addr
,
1061 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1065 if (!(s
->rttr
& (1 << 31))) {
1066 pxa2xx_rtc_hzupdate(s
);
1068 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1073 if ((s
->rtsr
^ value
) & (1 << 15))
1074 pxa2xx_rtc_piupdate(s
);
1076 if ((s
->rtsr
^ value
) & (1 << 12))
1077 pxa2xx_rtc_swupdate(s
);
1079 if (((s
->rtsr
^ value
) & 0x4aac) | (value
& ~0xdaac))
1080 pxa2xx_rtc_alarm_update(s
, value
);
1082 s
->rtsr
= (value
& 0xdaac) | (s
->rtsr
& ~(value
& ~0xdaac));
1083 pxa2xx_rtc_int_update(s
);
1088 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1093 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1098 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1103 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1108 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1112 pxa2xx_rtc_swupdate(s
);
1115 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1120 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1125 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1129 pxa2xx_rtc_hzupdate(s
);
1130 s
->last_rcnr
= value
;
1131 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1135 pxa2xx_rtc_hzupdate(s
);
1136 s
->last_rdcr
= value
;
1137 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1141 s
->last_rycr
= value
;
1145 pxa2xx_rtc_swupdate(s
);
1146 s
->last_swcr
= value
;
1147 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1151 pxa2xx_rtc_piupdate(s
);
1152 s
->last_rtcpicr
= value
& 0xffff;
1153 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1157 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1161 static CPUReadMemoryFunc
* const pxa2xx_rtc_readfn
[] = {
1167 static CPUWriteMemoryFunc
* const pxa2xx_rtc_writefn
[] = {
1173 static int pxa2xx_rtc_init(SysBusDevice
*dev
)
1175 PXA2xxRTCState
*s
= FROM_SYSBUS(PXA2xxRTCState
, dev
);
1183 qemu_get_timedate(&tm
, 0);
1184 wom
= ((tm
.tm_mday
- 1) / 7) + 1;
1186 s
->last_rcnr
= (uint32_t) mktimegm(&tm
);
1187 s
->last_rdcr
= (wom
<< 20) | ((tm
.tm_wday
+ 1) << 17) |
1188 (tm
.tm_hour
<< 12) | (tm
.tm_min
<< 6) | tm
.tm_sec
;
1189 s
->last_rycr
= ((tm
.tm_year
+ 1900) << 9) |
1190 ((tm
.tm_mon
+ 1) << 5) | tm
.tm_mday
;
1191 s
->last_swcr
= (tm
.tm_hour
<< 19) |
1192 (tm
.tm_min
<< 13) | (tm
.tm_sec
<< 7);
1193 s
->last_rtcpicr
= 0;
1194 s
->last_hz
= s
->last_sw
= s
->last_pi
= qemu_get_clock_ms(rt_clock
);
1196 s
->rtc_hz
= qemu_new_timer_ms(rt_clock
, pxa2xx_rtc_hz_tick
, s
);
1197 s
->rtc_rdal1
= qemu_new_timer_ms(rt_clock
, pxa2xx_rtc_rdal1_tick
, s
);
1198 s
->rtc_rdal2
= qemu_new_timer_ms(rt_clock
, pxa2xx_rtc_rdal2_tick
, s
);
1199 s
->rtc_swal1
= qemu_new_timer_ms(rt_clock
, pxa2xx_rtc_swal1_tick
, s
);
1200 s
->rtc_swal2
= qemu_new_timer_ms(rt_clock
, pxa2xx_rtc_swal2_tick
, s
);
1201 s
->rtc_pi
= qemu_new_timer_ms(rt_clock
, pxa2xx_rtc_pi_tick
, s
);
1203 sysbus_init_irq(dev
, &s
->rtc_irq
);
1205 iomemtype
= cpu_register_io_memory(pxa2xx_rtc_readfn
,
1206 pxa2xx_rtc_writefn
, s
, DEVICE_NATIVE_ENDIAN
);
1207 sysbus_init_mmio(dev
, 0x10000, iomemtype
);
1212 static void pxa2xx_rtc_pre_save(void *opaque
)
1214 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1216 pxa2xx_rtc_hzupdate(s
);
1217 pxa2xx_rtc_piupdate(s
);
1218 pxa2xx_rtc_swupdate(s
);
1221 static int pxa2xx_rtc_post_load(void *opaque
, int version_id
)
1223 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1225 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1230 static const VMStateDescription vmstate_pxa2xx_rtc_regs
= {
1231 .name
= "pxa2xx_rtc",
1233 .minimum_version_id
= 0,
1234 .minimum_version_id_old
= 0,
1235 .pre_save
= pxa2xx_rtc_pre_save
,
1236 .post_load
= pxa2xx_rtc_post_load
,
1237 .fields
= (VMStateField
[]) {
1238 VMSTATE_UINT32(rttr
, PXA2xxRTCState
),
1239 VMSTATE_UINT32(rtsr
, PXA2xxRTCState
),
1240 VMSTATE_UINT32(rtar
, PXA2xxRTCState
),
1241 VMSTATE_UINT32(rdar1
, PXA2xxRTCState
),
1242 VMSTATE_UINT32(rdar2
, PXA2xxRTCState
),
1243 VMSTATE_UINT32(ryar1
, PXA2xxRTCState
),
1244 VMSTATE_UINT32(ryar2
, PXA2xxRTCState
),
1245 VMSTATE_UINT32(swar1
, PXA2xxRTCState
),
1246 VMSTATE_UINT32(swar2
, PXA2xxRTCState
),
1247 VMSTATE_UINT32(piar
, PXA2xxRTCState
),
1248 VMSTATE_UINT32(last_rcnr
, PXA2xxRTCState
),
1249 VMSTATE_UINT32(last_rdcr
, PXA2xxRTCState
),
1250 VMSTATE_UINT32(last_rycr
, PXA2xxRTCState
),
1251 VMSTATE_UINT32(last_swcr
, PXA2xxRTCState
),
1252 VMSTATE_UINT32(last_rtcpicr
, PXA2xxRTCState
),
1253 VMSTATE_INT64(last_hz
, PXA2xxRTCState
),
1254 VMSTATE_INT64(last_sw
, PXA2xxRTCState
),
1255 VMSTATE_INT64(last_pi
, PXA2xxRTCState
),
1256 VMSTATE_END_OF_LIST(),
1260 static SysBusDeviceInfo pxa2xx_rtc_sysbus_info
= {
1261 .init
= pxa2xx_rtc_init
,
1262 .qdev
.name
= "pxa2xx_rtc",
1263 .qdev
.desc
= "PXA2xx RTC Controller",
1264 .qdev
.size
= sizeof(PXA2xxRTCState
),
1265 .qdev
.vmsd
= &vmstate_pxa2xx_rtc_regs
,
1271 PXA2xxI2CState
*host
;
1272 } PXA2xxI2CSlaveState
;
1274 struct PXA2xxI2CState
{
1275 SysBusDevice busdev
;
1276 PXA2xxI2CSlaveState
*slave
;
1280 uint32_t region_size
;
1288 #define IBMR 0x80 /* I2C Bus Monitor register */
1289 #define IDBR 0x88 /* I2C Data Buffer register */
1290 #define ICR 0x90 /* I2C Control register */
1291 #define ISR 0x98 /* I2C Status register */
1292 #define ISAR 0xa0 /* I2C Slave Address register */
1294 static void pxa2xx_i2c_update(PXA2xxI2CState
*s
)
1297 level
|= s
->status
& s
->control
& (1 << 10); /* BED */
1298 level
|= (s
->status
& (1 << 7)) && (s
->control
& (1 << 9)); /* IRF */
1299 level
|= (s
->status
& (1 << 6)) && (s
->control
& (1 << 8)); /* ITE */
1300 level
|= s
->status
& (1 << 9); /* SAD */
1301 qemu_set_irq(s
->irq
, !!level
);
1304 /* These are only stubs now. */
1305 static void pxa2xx_i2c_event(i2c_slave
*i2c
, enum i2c_event event
)
1307 PXA2xxI2CSlaveState
*slave
= FROM_I2C_SLAVE(PXA2xxI2CSlaveState
, i2c
);
1308 PXA2xxI2CState
*s
= slave
->host
;
1311 case I2C_START_SEND
:
1312 s
->status
|= (1 << 9); /* set SAD */
1313 s
->status
&= ~(1 << 0); /* clear RWM */
1315 case I2C_START_RECV
:
1316 s
->status
|= (1 << 9); /* set SAD */
1317 s
->status
|= 1 << 0; /* set RWM */
1320 s
->status
|= (1 << 4); /* set SSD */
1323 s
->status
|= 1 << 1; /* set ACKNAK */
1326 pxa2xx_i2c_update(s
);
1329 static int pxa2xx_i2c_rx(i2c_slave
*i2c
)
1331 PXA2xxI2CSlaveState
*slave
= FROM_I2C_SLAVE(PXA2xxI2CSlaveState
, i2c
);
1332 PXA2xxI2CState
*s
= slave
->host
;
1333 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6)))
1336 if (s
->status
& (1 << 0)) { /* RWM */
1337 s
->status
|= 1 << 6; /* set ITE */
1339 pxa2xx_i2c_update(s
);
1344 static int pxa2xx_i2c_tx(i2c_slave
*i2c
, uint8_t data
)
1346 PXA2xxI2CSlaveState
*slave
= FROM_I2C_SLAVE(PXA2xxI2CSlaveState
, i2c
);
1347 PXA2xxI2CState
*s
= slave
->host
;
1348 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6)))
1351 if (!(s
->status
& (1 << 0))) { /* RWM */
1352 s
->status
|= 1 << 7; /* set IRF */
1355 pxa2xx_i2c_update(s
);
1360 static uint32_t pxa2xx_i2c_read(void *opaque
, target_phys_addr_t addr
)
1362 PXA2xxI2CState
*s
= (PXA2xxI2CState
*) opaque
;
1369 return s
->status
| (i2c_bus_busy(s
->bus
) << 2);
1371 return s
->slave
->i2c
.address
;
1375 if (s
->status
& (1 << 2))
1376 s
->ibmr
^= 3; /* Fake SCL and SDA pin changes */
1381 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1387 static void pxa2xx_i2c_write(void *opaque
, target_phys_addr_t addr
,
1390 PXA2xxI2CState
*s
= (PXA2xxI2CState
*) opaque
;
1396 s
->control
= value
& 0xfff7;
1397 if ((value
& (1 << 3)) && (value
& (1 << 6))) { /* TB and IUE */
1398 /* TODO: slave mode */
1399 if (value
& (1 << 0)) { /* START condition */
1401 s
->status
|= 1 << 0; /* set RWM */
1403 s
->status
&= ~(1 << 0); /* clear RWM */
1404 ack
= !i2c_start_transfer(s
->bus
, s
->data
>> 1, s
->data
& 1);
1406 if (s
->status
& (1 << 0)) { /* RWM */
1407 s
->data
= i2c_recv(s
->bus
);
1408 if (value
& (1 << 2)) /* ACKNAK */
1412 ack
= !i2c_send(s
->bus
, s
->data
);
1415 if (value
& (1 << 1)) /* STOP condition */
1416 i2c_end_transfer(s
->bus
);
1419 if (value
& (1 << 0)) /* START condition */
1420 s
->status
|= 1 << 6; /* set ITE */
1422 if (s
->status
& (1 << 0)) /* RWM */
1423 s
->status
|= 1 << 7; /* set IRF */
1425 s
->status
|= 1 << 6; /* set ITE */
1426 s
->status
&= ~(1 << 1); /* clear ACKNAK */
1428 s
->status
|= 1 << 6; /* set ITE */
1429 s
->status
|= 1 << 10; /* set BED */
1430 s
->status
|= 1 << 1; /* set ACKNAK */
1433 if (!(value
& (1 << 3)) && (value
& (1 << 6))) /* !TB and IUE */
1434 if (value
& (1 << 4)) /* MA */
1435 i2c_end_transfer(s
->bus
);
1436 pxa2xx_i2c_update(s
);
1440 s
->status
&= ~(value
& 0x07f0);
1441 pxa2xx_i2c_update(s
);
1445 i2c_set_slave_address(&s
->slave
->i2c
, value
& 0x7f);
1449 s
->data
= value
& 0xff;
1453 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1457 static CPUReadMemoryFunc
* const pxa2xx_i2c_readfn
[] = {
1463 static CPUWriteMemoryFunc
* const pxa2xx_i2c_writefn
[] = {
1469 static const VMStateDescription vmstate_pxa2xx_i2c_slave
= {
1470 .name
= "pxa2xx_i2c_slave",
1472 .minimum_version_id
= 1,
1473 .minimum_version_id_old
= 1,
1474 .fields
= (VMStateField
[]) {
1475 VMSTATE_I2C_SLAVE(i2c
, PXA2xxI2CSlaveState
),
1476 VMSTATE_END_OF_LIST()
1480 static const VMStateDescription vmstate_pxa2xx_i2c
= {
1481 .name
= "pxa2xx_i2c",
1483 .minimum_version_id
= 1,
1484 .minimum_version_id_old
= 1,
1485 .fields
= (VMStateField
[]) {
1486 VMSTATE_UINT16(control
, PXA2xxI2CState
),
1487 VMSTATE_UINT16(status
, PXA2xxI2CState
),
1488 VMSTATE_UINT8(ibmr
, PXA2xxI2CState
),
1489 VMSTATE_UINT8(data
, PXA2xxI2CState
),
1490 VMSTATE_STRUCT_POINTER(slave
, PXA2xxI2CState
,
1491 vmstate_pxa2xx_i2c_slave
, PXA2xxI2CSlaveState
*),
1492 VMSTATE_END_OF_LIST()
1496 static int pxa2xx_i2c_slave_init(i2c_slave
*i2c
)
1498 /* Nothing to do. */
1502 static I2CSlaveInfo pxa2xx_i2c_slave_info
= {
1503 .qdev
.name
= "pxa2xx-i2c-slave",
1504 .qdev
.size
= sizeof(PXA2xxI2CSlaveState
),
1505 .init
= pxa2xx_i2c_slave_init
,
1506 .event
= pxa2xx_i2c_event
,
1507 .recv
= pxa2xx_i2c_rx
,
1508 .send
= pxa2xx_i2c_tx
1511 PXA2xxI2CState
*pxa2xx_i2c_init(target_phys_addr_t base
,
1512 qemu_irq irq
, uint32_t region_size
)
1515 SysBusDevice
*i2c_dev
;
1518 i2c_dev
= sysbus_from_qdev(qdev_create(NULL
, "pxa2xx_i2c"));
1519 qdev_prop_set_uint32(&i2c_dev
->qdev
, "size", region_size
+ 1);
1520 qdev_prop_set_uint32(&i2c_dev
->qdev
, "offset",
1521 base
- (base
& (~region_size
) & TARGET_PAGE_MASK
));
1523 qdev_init_nofail(&i2c_dev
->qdev
);
1525 sysbus_mmio_map(i2c_dev
, 0, base
& ~region_size
);
1526 sysbus_connect_irq(i2c_dev
, 0, irq
);
1528 s
= FROM_SYSBUS(PXA2xxI2CState
, i2c_dev
);
1529 /* FIXME: Should the slave device really be on a separate bus? */
1530 dev
= i2c_create_slave(i2c_init_bus(NULL
, "dummy"), "pxa2xx-i2c-slave", 0);
1531 s
->slave
= FROM_I2C_SLAVE(PXA2xxI2CSlaveState
, I2C_SLAVE_FROM_QDEV(dev
));
1537 static int pxa2xx_i2c_initfn(SysBusDevice
*dev
)
1539 PXA2xxI2CState
*s
= FROM_SYSBUS(PXA2xxI2CState
, dev
);
1542 s
->bus
= i2c_init_bus(&dev
->qdev
, "i2c");
1544 iomemtype
= cpu_register_io_memory(pxa2xx_i2c_readfn
,
1545 pxa2xx_i2c_writefn
, s
, DEVICE_NATIVE_ENDIAN
);
1546 sysbus_init_mmio(dev
, s
->region_size
, iomemtype
);
1547 sysbus_init_irq(dev
, &s
->irq
);
1552 i2c_bus
*pxa2xx_i2c_bus(PXA2xxI2CState
*s
)
1557 static SysBusDeviceInfo pxa2xx_i2c_info
= {
1558 .init
= pxa2xx_i2c_initfn
,
1559 .qdev
.name
= "pxa2xx_i2c",
1560 .qdev
.desc
= "PXA2xx I2C Bus Controller",
1561 .qdev
.size
= sizeof(PXA2xxI2CState
),
1562 .qdev
.vmsd
= &vmstate_pxa2xx_i2c
,
1563 .qdev
.props
= (Property
[]) {
1564 DEFINE_PROP_UINT32("size", PXA2xxI2CState
, region_size
, 0x10000),
1565 DEFINE_PROP_UINT32("offset", PXA2xxI2CState
, offset
, 0),
1566 DEFINE_PROP_END_OF_LIST(),
1570 /* PXA Inter-IC Sound Controller */
1571 static void pxa2xx_i2s_reset(PXA2xxI2SState
*i2s
)
1577 i2s
->control
[0] = 0x00;
1578 i2s
->control
[1] = 0x00;
1583 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1584 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1585 #define SACR_DREC(val) (val & (1 << 3))
1586 #define SACR_DPRL(val) (val & (1 << 4))
1588 static inline void pxa2xx_i2s_update(PXA2xxI2SState
*i2s
)
1591 rfs
= SACR_RFTH(i2s
->control
[0]) < i2s
->rx_len
&&
1592 !SACR_DREC(i2s
->control
[1]);
1593 tfs
= (i2s
->tx_len
|| i2s
->fifo_len
< SACR_TFTH(i2s
->control
[0])) &&
1594 i2s
->enable
&& !SACR_DPRL(i2s
->control
[1]);
1596 qemu_set_irq(i2s
->rx_dma
, rfs
);
1597 qemu_set_irq(i2s
->tx_dma
, tfs
);
1599 i2s
->status
&= 0xe0;
1600 if (i2s
->fifo_len
< 16 || !i2s
->enable
)
1601 i2s
->status
|= 1 << 0; /* TNF */
1603 i2s
->status
|= 1 << 1; /* RNE */
1605 i2s
->status
|= 1 << 2; /* BSY */
1607 i2s
->status
|= 1 << 3; /* TFS */
1609 i2s
->status
|= 1 << 4; /* RFS */
1610 if (!(i2s
->tx_len
&& i2s
->enable
))
1611 i2s
->status
|= i2s
->fifo_len
<< 8; /* TFL */
1612 i2s
->status
|= MAX(i2s
->rx_len
, 0xf) << 12; /* RFL */
1614 qemu_set_irq(i2s
->irq
, i2s
->status
& i2s
->mask
);
1617 #define SACR0 0x00 /* Serial Audio Global Control register */
1618 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1619 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1620 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1621 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1622 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1623 #define SADR 0x80 /* Serial Audio Data register */
1625 static uint32_t pxa2xx_i2s_read(void *opaque
, target_phys_addr_t addr
)
1627 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1631 return s
->control
[0];
1633 return s
->control
[1];
1643 if (s
->rx_len
> 0) {
1645 pxa2xx_i2s_update(s
);
1646 return s
->codec_in(s
->opaque
);
1650 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1656 static void pxa2xx_i2s_write(void *opaque
, target_phys_addr_t addr
,
1659 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1664 if (value
& (1 << 3)) /* RST */
1665 pxa2xx_i2s_reset(s
);
1666 s
->control
[0] = value
& 0xff3d;
1667 if (!s
->enable
&& (value
& 1) && s
->tx_len
) { /* ENB */
1668 for (sample
= s
->fifo
; s
->fifo_len
> 0; s
->fifo_len
--, sample
++)
1669 s
->codec_out(s
->opaque
, *sample
);
1670 s
->status
&= ~(1 << 7); /* I2SOFF */
1672 if (value
& (1 << 4)) /* EFWR */
1673 printf("%s: Attempt to use special function\n", __FUNCTION__
);
1674 s
->enable
= (value
& 9) == 1; /* ENB && !RST*/
1675 pxa2xx_i2s_update(s
);
1678 s
->control
[1] = value
& 0x0039;
1679 if (value
& (1 << 5)) /* ENLBF */
1680 printf("%s: Attempt to use loopback function\n", __FUNCTION__
);
1681 if (value
& (1 << 4)) /* DPRL */
1683 pxa2xx_i2s_update(s
);
1686 s
->mask
= value
& 0x0078;
1687 pxa2xx_i2s_update(s
);
1690 s
->status
&= ~(value
& (3 << 5));
1691 pxa2xx_i2s_update(s
);
1694 s
->clk
= value
& 0x007f;
1697 if (s
->tx_len
&& s
->enable
) {
1699 pxa2xx_i2s_update(s
);
1700 s
->codec_out(s
->opaque
, value
);
1701 } else if (s
->fifo_len
< 16) {
1702 s
->fifo
[s
->fifo_len
++] = value
;
1703 pxa2xx_i2s_update(s
);
1707 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1711 static CPUReadMemoryFunc
* const pxa2xx_i2s_readfn
[] = {
1717 static CPUWriteMemoryFunc
* const pxa2xx_i2s_writefn
[] = {
1723 static const VMStateDescription vmstate_pxa2xx_i2s
= {
1724 .name
= "pxa2xx_i2s",
1726 .minimum_version_id
= 0,
1727 .minimum_version_id_old
= 0,
1728 .fields
= (VMStateField
[]) {
1729 VMSTATE_UINT32_ARRAY(control
, PXA2xxI2SState
, 2),
1730 VMSTATE_UINT32(status
, PXA2xxI2SState
),
1731 VMSTATE_UINT32(mask
, PXA2xxI2SState
),
1732 VMSTATE_UINT32(clk
, PXA2xxI2SState
),
1733 VMSTATE_INT32(enable
, PXA2xxI2SState
),
1734 VMSTATE_INT32(rx_len
, PXA2xxI2SState
),
1735 VMSTATE_INT32(tx_len
, PXA2xxI2SState
),
1736 VMSTATE_INT32(fifo_len
, PXA2xxI2SState
),
1737 VMSTATE_END_OF_LIST()
1741 static void pxa2xx_i2s_data_req(void *opaque
, int tx
, int rx
)
1743 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1746 /* Signal FIFO errors */
1747 if (s
->enable
&& s
->tx_len
)
1748 s
->status
|= 1 << 5; /* TUR */
1749 if (s
->enable
&& s
->rx_len
)
1750 s
->status
|= 1 << 6; /* ROR */
1752 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1753 * handle the cases where it makes a difference. */
1754 s
->tx_len
= tx
- s
->fifo_len
;
1756 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1758 for (sample
= s
->fifo
; s
->fifo_len
; s
->fifo_len
--, sample
++)
1759 s
->codec_out(s
->opaque
, *sample
);
1760 pxa2xx_i2s_update(s
);
1763 static PXA2xxI2SState
*pxa2xx_i2s_init(target_phys_addr_t base
,
1764 qemu_irq irq
, qemu_irq rx_dma
, qemu_irq tx_dma
)
1767 PXA2xxI2SState
*s
= (PXA2xxI2SState
*)
1768 g_malloc0(sizeof(PXA2xxI2SState
));
1773 s
->data_req
= pxa2xx_i2s_data_req
;
1775 pxa2xx_i2s_reset(s
);
1777 iomemtype
= cpu_register_io_memory(pxa2xx_i2s_readfn
,
1778 pxa2xx_i2s_writefn
, s
, DEVICE_NATIVE_ENDIAN
);
1779 cpu_register_physical_memory(base
, 0x100000, iomemtype
);
1781 vmstate_register(NULL
, base
, &vmstate_pxa2xx_i2s
, s
);
1786 /* PXA Fast Infra-red Communications Port */
1787 struct PXA2xxFIrState
{
1792 CharDriverState
*chr
;
1799 uint8_t rx_fifo
[64];
1802 static void pxa2xx_fir_reset(PXA2xxFIrState
*s
)
1804 s
->control
[0] = 0x00;
1805 s
->control
[1] = 0x00;
1806 s
->control
[2] = 0x00;
1807 s
->status
[0] = 0x00;
1808 s
->status
[1] = 0x00;
1812 static inline void pxa2xx_fir_update(PXA2xxFIrState
*s
)
1814 static const int tresh
[4] = { 8, 16, 32, 0 };
1816 if ((s
->control
[0] & (1 << 4)) && /* RXE */
1817 s
->rx_len
>= tresh
[s
->control
[2] & 3]) /* TRIG */
1818 s
->status
[0] |= 1 << 4; /* RFS */
1820 s
->status
[0] &= ~(1 << 4); /* RFS */
1821 if (s
->control
[0] & (1 << 3)) /* TXE */
1822 s
->status
[0] |= 1 << 3; /* TFS */
1824 s
->status
[0] &= ~(1 << 3); /* TFS */
1826 s
->status
[1] |= 1 << 2; /* RNE */
1828 s
->status
[1] &= ~(1 << 2); /* RNE */
1829 if (s
->control
[0] & (1 << 4)) /* RXE */
1830 s
->status
[1] |= 1 << 0; /* RSY */
1832 s
->status
[1] &= ~(1 << 0); /* RSY */
1834 intr
|= (s
->control
[0] & (1 << 5)) && /* RIE */
1835 (s
->status
[0] & (1 << 4)); /* RFS */
1836 intr
|= (s
->control
[0] & (1 << 6)) && /* TIE */
1837 (s
->status
[0] & (1 << 3)); /* TFS */
1838 intr
|= (s
->control
[2] & (1 << 4)) && /* TRAIL */
1839 (s
->status
[0] & (1 << 6)); /* EOC */
1840 intr
|= (s
->control
[0] & (1 << 2)) && /* TUS */
1841 (s
->status
[0] & (1 << 1)); /* TUR */
1842 intr
|= s
->status
[0] & 0x25; /* FRE, RAB, EIF */
1844 qemu_set_irq(s
->rx_dma
, (s
->status
[0] >> 4) & 1);
1845 qemu_set_irq(s
->tx_dma
, (s
->status
[0] >> 3) & 1);
1847 qemu_set_irq(s
->irq
, intr
&& s
->enable
);
1850 #define ICCR0 0x00 /* FICP Control register 0 */
1851 #define ICCR1 0x04 /* FICP Control register 1 */
1852 #define ICCR2 0x08 /* FICP Control register 2 */
1853 #define ICDR 0x0c /* FICP Data register */
1854 #define ICSR0 0x14 /* FICP Status register 0 */
1855 #define ICSR1 0x18 /* FICP Status register 1 */
1856 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1858 static uint32_t pxa2xx_fir_read(void *opaque
, target_phys_addr_t addr
)
1860 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1865 return s
->control
[0];
1867 return s
->control
[1];
1869 return s
->control
[2];
1871 s
->status
[0] &= ~0x01;
1872 s
->status
[1] &= ~0x72;
1875 ret
= s
->rx_fifo
[s
->rx_start
++];
1877 pxa2xx_fir_update(s
);
1880 printf("%s: Rx FIFO underrun.\n", __FUNCTION__
);
1883 return s
->status
[0];
1885 return s
->status
[1] | (1 << 3); /* TNF */
1889 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1895 static void pxa2xx_fir_write(void *opaque
, target_phys_addr_t addr
,
1898 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1903 s
->control
[0] = value
;
1904 if (!(value
& (1 << 4))) /* RXE */
1905 s
->rx_len
= s
->rx_start
= 0;
1906 if (!(value
& (1 << 3))) { /* TXE */
1909 s
->enable
= value
& 1; /* ITR */
1912 pxa2xx_fir_update(s
);
1915 s
->control
[1] = value
;
1918 s
->control
[2] = value
& 0x3f;
1919 pxa2xx_fir_update(s
);
1922 if (s
->control
[2] & (1 << 2)) /* TXP */
1926 if (s
->chr
&& s
->enable
&& (s
->control
[0] & (1 << 3))) /* TXE */
1927 qemu_chr_fe_write(s
->chr
, &ch
, 1);
1930 s
->status
[0] &= ~(value
& 0x66);
1931 pxa2xx_fir_update(s
);
1936 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1940 static CPUReadMemoryFunc
* const pxa2xx_fir_readfn
[] = {
1946 static CPUWriteMemoryFunc
* const pxa2xx_fir_writefn
[] = {
1952 static int pxa2xx_fir_is_empty(void *opaque
)
1954 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1955 return (s
->rx_len
< 64);
1958 static void pxa2xx_fir_rx(void *opaque
, const uint8_t *buf
, int size
)
1960 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1961 if (!(s
->control
[0] & (1 << 4))) /* RXE */
1965 s
->status
[1] |= 1 << 4; /* EOF */
1966 if (s
->rx_len
>= 64) {
1967 s
->status
[1] |= 1 << 6; /* ROR */
1971 if (s
->control
[2] & (1 << 3)) /* RXP */
1972 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = *(buf
++);
1974 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = ~*(buf
++);
1977 pxa2xx_fir_update(s
);
1980 static void pxa2xx_fir_event(void *opaque
, int event
)
1984 static void pxa2xx_fir_save(QEMUFile
*f
, void *opaque
)
1986 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1989 qemu_put_be32(f
, s
->enable
);
1991 qemu_put_8s(f
, &s
->control
[0]);
1992 qemu_put_8s(f
, &s
->control
[1]);
1993 qemu_put_8s(f
, &s
->control
[2]);
1994 qemu_put_8s(f
, &s
->status
[0]);
1995 qemu_put_8s(f
, &s
->status
[1]);
1997 qemu_put_byte(f
, s
->rx_len
);
1998 for (i
= 0; i
< s
->rx_len
; i
++)
1999 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 63]);
2002 static int pxa2xx_fir_load(QEMUFile
*f
, void *opaque
, int version_id
)
2004 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
2007 s
->enable
= qemu_get_be32(f
);
2009 qemu_get_8s(f
, &s
->control
[0]);
2010 qemu_get_8s(f
, &s
->control
[1]);
2011 qemu_get_8s(f
, &s
->control
[2]);
2012 qemu_get_8s(f
, &s
->status
[0]);
2013 qemu_get_8s(f
, &s
->status
[1]);
2015 s
->rx_len
= qemu_get_byte(f
);
2017 for (i
= 0; i
< s
->rx_len
; i
++)
2018 s
->rx_fifo
[i
] = qemu_get_byte(f
);
2023 static PXA2xxFIrState
*pxa2xx_fir_init(target_phys_addr_t base
,
2024 qemu_irq irq
, qemu_irq rx_dma
, qemu_irq tx_dma
,
2025 CharDriverState
*chr
)
2028 PXA2xxFIrState
*s
= (PXA2xxFIrState
*)
2029 g_malloc0(sizeof(PXA2xxFIrState
));
2036 pxa2xx_fir_reset(s
);
2038 iomemtype
= cpu_register_io_memory(pxa2xx_fir_readfn
,
2039 pxa2xx_fir_writefn
, s
, DEVICE_NATIVE_ENDIAN
);
2040 cpu_register_physical_memory(base
, 0x1000, iomemtype
);
2043 qemu_chr_add_handlers(chr
, pxa2xx_fir_is_empty
,
2044 pxa2xx_fir_rx
, pxa2xx_fir_event
, s
);
2046 register_savevm(NULL
, "pxa2xx_fir", 0, 0, pxa2xx_fir_save
,
2047 pxa2xx_fir_load
, s
);
2052 static void pxa2xx_reset(void *opaque
, int line
, int level
)
2054 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
2056 if (level
&& (s
->pm_regs
[PCFR
>> 2] & 0x10)) { /* GPR_EN */
2058 /* TODO: reset peripherals */
2062 /* Initialise a PXA270 integrated chip (ARM based core). */
2063 PXA2xxState
*pxa270_init(unsigned int sdram_size
, const char *revision
)
2068 s
= (PXA2xxState
*) g_malloc0(sizeof(PXA2xxState
));
2070 if (revision
&& strncmp(revision
, "pxa27", 5)) {
2071 fprintf(stderr
, "Machine requires a PXA27x processor.\n");
2075 revision
= "pxa270";
2077 s
->env
= cpu_init(revision
);
2079 fprintf(stderr
, "Unable to find CPU definition\n");
2082 s
->reset
= qemu_allocate_irqs(pxa2xx_reset
, s
, 1)[0];
2084 /* SDRAM & Internal Memory Storage */
2085 cpu_register_physical_memory(PXA2XX_SDRAM_BASE
,
2086 sdram_size
, qemu_ram_alloc(NULL
, "pxa270.sdram",
2087 sdram_size
) | IO_MEM_RAM
);
2088 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE
,
2089 0x40000, qemu_ram_alloc(NULL
, "pxa270.internal",
2090 0x40000) | IO_MEM_RAM
);
2092 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->env
);
2094 s
->dma
= pxa27x_dma_init(0x40000000,
2095 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_DMA
));
2097 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2098 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 0),
2099 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 1),
2100 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 2),
2101 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 3),
2102 qdev_get_gpio_in(s
->pic
, PXA27X_PIC_OST_4_11
),
2105 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->env
, s
->pic
, 121);
2107 dinfo
= drive_get(IF_SD
, 0, 0);
2109 fprintf(stderr
, "qemu: missing SecureDigital device\n");
2112 s
->mmc
= pxa2xx_mmci_init(0x41100000, dinfo
->bdrv
,
2113 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_MMC
),
2114 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_MMCI
),
2115 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_MMCI
));
2117 for (i
= 0; pxa270_serial
[i
].io_base
; i
++) {
2118 if (serial_hds
[i
]) {
2119 serial_mm_init(get_system_memory(), pxa270_serial
[i
].io_base
, 2,
2120 qdev_get_gpio_in(s
->pic
, pxa270_serial
[i
].irqn
),
2121 14857000 / 16, serial_hds
[i
],
2122 DEVICE_NATIVE_ENDIAN
);
2128 s
->fir
= pxa2xx_fir_init(0x40800000,
2129 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_ICP
),
2130 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_ICP
),
2131 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_ICP
),
2134 s
->lcd
= pxa2xx_lcdc_init(0x44000000,
2135 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_LCD
));
2137 s
->cm_base
= 0x41300000;
2138 s
->cm_regs
[CCCR
>> 2] = 0x02000210; /* 416.0 MHz */
2139 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2140 iomemtype
= cpu_register_io_memory(pxa2xx_cm_readfn
,
2141 pxa2xx_cm_writefn
, s
, DEVICE_NATIVE_ENDIAN
);
2142 cpu_register_physical_memory(s
->cm_base
, 0x1000, iomemtype
);
2143 vmstate_register(NULL
, 0, &vmstate_pxa2xx_cm
, s
);
2145 cpu_arm_set_cp_io(s
->env
, 14, pxa2xx_cp14_read
, pxa2xx_cp14_write
, s
);
2147 s
->mm_base
= 0x48000000;
2148 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2149 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2150 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2151 iomemtype
= cpu_register_io_memory(pxa2xx_mm_readfn
,
2152 pxa2xx_mm_writefn
, s
, DEVICE_NATIVE_ENDIAN
);
2153 cpu_register_physical_memory(s
->mm_base
, 0x1000, iomemtype
);
2154 vmstate_register(NULL
, 0, &vmstate_pxa2xx_mm
, s
);
2156 s
->pm_base
= 0x40f00000;
2157 iomemtype
= cpu_register_io_memory(pxa2xx_pm_readfn
,
2158 pxa2xx_pm_writefn
, s
, DEVICE_NATIVE_ENDIAN
);
2159 cpu_register_physical_memory(s
->pm_base
, 0x100, iomemtype
);
2160 vmstate_register(NULL
, 0, &vmstate_pxa2xx_pm
, s
);
2162 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++);
2163 s
->ssp
= (SSIBus
**)g_malloc0(sizeof(SSIBus
*) * i
);
2164 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++) {
2166 dev
= sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp
[i
].io_base
,
2167 qdev_get_gpio_in(s
->pic
, pxa27x_ssp
[i
].irqn
));
2168 s
->ssp
[i
] = (SSIBus
*)qdev_get_child_bus(dev
, "ssi");
2172 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2173 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_USBH1
));
2176 s
->pcmcia
[0] = pxa2xx_pcmcia_init(0x20000000);
2177 s
->pcmcia
[1] = pxa2xx_pcmcia_init(0x30000000);
2179 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2180 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_RTCALARM
));
2182 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600,
2183 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2C
), 0xffff);
2184 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100,
2185 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_PWRI2C
), 0xff);
2187 s
->i2s
= pxa2xx_i2s_init(0x40400000,
2188 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2S
),
2189 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_I2S
),
2190 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_I2S
));
2192 s
->kp
= pxa27x_keypad_init(0x41500000,
2193 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_KEYPAD
));
2195 /* GPIO1 resets the processor */
2196 /* The handler can be overridden by board-specific code */
2197 qdev_connect_gpio_out(s
->gpio
, 1, s
->reset
);
2201 /* Initialise a PXA255 integrated chip (ARM based core). */
2202 PXA2xxState
*pxa255_init(unsigned int sdram_size
)
2208 s
= (PXA2xxState
*) g_malloc0(sizeof(PXA2xxState
));
2210 s
->env
= cpu_init("pxa255");
2212 fprintf(stderr
, "Unable to find CPU definition\n");
2215 s
->reset
= qemu_allocate_irqs(pxa2xx_reset
, s
, 1)[0];
2217 /* SDRAM & Internal Memory Storage */
2218 cpu_register_physical_memory(PXA2XX_SDRAM_BASE
, sdram_size
,
2219 qemu_ram_alloc(NULL
, "pxa255.sdram",
2220 sdram_size
) | IO_MEM_RAM
);
2221 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE
, PXA2XX_INTERNAL_SIZE
,
2222 qemu_ram_alloc(NULL
, "pxa255.internal",
2223 PXA2XX_INTERNAL_SIZE
) | IO_MEM_RAM
);
2225 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->env
);
2227 s
->dma
= pxa255_dma_init(0x40000000,
2228 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_DMA
));
2230 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2231 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 0),
2232 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 1),
2233 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 2),
2234 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 3),
2237 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->env
, s
->pic
, 85);
2239 dinfo
= drive_get(IF_SD
, 0, 0);
2241 fprintf(stderr
, "qemu: missing SecureDigital device\n");
2244 s
->mmc
= pxa2xx_mmci_init(0x41100000, dinfo
->bdrv
,
2245 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_MMC
),
2246 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_MMCI
),
2247 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_MMCI
));
2249 for (i
= 0; pxa255_serial
[i
].io_base
; i
++) {
2250 if (serial_hds
[i
]) {
2251 serial_mm_init(get_system_memory(), pxa255_serial
[i
].io_base
, 2,
2252 qdev_get_gpio_in(s
->pic
, pxa255_serial
[i
].irqn
),
2253 14745600 / 16, serial_hds
[i
],
2254 DEVICE_NATIVE_ENDIAN
);
2260 s
->fir
= pxa2xx_fir_init(0x40800000,
2261 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_ICP
),
2262 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_ICP
),
2263 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_ICP
),
2266 s
->lcd
= pxa2xx_lcdc_init(0x44000000,
2267 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_LCD
));
2269 s
->cm_base
= 0x41300000;
2270 s
->cm_regs
[CCCR
>> 2] = 0x02000210; /* 416.0 MHz */
2271 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2272 iomemtype
= cpu_register_io_memory(pxa2xx_cm_readfn
,
2273 pxa2xx_cm_writefn
, s
, DEVICE_NATIVE_ENDIAN
);
2274 cpu_register_physical_memory(s
->cm_base
, 0x1000, iomemtype
);
2275 vmstate_register(NULL
, 0, &vmstate_pxa2xx_cm
, s
);
2277 cpu_arm_set_cp_io(s
->env
, 14, pxa2xx_cp14_read
, pxa2xx_cp14_write
, s
);
2279 s
->mm_base
= 0x48000000;
2280 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2281 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2282 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2283 iomemtype
= cpu_register_io_memory(pxa2xx_mm_readfn
,
2284 pxa2xx_mm_writefn
, s
, DEVICE_NATIVE_ENDIAN
);
2285 cpu_register_physical_memory(s
->mm_base
, 0x1000, iomemtype
);
2286 vmstate_register(NULL
, 0, &vmstate_pxa2xx_mm
, s
);
2288 s
->pm_base
= 0x40f00000;
2289 iomemtype
= cpu_register_io_memory(pxa2xx_pm_readfn
,
2290 pxa2xx_pm_writefn
, s
, DEVICE_NATIVE_ENDIAN
);
2291 cpu_register_physical_memory(s
->pm_base
, 0x100, iomemtype
);
2292 vmstate_register(NULL
, 0, &vmstate_pxa2xx_pm
, s
);
2294 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++);
2295 s
->ssp
= (SSIBus
**)g_malloc0(sizeof(SSIBus
*) * i
);
2296 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++) {
2298 dev
= sysbus_create_simple("pxa2xx-ssp", pxa255_ssp
[i
].io_base
,
2299 qdev_get_gpio_in(s
->pic
, pxa255_ssp
[i
].irqn
));
2300 s
->ssp
[i
] = (SSIBus
*)qdev_get_child_bus(dev
, "ssi");
2304 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2305 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_USBH1
));
2308 s
->pcmcia
[0] = pxa2xx_pcmcia_init(0x20000000);
2309 s
->pcmcia
[1] = pxa2xx_pcmcia_init(0x30000000);
2311 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2312 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_RTCALARM
));
2314 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600,
2315 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2C
), 0xffff);
2316 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100,
2317 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_PWRI2C
), 0xff);
2319 s
->i2s
= pxa2xx_i2s_init(0x40400000,
2320 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2S
),
2321 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_I2S
),
2322 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_I2S
));
2324 /* GPIO1 resets the processor */
2325 /* The handler can be overridden by board-specific code */
2326 qdev_connect_gpio_out(s
->gpio
, 1, s
->reset
);
2330 static void pxa2xx_register_devices(void)
2332 i2c_register_slave(&pxa2xx_i2c_slave_info
);
2333 sysbus_register_dev("pxa2xx-ssp", sizeof(PXA2xxSSPState
), pxa2xx_ssp_init
);
2334 sysbus_register_withprop(&pxa2xx_i2c_info
);
2335 sysbus_register_withprop(&pxa2xx_rtc_sysbus_info
);
2338 device_init(pxa2xx_register_devices
)