2 * Intel XScale PXA255/270 processor support.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licenced under the GPL.
13 target_phys_addr_t io_base
;
16 { 0x40100000, PXA2XX_PIC_FFUART
},
17 { 0x40200000, PXA2XX_PIC_BTUART
},
18 { 0x40700000, PXA2XX_PIC_STUART
},
19 { 0x41600000, PXA25X_PIC_HWUART
},
21 }, pxa270_serial
[] = {
22 { 0x40100000, PXA2XX_PIC_FFUART
},
23 { 0x40200000, PXA2XX_PIC_BTUART
},
24 { 0x40700000, PXA2XX_PIC_STUART
},
29 target_phys_addr_t io_base
;
32 { 0x41000000, PXA2XX_PIC_SSP
},
35 { 0x41000000, PXA2XX_PIC_SSP
},
36 { 0x41400000, PXA25X_PIC_NSSP
},
39 { 0x41000000, PXA2XX_PIC_SSP
},
40 { 0x41400000, PXA25X_PIC_NSSP
},
41 { 0x41500000, PXA26X_PIC_ASSP
},
44 { 0x41000000, PXA2XX_PIC_SSP
},
45 { 0x41700000, PXA27X_PIC_SSP2
},
46 { 0x41900000, PXA2XX_PIC_SSP3
},
50 #define PMCR 0x00 /* Power Manager Control register */
51 #define PSSR 0x04 /* Power Manager Sleep Status register */
52 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
53 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
54 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
55 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
56 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
57 #define PCFR 0x1c /* Power Manager General Configuration register */
58 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
59 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
60 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
61 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
62 #define RCSR 0x30 /* Reset Controller Status register */
63 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
64 #define PTSR 0x38 /* Power Manager Standby Configuration register */
65 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
66 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
67 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
68 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
69 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
70 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
72 static uint32_t pxa2xx_pm_read(void *opaque
, target_phys_addr_t addr
)
74 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
82 return s
->pm_regs
[addr
>> 2];
85 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
91 static void pxa2xx_pm_write(void *opaque
, target_phys_addr_t addr
,
94 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
99 s
->pm_regs
[addr
>> 2] &= 0x15 & ~(value
& 0x2a);
100 s
->pm_regs
[addr
>> 2] |= value
& 0x15;
103 case PSSR
: /* Read-clean registers */
106 s
->pm_regs
[addr
>> 2] &= ~value
;
109 default: /* Read-write registers */
110 if (addr
>= PMCR
&& addr
<= PCMD31
&& !(addr
& 3)) {
111 s
->pm_regs
[addr
>> 2] = value
;
115 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
120 static CPUReadMemoryFunc
*pxa2xx_pm_readfn
[] = {
126 static CPUWriteMemoryFunc
*pxa2xx_pm_writefn
[] = {
132 #define CCCR 0x00 /* Core Clock Configuration register */
133 #define CKEN 0x04 /* Clock Enable register */
134 #define OSCC 0x08 /* Oscillator Configuration register */
135 #define CCSR 0x0c /* Core Clock Status register */
137 static uint32_t pxa2xx_cm_read(void *opaque
, target_phys_addr_t addr
)
139 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
146 return s
->cm_regs
[addr
>> 2];
149 return s
->cm_regs
[CCCR
>> 2] | (3 << 28);
152 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
158 static void pxa2xx_cm_write(void *opaque
, target_phys_addr_t addr
,
161 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
167 s
->cm_regs
[addr
>> 2] = value
;
171 s
->cm_regs
[addr
>> 2] &= ~0x6e;
172 s
->cm_regs
[addr
>> 2] |= value
& 0x6e;
176 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
181 static CPUReadMemoryFunc
*pxa2xx_cm_readfn
[] = {
187 static CPUWriteMemoryFunc
*pxa2xx_cm_writefn
[] = {
193 static uint32_t pxa2xx_clkpwr_read(void *opaque
, int op2
, int reg
, int crm
)
195 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
198 case 6: /* Clock Configuration register */
201 case 7: /* Power Mode register */
205 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
211 static void pxa2xx_clkpwr_write(void *opaque
, int op2
, int reg
, int crm
,
214 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
215 static const char *pwrmode
[8] = {
216 "Normal", "Idle", "Deep-idle", "Standby",
217 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
221 case 6: /* Clock Configuration register */
222 s
->clkcfg
= value
& 0xf;
224 printf("%s: CPU frequency change attempt\n", __FUNCTION__
);
227 case 7: /* Power Mode register */
229 printf("%s: CPU voltage change attempt\n", __FUNCTION__
);
237 if (!(s
->cm_regs
[CCCR
] & (1 << 31))) { /* CPDIS */
238 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
245 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
246 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
251 s
->env
->cp15
.c1_sys
= 0;
252 s
->env
->cp15
.c1_coproc
= 0;
255 s
->pm_regs
[PSSR
>> 2] |= 0x8; /* Set STS */
256 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
259 * The scratch-pad register is almost universally used
260 * for storing the return address on suspend. For the
261 * lack of a resuming bootloader, perform a jump
262 * directly to that address.
264 memset(s
->env
->regs
, 0, 4 * 15);
265 s
->env
->regs
[15] = s
->pm_regs
[PSPR
>> 2];
268 buffer
= 0xe59ff000; /* ldr pc, [pc, #0] */
269 cpu_physical_memory_write(0, &buffer
, 4);
270 buffer
= s
->pm_regs
[PSPR
>> 2];
271 cpu_physical_memory_write(8, &buffer
, 4);
275 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HALT
);
281 printf("%s: machine entered %s mode\n", __FUNCTION__
,
287 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
292 /* Performace Monitoring Registers */
293 #define CPPMNC 0 /* Performance Monitor Control register */
294 #define CPCCNT 1 /* Clock Counter register */
295 #define CPINTEN 4 /* Interrupt Enable register */
296 #define CPFLAG 5 /* Overflow Flag register */
297 #define CPEVTSEL 8 /* Event Selection register */
299 #define CPPMN0 0 /* Performance Count register 0 */
300 #define CPPMN1 1 /* Performance Count register 1 */
301 #define CPPMN2 2 /* Performance Count register 2 */
302 #define CPPMN3 3 /* Performance Count register 3 */
304 static uint32_t pxa2xx_perf_read(void *opaque
, int op2
, int reg
, int crm
)
306 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
313 return qemu_get_clock(vm_clock
);
322 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
328 static void pxa2xx_perf_write(void *opaque
, int op2
, int reg
, int crm
,
331 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
345 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
350 static uint32_t pxa2xx_cp14_read(void *opaque
, int op2
, int reg
, int crm
)
354 return pxa2xx_clkpwr_read(opaque
, op2
, reg
, crm
);
356 return pxa2xx_perf_read(opaque
, op2
, reg
, crm
);
367 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
373 static void pxa2xx_cp14_write(void *opaque
, int op2
, int reg
, int crm
,
378 pxa2xx_clkpwr_write(opaque
, op2
, reg
, crm
, value
);
381 pxa2xx_perf_write(opaque
, op2
, reg
, crm
, value
);
393 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
398 #define MDCNFG 0x00 /* SDRAM Configuration register */
399 #define MDREFR 0x04 /* SDRAM Refresh Control register */
400 #define MSC0 0x08 /* Static Memory Control register 0 */
401 #define MSC1 0x0c /* Static Memory Control register 1 */
402 #define MSC2 0x10 /* Static Memory Control register 2 */
403 #define MECR 0x14 /* Expansion Memory Bus Config register */
404 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
405 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
406 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
407 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
408 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
409 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
410 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
411 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
412 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
413 #define ARB_CNTL 0x48 /* Arbiter Control register */
414 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
415 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
416 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
417 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
418 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
419 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
420 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
422 static uint32_t pxa2xx_mm_read(void *opaque
, target_phys_addr_t addr
)
424 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
428 case MDCNFG
... SA1110
:
430 return s
->mm_regs
[addr
>> 2];
433 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
439 static void pxa2xx_mm_write(void *opaque
, target_phys_addr_t addr
,
442 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
446 case MDCNFG
... SA1110
:
447 if ((addr
& 3) == 0) {
448 s
->mm_regs
[addr
>> 2] = value
;
453 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
458 static CPUReadMemoryFunc
*pxa2xx_mm_readfn
[] = {
464 static CPUWriteMemoryFunc
*pxa2xx_mm_writefn
[] = {
470 /* Synchronous Serial Ports */
471 struct pxa2xx_ssp_s
{
472 target_phys_addr_t base
;
485 uint32_t rx_fifo
[16];
489 uint32_t (*readfn
)(void *opaque
);
490 void (*writefn
)(void *opaque
, uint32_t value
);
494 #define SSCR0 0x00 /* SSP Control register 0 */
495 #define SSCR1 0x04 /* SSP Control register 1 */
496 #define SSSR 0x08 /* SSP Status register */
497 #define SSITR 0x0c /* SSP Interrupt Test register */
498 #define SSDR 0x10 /* SSP Data register */
499 #define SSTO 0x28 /* SSP Time-Out register */
500 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
501 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
502 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
503 #define SSTSS 0x38 /* SSP Time Slot Status register */
504 #define SSACD 0x3c /* SSP Audio Clock Divider register */
506 /* Bitfields for above registers */
507 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
508 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
509 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
510 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
511 #define SSCR0_SSE (1 << 7)
512 #define SSCR0_RIM (1 << 22)
513 #define SSCR0_TIM (1 << 23)
514 #define SSCR0_MOD (1 << 31)
515 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
516 #define SSCR1_RIE (1 << 0)
517 #define SSCR1_TIE (1 << 1)
518 #define SSCR1_LBM (1 << 2)
519 #define SSCR1_MWDS (1 << 5)
520 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
521 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
522 #define SSCR1_EFWR (1 << 14)
523 #define SSCR1_PINTE (1 << 18)
524 #define SSCR1_TINTE (1 << 19)
525 #define SSCR1_RSRE (1 << 20)
526 #define SSCR1_TSRE (1 << 21)
527 #define SSCR1_EBCEI (1 << 29)
528 #define SSITR_INT (7 << 5)
529 #define SSSR_TNF (1 << 2)
530 #define SSSR_RNE (1 << 3)
531 #define SSSR_TFS (1 << 5)
532 #define SSSR_RFS (1 << 6)
533 #define SSSR_ROR (1 << 7)
534 #define SSSR_PINT (1 << 18)
535 #define SSSR_TINT (1 << 19)
536 #define SSSR_EOC (1 << 20)
537 #define SSSR_TUR (1 << 21)
538 #define SSSR_BCE (1 << 23)
539 #define SSSR_RW 0x00bc0080
541 static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s
*s
)
545 level
|= s
->ssitr
& SSITR_INT
;
546 level
|= (s
->sssr
& SSSR_BCE
) && (s
->sscr
[1] & SSCR1_EBCEI
);
547 level
|= (s
->sssr
& SSSR_TUR
) && !(s
->sscr
[0] & SSCR0_TIM
);
548 level
|= (s
->sssr
& SSSR_EOC
) && (s
->sssr
& (SSSR_TINT
| SSSR_PINT
));
549 level
|= (s
->sssr
& SSSR_TINT
) && (s
->sscr
[1] & SSCR1_TINTE
);
550 level
|= (s
->sssr
& SSSR_PINT
) && (s
->sscr
[1] & SSCR1_PINTE
);
551 level
|= (s
->sssr
& SSSR_ROR
) && !(s
->sscr
[0] & SSCR0_RIM
);
552 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
553 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
554 qemu_set_irq(s
->irq
, !!level
);
557 static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s
*s
)
559 s
->sssr
&= ~(0xf << 12); /* Clear RFL */
560 s
->sssr
&= ~(0xf << 8); /* Clear TFL */
561 s
->sssr
&= ~SSSR_TNF
;
563 s
->sssr
|= ((s
->rx_level
- 1) & 0xf) << 12;
564 if (s
->rx_level
>= SSCR1_RFT(s
->sscr
[1]))
567 s
->sssr
&= ~SSSR_RFS
;
568 if (0 <= SSCR1_TFT(s
->sscr
[1]))
571 s
->sssr
&= ~SSSR_TFS
;
575 s
->sssr
&= ~SSSR_RNE
;
579 pxa2xx_ssp_int_update(s
);
582 static uint32_t pxa2xx_ssp_read(void *opaque
, target_phys_addr_t addr
)
584 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
600 return s
->sssr
| s
->ssitr
;
604 if (s
->rx_level
< 1) {
605 printf("%s: SSP Rx Underrun\n", __FUNCTION__
);
609 retval
= s
->rx_fifo
[s
->rx_start
++];
611 pxa2xx_ssp_fifo_update(s
);
622 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
628 static void pxa2xx_ssp_write(void *opaque
, target_phys_addr_t addr
,
631 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
636 s
->sscr
[0] = value
& 0xc7ffffff;
637 s
->enable
= value
& SSCR0_SSE
;
638 if (value
& SSCR0_MOD
)
639 printf("%s: Attempt to use network mode\n", __FUNCTION__
);
640 if (s
->enable
&& SSCR0_DSS(value
) < 4)
641 printf("%s: Wrong data size: %i bits\n", __FUNCTION__
,
643 if (!(value
& SSCR0_SSE
)) {
648 pxa2xx_ssp_fifo_update(s
);
653 if (value
& (SSCR1_LBM
| SSCR1_EFWR
))
654 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__
);
655 pxa2xx_ssp_fifo_update(s
);
667 s
->ssitr
= value
& SSITR_INT
;
668 pxa2xx_ssp_int_update(s
);
672 s
->sssr
&= ~(value
& SSSR_RW
);
673 pxa2xx_ssp_int_update(s
);
677 if (SSCR0_UWIRE(s
->sscr
[0])) {
678 if (s
->sscr
[1] & SSCR1_MWDS
)
683 /* Note how 32bits overflow does no harm here */
684 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
686 /* Data goes from here to the Tx FIFO and is shifted out from
687 * there directly to the slave, no need to buffer it.
691 s
->writefn(s
->opaque
, value
);
693 if (s
->rx_level
< 0x10) {
695 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0xf] =
696 s
->readfn(s
->opaque
);
698 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0xf] = 0x0;
702 pxa2xx_ssp_fifo_update(s
);
718 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
723 void pxa2xx_ssp_attach(struct pxa2xx_ssp_s
*port
,
724 uint32_t (*readfn
)(void *opaque
),
725 void (*writefn
)(void *opaque
, uint32_t value
), void *opaque
)
728 printf("%s: no such SSP\n", __FUNCTION__
);
732 port
->opaque
= opaque
;
733 port
->readfn
= readfn
;
734 port
->writefn
= writefn
;
737 static CPUReadMemoryFunc
*pxa2xx_ssp_readfn
[] = {
743 static CPUWriteMemoryFunc
*pxa2xx_ssp_writefn
[] = {
749 /* Real-Time Clock */
750 #define RCNR 0x00 /* RTC Counter register */
751 #define RTAR 0x04 /* RTC Alarm register */
752 #define RTSR 0x08 /* RTC Status register */
753 #define RTTR 0x0c /* RTC Timer Trim register */
754 #define RDCR 0x10 /* RTC Day Counter register */
755 #define RYCR 0x14 /* RTC Year Counter register */
756 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
757 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
758 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
759 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
760 #define SWCR 0x28 /* RTC Stopwatch Counter register */
761 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
762 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
763 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
764 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
766 static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s
*s
)
768 qemu_set_irq(s
->pic
[PXA2XX_PIC_RTCALARM
], !!(s
->rtsr
& 0x2553));
771 static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s
*s
)
773 int64_t rt
= qemu_get_clock(rt_clock
);
774 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
775 (1000 * ((s
->rttr
& 0xffff) + 1));
776 s
->last_rdcr
+= ((rt
- s
->last_hz
) << 15) /
777 (1000 * ((s
->rttr
& 0xffff) + 1));
781 static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s
*s
)
783 int64_t rt
= qemu_get_clock(rt_clock
);
784 if (s
->rtsr
& (1 << 12))
785 s
->last_swcr
+= (rt
- s
->last_sw
) / 10;
789 static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s
*s
)
791 int64_t rt
= qemu_get_clock(rt_clock
);
792 if (s
->rtsr
& (1 << 15))
793 s
->last_swcr
+= rt
- s
->last_pi
;
797 static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s
*s
,
800 if ((rtsr
& (1 << 2)) && !(rtsr
& (1 << 0)))
801 qemu_mod_timer(s
->rtc_hz
, s
->last_hz
+
802 (((s
->rtar
- s
->last_rcnr
) * 1000 *
803 ((s
->rttr
& 0xffff) + 1)) >> 15));
805 qemu_del_timer(s
->rtc_hz
);
807 if ((rtsr
& (1 << 5)) && !(rtsr
& (1 << 4)))
808 qemu_mod_timer(s
->rtc_rdal1
, s
->last_hz
+
809 (((s
->rdar1
- s
->last_rdcr
) * 1000 *
810 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
812 qemu_del_timer(s
->rtc_rdal1
);
814 if ((rtsr
& (1 << 7)) && !(rtsr
& (1 << 6)))
815 qemu_mod_timer(s
->rtc_rdal2
, s
->last_hz
+
816 (((s
->rdar2
- s
->last_rdcr
) * 1000 *
817 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
819 qemu_del_timer(s
->rtc_rdal2
);
821 if ((rtsr
& 0x1200) == 0x1200 && !(rtsr
& (1 << 8)))
822 qemu_mod_timer(s
->rtc_swal1
, s
->last_sw
+
823 (s
->swar1
- s
->last_swcr
) * 10); /* TODO: fixup */
825 qemu_del_timer(s
->rtc_swal1
);
827 if ((rtsr
& 0x1800) == 0x1800 && !(rtsr
& (1 << 10)))
828 qemu_mod_timer(s
->rtc_swal2
, s
->last_sw
+
829 (s
->swar2
- s
->last_swcr
) * 10); /* TODO: fixup */
831 qemu_del_timer(s
->rtc_swal2
);
833 if ((rtsr
& 0xc000) == 0xc000 && !(rtsr
& (1 << 13)))
834 qemu_mod_timer(s
->rtc_pi
, s
->last_pi
+
835 (s
->piar
& 0xffff) - s
->last_rtcpicr
);
837 qemu_del_timer(s
->rtc_pi
);
840 static inline void pxa2xx_rtc_hz_tick(void *opaque
)
842 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
844 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
845 pxa2xx_rtc_int_update(s
);
848 static inline void pxa2xx_rtc_rdal1_tick(void *opaque
)
850 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
852 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
853 pxa2xx_rtc_int_update(s
);
856 static inline void pxa2xx_rtc_rdal2_tick(void *opaque
)
858 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
860 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
861 pxa2xx_rtc_int_update(s
);
864 static inline void pxa2xx_rtc_swal1_tick(void *opaque
)
866 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
868 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
869 pxa2xx_rtc_int_update(s
);
872 static inline void pxa2xx_rtc_swal2_tick(void *opaque
)
874 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
875 s
->rtsr
|= (1 << 10);
876 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
877 pxa2xx_rtc_int_update(s
);
880 static inline void pxa2xx_rtc_pi_tick(void *opaque
)
882 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
883 s
->rtsr
|= (1 << 13);
884 pxa2xx_rtc_piupdate(s
);
886 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
887 pxa2xx_rtc_int_update(s
);
890 static uint32_t pxa2xx_rtc_read(void *opaque
, target_phys_addr_t addr
)
892 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
917 return s
->last_rcnr
+ ((qemu_get_clock(rt_clock
) - s
->last_hz
) << 15) /
918 (1000 * ((s
->rttr
& 0xffff) + 1));
920 return s
->last_rdcr
+ ((qemu_get_clock(rt_clock
) - s
->last_hz
) << 15) /
921 (1000 * ((s
->rttr
& 0xffff) + 1));
925 if (s
->rtsr
& (1 << 12))
926 return s
->last_swcr
+ (qemu_get_clock(rt_clock
) - s
->last_sw
) / 10;
930 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
936 static void pxa2xx_rtc_write(void *opaque
, target_phys_addr_t addr
,
939 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
944 if (!(s
->rttr
& (1 << 31))) {
945 pxa2xx_rtc_hzupdate(s
);
947 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
952 if ((s
->rtsr
^ value
) & (1 << 15))
953 pxa2xx_rtc_piupdate(s
);
955 if ((s
->rtsr
^ value
) & (1 << 12))
956 pxa2xx_rtc_swupdate(s
);
958 if (((s
->rtsr
^ value
) & 0x4aac) | (value
& ~0xdaac))
959 pxa2xx_rtc_alarm_update(s
, value
);
961 s
->rtsr
= (value
& 0xdaac) | (s
->rtsr
& ~(value
& ~0xdaac));
962 pxa2xx_rtc_int_update(s
);
967 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
972 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
977 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
982 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
987 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
991 pxa2xx_rtc_swupdate(s
);
994 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
999 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1004 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1008 pxa2xx_rtc_hzupdate(s
);
1009 s
->last_rcnr
= value
;
1010 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1014 pxa2xx_rtc_hzupdate(s
);
1015 s
->last_rdcr
= value
;
1016 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1020 s
->last_rycr
= value
;
1024 pxa2xx_rtc_swupdate(s
);
1025 s
->last_swcr
= value
;
1026 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1030 pxa2xx_rtc_piupdate(s
);
1031 s
->last_rtcpicr
= value
& 0xffff;
1032 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1036 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1040 static void pxa2xx_rtc_reset(struct pxa2xx_state_s
*s
)
1053 tm
= localtime(&ti
);
1054 wom
= ((tm
->tm_mday
- 1) / 7) + 1;
1056 s
->last_rcnr
= (uint32_t) ti
;
1057 s
->last_rdcr
= (wom
<< 20) | ((tm
->tm_wday
+ 1) << 17) |
1058 (tm
->tm_hour
<< 12) | (tm
->tm_min
<< 6) | tm
->tm_sec
;
1059 s
->last_rycr
= ((tm
->tm_year
+ 1900) << 9) |
1060 ((tm
->tm_mon
+ 1) << 5) | tm
->tm_mday
;
1061 s
->last_swcr
= (tm
->tm_hour
<< 19) |
1062 (tm
->tm_min
<< 13) | (tm
->tm_sec
<< 7);
1063 s
->last_rtcpicr
= 0;
1064 s
->last_hz
= s
->last_sw
= s
->last_pi
= qemu_get_clock(rt_clock
);
1066 s
->rtc_hz
= qemu_new_timer(rt_clock
, pxa2xx_rtc_hz_tick
, s
);
1067 s
->rtc_rdal1
= qemu_new_timer(rt_clock
, pxa2xx_rtc_rdal1_tick
, s
);
1068 s
->rtc_rdal2
= qemu_new_timer(rt_clock
, pxa2xx_rtc_rdal2_tick
, s
);
1069 s
->rtc_swal1
= qemu_new_timer(rt_clock
, pxa2xx_rtc_swal1_tick
, s
);
1070 s
->rtc_swal2
= qemu_new_timer(rt_clock
, pxa2xx_rtc_swal2_tick
, s
);
1071 s
->rtc_pi
= qemu_new_timer(rt_clock
, pxa2xx_rtc_pi_tick
, s
);
1074 static CPUReadMemoryFunc
*pxa2xx_rtc_readfn
[] = {
1080 static CPUWriteMemoryFunc
*pxa2xx_rtc_writefn
[] = {
1086 /* PXA Inter-IC Sound Controller */
1087 static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s
*i2s
)
1093 i2s
->control
[0] = 0x00;
1094 i2s
->control
[1] = 0x00;
1099 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1100 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1101 #define SACR_DREC(val) (val & (1 << 3))
1102 #define SACR_DPRL(val) (val & (1 << 4))
1104 static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s
*i2s
)
1107 rfs
= SACR_RFTH(i2s
->control
[0]) < i2s
->rx_len
&&
1108 !SACR_DREC(i2s
->control
[1]);
1109 tfs
= (i2s
->tx_len
|| i2s
->fifo_len
< SACR_TFTH(i2s
->control
[0])) &&
1110 i2s
->enable
&& !SACR_DPRL(i2s
->control
[1]);
1112 pxa2xx_dma_request(i2s
->dma
, PXA2XX_RX_RQ_I2S
, rfs
);
1113 pxa2xx_dma_request(i2s
->dma
, PXA2XX_TX_RQ_I2S
, tfs
);
1115 i2s
->status
&= 0xe0;
1117 i2s
->status
|= 1 << 1; /* RNE */
1119 i2s
->status
|= 1 << 2; /* BSY */
1121 i2s
->status
|= 1 << 3; /* TFS */
1123 i2s
->status
|= 1 << 4; /* RFS */
1124 if (!(i2s
->tx_len
&& i2s
->enable
))
1125 i2s
->status
|= i2s
->fifo_len
<< 8; /* TFL */
1126 i2s
->status
|= MAX(i2s
->rx_len
, 0xf) << 12; /* RFL */
1128 qemu_set_irq(i2s
->irq
, i2s
->status
& i2s
->mask
);
1131 #define SACR0 0x00 /* Serial Audio Global Control register */
1132 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1133 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1134 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1135 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1136 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1137 #define SADR 0x80 /* Serial Audio Data register */
1139 static uint32_t pxa2xx_i2s_read(void *opaque
, target_phys_addr_t addr
)
1141 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1146 return s
->control
[0];
1148 return s
->control
[1];
1158 if (s
->rx_len
> 0) {
1160 pxa2xx_i2s_update(s
);
1161 return s
->codec_in(s
->opaque
);
1165 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1171 static void pxa2xx_i2s_write(void *opaque
, target_phys_addr_t addr
,
1174 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1180 if (value
& (1 << 3)) /* RST */
1181 pxa2xx_i2s_reset(s
);
1182 s
->control
[0] = value
& 0xff3d;
1183 if (!s
->enable
&& (value
& 1) && s
->tx_len
) { /* ENB */
1184 for (sample
= s
->fifo
; s
->fifo_len
> 0; s
->fifo_len
--, sample
++)
1185 s
->codec_out(s
->opaque
, *sample
);
1186 s
->status
&= ~(1 << 7); /* I2SOFF */
1188 if (value
& (1 << 4)) /* EFWR */
1189 printf("%s: Attempt to use special function\n", __FUNCTION__
);
1190 s
->enable
= ((value
^ 4) & 5) == 5; /* ENB && !RST*/
1191 pxa2xx_i2s_update(s
);
1194 s
->control
[1] = value
& 0x0039;
1195 if (value
& (1 << 5)) /* ENLBF */
1196 printf("%s: Attempt to use loopback function\n", __FUNCTION__
);
1197 if (value
& (1 << 4)) /* DPRL */
1199 pxa2xx_i2s_update(s
);
1202 s
->mask
= value
& 0x0078;
1203 pxa2xx_i2s_update(s
);
1206 s
->status
&= ~(value
& (3 << 5));
1207 pxa2xx_i2s_update(s
);
1210 s
->clk
= value
& 0x007f;
1213 if (s
->tx_len
&& s
->enable
) {
1215 pxa2xx_i2s_update(s
);
1216 s
->codec_out(s
->opaque
, value
);
1217 } else if (s
->fifo_len
< 16) {
1218 s
->fifo
[s
->fifo_len
++] = value
;
1219 pxa2xx_i2s_update(s
);
1223 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1227 static CPUReadMemoryFunc
*pxa2xx_i2s_readfn
[] = {
1233 static CPUWriteMemoryFunc
*pxa2xx_i2s_writefn
[] = {
1239 static void pxa2xx_i2s_data_req(void *opaque
, int tx
, int rx
)
1241 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1244 /* Signal FIFO errors */
1245 if (s
->enable
&& s
->tx_len
)
1246 s
->status
|= 1 << 5; /* TUR */
1247 if (s
->enable
&& s
->rx_len
)
1248 s
->status
|= 1 << 6; /* ROR */
1250 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1251 * handle the cases where it makes a difference. */
1252 s
->tx_len
= tx
- s
->fifo_len
;
1254 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1256 for (sample
= s
->fifo
; s
->fifo_len
; s
->fifo_len
--, sample
++)
1257 s
->codec_out(s
->opaque
, *sample
);
1258 pxa2xx_i2s_update(s
);
1261 static struct pxa2xx_i2s_s
*pxa2xx_i2s_init(target_phys_addr_t base
,
1262 qemu_irq irq
, struct pxa2xx_dma_state_s
*dma
)
1265 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*)
1266 qemu_mallocz(sizeof(struct pxa2xx_i2s_s
));
1271 s
->data_req
= pxa2xx_i2s_data_req
;
1273 pxa2xx_i2s_reset(s
);
1275 iomemtype
= cpu_register_io_memory(0, pxa2xx_i2s_readfn
,
1276 pxa2xx_i2s_writefn
, s
);
1277 cpu_register_physical_memory(s
->base
& 0xfff00000, 0xfffff, iomemtype
);
1282 /* PXA Fast Infra-red Communications Port */
1283 struct pxa2xx_fir_s
{
1284 target_phys_addr_t base
;
1286 struct pxa2xx_dma_state_s
*dma
;
1288 CharDriverState
*chr
;
1295 uint8_t rx_fifo
[64];
1298 static void pxa2xx_fir_reset(struct pxa2xx_fir_s
*s
)
1300 s
->control
[0] = 0x00;
1301 s
->control
[1] = 0x00;
1302 s
->control
[2] = 0x00;
1303 s
->status
[0] = 0x00;
1304 s
->status
[1] = 0x00;
1308 static inline void pxa2xx_fir_update(struct pxa2xx_fir_s
*s
)
1310 static const int tresh
[4] = { 8, 16, 32, 0 };
1312 if ((s
->control
[0] & (1 << 4)) && /* RXE */
1313 s
->rx_len
>= tresh
[s
->control
[2] & 3]) /* TRIG */
1314 s
->status
[0] |= 1 << 4; /* RFS */
1316 s
->status
[0] &= ~(1 << 4); /* RFS */
1317 if (s
->control
[0] & (1 << 3)) /* TXE */
1318 s
->status
[0] |= 1 << 3; /* TFS */
1320 s
->status
[0] &= ~(1 << 3); /* TFS */
1322 s
->status
[1] |= 1 << 2; /* RNE */
1324 s
->status
[1] &= ~(1 << 2); /* RNE */
1325 if (s
->control
[0] & (1 << 4)) /* RXE */
1326 s
->status
[1] |= 1 << 0; /* RSY */
1328 s
->status
[1] &= ~(1 << 0); /* RSY */
1330 intr
|= (s
->control
[0] & (1 << 5)) && /* RIE */
1331 (s
->status
[0] & (1 << 4)); /* RFS */
1332 intr
|= (s
->control
[0] & (1 << 6)) && /* TIE */
1333 (s
->status
[0] & (1 << 3)); /* TFS */
1334 intr
|= (s
->control
[2] & (1 << 4)) && /* TRAIL */
1335 (s
->status
[0] & (1 << 6)); /* EOC */
1336 intr
|= (s
->control
[0] & (1 << 2)) && /* TUS */
1337 (s
->status
[0] & (1 << 1)); /* TUR */
1338 intr
|= s
->status
[0] & 0x25; /* FRE, RAB, EIF */
1340 pxa2xx_dma_request(s
->dma
, PXA2XX_RX_RQ_ICP
, (s
->status
[0] >> 4) & 1);
1341 pxa2xx_dma_request(s
->dma
, PXA2XX_TX_RQ_ICP
, (s
->status
[0] >> 3) & 1);
1343 qemu_set_irq(s
->irq
, intr
&& s
->enable
);
1346 #define ICCR0 0x00 /* FICP Control register 0 */
1347 #define ICCR1 0x04 /* FICP Control register 1 */
1348 #define ICCR2 0x08 /* FICP Control register 2 */
1349 #define ICDR 0x0c /* FICP Data register */
1350 #define ICSR0 0x14 /* FICP Status register 0 */
1351 #define ICSR1 0x18 /* FICP Status register 1 */
1352 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1354 static uint32_t pxa2xx_fir_read(void *opaque
, target_phys_addr_t addr
)
1356 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1362 return s
->control
[0];
1364 return s
->control
[1];
1366 return s
->control
[2];
1368 s
->status
[0] &= ~0x01;
1369 s
->status
[1] &= ~0x72;
1372 ret
= s
->rx_fifo
[s
->rx_start
++];
1374 pxa2xx_fir_update(s
);
1377 printf("%s: Rx FIFO underrun.\n", __FUNCTION__
);
1380 return s
->status
[0];
1382 return s
->status
[1] | (1 << 3); /* TNF */
1386 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1392 static void pxa2xx_fir_write(void *opaque
, target_phys_addr_t addr
,
1395 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1401 s
->control
[0] = value
;
1402 if (!(value
& (1 << 4))) /* RXE */
1403 s
->rx_len
= s
->rx_start
= 0;
1404 if (!(value
& (1 << 3))) /* TXE */
1406 s
->enable
= value
& 1; /* ITR */
1409 pxa2xx_fir_update(s
);
1412 s
->control
[1] = value
;
1415 s
->control
[2] = value
& 0x3f;
1416 pxa2xx_fir_update(s
);
1419 if (s
->control
[2] & (1 << 2)) /* TXP */
1423 if (s
->chr
&& s
->enable
&& (s
->control
[0] & (1 << 3))) /* TXE */
1424 qemu_chr_write(s
->chr
, &ch
, 1);
1427 s
->status
[0] &= ~(value
& 0x66);
1428 pxa2xx_fir_update(s
);
1433 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1437 static CPUReadMemoryFunc
*pxa2xx_fir_readfn
[] = {
1443 static CPUWriteMemoryFunc
*pxa2xx_fir_writefn
[] = {
1449 static int pxa2xx_fir_is_empty(void *opaque
)
1451 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1452 return (s
->rx_len
< 64);
1455 static void pxa2xx_fir_rx(void *opaque
, const uint8_t *buf
, int size
)
1457 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1458 if (!(s
->control
[0] & (1 << 4))) /* RXE */
1462 s
->status
[1] |= 1 << 4; /* EOF */
1463 if (s
->rx_len
>= 64) {
1464 s
->status
[1] |= 1 << 6; /* ROR */
1468 if (s
->control
[2] & (1 << 3)) /* RXP */
1469 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = *(buf
++);
1471 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = ~*(buf
++);
1474 pxa2xx_fir_update(s
);
1477 static void pxa2xx_fir_event(void *opaque
, int event
)
1481 static struct pxa2xx_fir_s
*pxa2xx_fir_init(target_phys_addr_t base
,
1482 qemu_irq irq
, struct pxa2xx_dma_state_s
*dma
,
1483 CharDriverState
*chr
)
1486 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*)
1487 qemu_mallocz(sizeof(struct pxa2xx_fir_s
));
1494 pxa2xx_fir_reset(s
);
1496 iomemtype
= cpu_register_io_memory(0, pxa2xx_fir_readfn
,
1497 pxa2xx_fir_writefn
, s
);
1498 cpu_register_physical_memory(s
->base
, 0xfff, iomemtype
);
1501 qemu_chr_add_handlers(chr
, pxa2xx_fir_is_empty
,
1502 pxa2xx_fir_rx
, pxa2xx_fir_event
, s
);
1507 void pxa2xx_reset(int line
, int level
, void *opaque
)
1509 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1510 if (level
&& (s
->pm_regs
[PCFR
>> 2] & 0x10)) { /* GPR_EN */
1512 /* TODO: reset peripherals */
1516 /* Initialise a PXA270 integrated chip (ARM based core). */
1517 struct pxa2xx_state_s
*pxa270_init(DisplayState
*ds
, const char *revision
)
1519 struct pxa2xx_state_s
*s
;
1520 struct pxa2xx_ssp_s
*ssp
;
1523 s
= (struct pxa2xx_state_s
*) qemu_mallocz(sizeof(struct pxa2xx_state_s
));
1525 s
->env
= cpu_init();
1526 asprintf(&cpu_model
, "pxa270-%s", revision
);
1527 cpu_arm_set_model(s
->env
, cpu_model
);
1530 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->env
);
1532 s
->dma
= pxa27x_dma_init(0x40000000, s
->pic
[PXA2XX_PIC_DMA
]);
1534 pxa27x_timer_init(0x40a00000, &s
->pic
[PXA2XX_PIC_OST_0
],
1535 s
->pic
[PXA27X_PIC_OST_4_11
], s
->env
);
1537 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->env
, s
->pic
, 121);
1539 s
->mmc
= pxa2xx_mmci_init(0x41100000, s
->pic
[PXA2XX_PIC_MMC
], s
->dma
);
1541 for (i
= 0; pxa270_serial
[i
].io_base
; i
++)
1543 serial_mm_init(pxa270_serial
[i
].io_base
, 2,
1544 s
->pic
[pxa270_serial
[i
].irqn
], serial_hds
[i
], 1);
1548 s
->fir
= pxa2xx_fir_init(0x40800000, s
->pic
[PXA2XX_PIC_ICP
],
1549 s
->dma
, serial_hds
[i
]);
1552 s
->lcd
= pxa2xx_lcdc_init(0x44000000, s
->pic
[PXA2XX_PIC_LCD
], ds
);
1554 s
->cm_base
= 0x41300000;
1555 s
->cm_regs
[CCCR
>> 4] = 0x02000210; /* 416.0 MHz */
1556 s
->clkcfg
= 0x00000009; /* Turbo mode active */
1557 iomemtype
= cpu_register_io_memory(0, pxa2xx_cm_readfn
,
1558 pxa2xx_cm_writefn
, s
);
1559 cpu_register_physical_memory(s
->cm_base
, 0xfff, iomemtype
);
1561 cpu_arm_set_cp_io(s
->env
, 14, pxa2xx_cp14_read
, pxa2xx_cp14_write
, s
);
1563 s
->mm_base
= 0x48000000;
1564 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
1565 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
1566 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
1567 iomemtype
= cpu_register_io_memory(0, pxa2xx_mm_readfn
,
1568 pxa2xx_mm_writefn
, s
);
1569 cpu_register_physical_memory(s
->mm_base
, 0xfff, iomemtype
);
1571 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++);
1572 s
->ssp
= (struct pxa2xx_ssp_s
**)
1573 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
*) * i
);
1574 ssp
= (struct pxa2xx_ssp_s
*)
1575 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
) * i
);
1576 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++) {
1577 s
->ssp
[i
] = &ssp
[i
];
1578 ssp
[i
].base
= pxa27x_ssp
[i
].io_base
;
1579 ssp
[i
].irq
= s
->pic
[pxa27x_ssp
[i
].irqn
];
1581 iomemtype
= cpu_register_io_memory(0, pxa2xx_ssp_readfn
,
1582 pxa2xx_ssp_writefn
, &ssp
[i
]);
1583 cpu_register_physical_memory(ssp
[i
].base
, 0xfff, iomemtype
);
1587 usb_ohci_init_pxa(0x4c000000, 3, -1, s
->pic
[PXA2XX_PIC_USBH1
]);
1590 s
->pcmcia
[0] = pxa2xx_pcmcia_init(0x20000000);
1591 s
->pcmcia
[1] = pxa2xx_pcmcia_init(0x30000000);
1593 s
->rtc_base
= 0x40900000;
1594 iomemtype
= cpu_register_io_memory(0, pxa2xx_rtc_readfn
,
1595 pxa2xx_rtc_writefn
, s
);
1596 cpu_register_physical_memory(s
->rtc_base
, 0xfff, iomemtype
);
1597 pxa2xx_rtc_reset(s
);
1599 s
->pm_base
= 0x40f00000;
1600 iomemtype
= cpu_register_io_memory(0, pxa2xx_pm_readfn
,
1601 pxa2xx_pm_writefn
, s
);
1602 cpu_register_physical_memory(s
->pm_base
, 0xfff, iomemtype
);
1604 s
->i2s
= pxa2xx_i2s_init(0x40400000, s
->pic
[PXA2XX_PIC_I2S
], s
->dma
);
1606 /* GPIO1 resets the processor */
1607 /* The handler can be overriden by board-specific code */
1608 pxa2xx_gpio_handler_set(s
->gpio
, 1, pxa2xx_reset
, s
);
1612 /* Initialise a PXA255 integrated chip (ARM based core). */
1613 struct pxa2xx_state_s
*pxa255_init(DisplayState
*ds
)
1615 struct pxa2xx_state_s
*s
;
1616 struct pxa2xx_ssp_s
*ssp
;
1618 s
= (struct pxa2xx_state_s
*) qemu_mallocz(sizeof(struct pxa2xx_state_s
));
1620 s
->env
= cpu_init();
1621 cpu_arm_set_model(s
->env
, "pxa255");
1623 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->env
);
1625 s
->dma
= pxa255_dma_init(0x40000000, s
->pic
[PXA2XX_PIC_DMA
]);
1627 pxa25x_timer_init(0x40a00000, &s
->pic
[PXA2XX_PIC_OST_0
], s
->env
);
1629 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->env
, s
->pic
, 121);
1631 s
->mmc
= pxa2xx_mmci_init(0x41100000, s
->pic
[PXA2XX_PIC_MMC
], s
->dma
);
1633 for (i
= 0; pxa255_serial
[i
].io_base
; i
++)
1635 serial_mm_init(pxa255_serial
[i
].io_base
, 2,
1636 s
->pic
[pxa255_serial
[i
].irqn
], serial_hds
[i
], 1);
1640 s
->fir
= pxa2xx_fir_init(0x40800000, s
->pic
[PXA2XX_PIC_ICP
],
1641 s
->dma
, serial_hds
[i
]);
1644 s
->lcd
= pxa2xx_lcdc_init(0x44000000, s
->pic
[PXA2XX_PIC_LCD
], ds
);
1646 s
->cm_base
= 0x41300000;
1647 s
->cm_regs
[CCCR
>> 4] = 0x02000210; /* 416.0 MHz */
1648 s
->clkcfg
= 0x00000009; /* Turbo mode active */
1649 iomemtype
= cpu_register_io_memory(0, pxa2xx_cm_readfn
,
1650 pxa2xx_cm_writefn
, s
);
1651 cpu_register_physical_memory(s
->cm_base
, 0xfff, iomemtype
);
1653 cpu_arm_set_cp_io(s
->env
, 14, pxa2xx_cp14_read
, pxa2xx_cp14_write
, s
);
1655 s
->mm_base
= 0x48000000;
1656 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
1657 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
1658 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
1659 iomemtype
= cpu_register_io_memory(0, pxa2xx_mm_readfn
,
1660 pxa2xx_mm_writefn
, s
);
1661 cpu_register_physical_memory(s
->mm_base
, 0xfff, iomemtype
);
1663 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++);
1664 s
->ssp
= (struct pxa2xx_ssp_s
**)
1665 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
*) * i
);
1666 ssp
= (struct pxa2xx_ssp_s
*)
1667 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
) * i
);
1668 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++) {
1669 s
->ssp
[i
] = &ssp
[i
];
1670 ssp
[i
].base
= pxa255_ssp
[i
].io_base
;
1671 ssp
[i
].irq
= s
->pic
[pxa255_ssp
[i
].irqn
];
1673 iomemtype
= cpu_register_io_memory(0, pxa2xx_ssp_readfn
,
1674 pxa2xx_ssp_writefn
, &ssp
[i
]);
1675 cpu_register_physical_memory(ssp
[i
].base
, 0xfff, iomemtype
);
1679 usb_ohci_init_pxa(0x4c000000, 3, -1, s
->pic
[PXA2XX_PIC_USBH1
]);
1682 s
->pcmcia
[0] = pxa2xx_pcmcia_init(0x20000000);
1683 s
->pcmcia
[1] = pxa2xx_pcmcia_init(0x30000000);
1685 s
->rtc_base
= 0x40900000;
1686 iomemtype
= cpu_register_io_memory(0, pxa2xx_rtc_readfn
,
1687 pxa2xx_rtc_writefn
, s
);
1688 cpu_register_physical_memory(s
->rtc_base
, 0xfff, iomemtype
);
1689 pxa2xx_rtc_reset(s
);
1691 s
->pm_base
= 0x40f00000;
1692 iomemtype
= cpu_register_io_memory(0, pxa2xx_pm_readfn
,
1693 pxa2xx_pm_writefn
, s
);
1694 cpu_register_physical_memory(s
->pm_base
, 0xfff, iomemtype
);
1696 s
->i2s
= pxa2xx_i2s_init(0x40400000, s
->pic
[PXA2XX_PIC_I2S
], s
->dma
);
1698 /* GPIO1 resets the processor */
1699 /* The handler can be overriden by board-specific code */
1700 pxa2xx_gpio_handler_set(s
->gpio
, 1, pxa2xx_reset
, s
);