]> git.proxmox.com Git - mirror_qemu.git/blob - hw/pxa2xx.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
serial: Add MemoryRegion parameter to serial_mm_init
[mirror_qemu.git] / hw / pxa2xx.c
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "sysbus.h"
11 #include "pxa.h"
12 #include "sysemu.h"
13 #include "pc.h"
14 #include "i2c.h"
15 #include "ssi.h"
16 #include "qemu-char.h"
17 #include "blockdev.h"
18 #include "exec-memory.h"
19
20 static struct {
21 target_phys_addr_t io_base;
22 int irqn;
23 } pxa255_serial[] = {
24 { 0x40100000, PXA2XX_PIC_FFUART },
25 { 0x40200000, PXA2XX_PIC_BTUART },
26 { 0x40700000, PXA2XX_PIC_STUART },
27 { 0x41600000, PXA25X_PIC_HWUART },
28 { 0, 0 }
29 }, pxa270_serial[] = {
30 { 0x40100000, PXA2XX_PIC_FFUART },
31 { 0x40200000, PXA2XX_PIC_BTUART },
32 { 0x40700000, PXA2XX_PIC_STUART },
33 { 0, 0 }
34 };
35
36 typedef struct PXASSPDef {
37 target_phys_addr_t io_base;
38 int irqn;
39 } PXASSPDef;
40
41 #if 0
42 static PXASSPDef pxa250_ssp[] = {
43 { 0x41000000, PXA2XX_PIC_SSP },
44 { 0, 0 }
45 };
46 #endif
47
48 static PXASSPDef pxa255_ssp[] = {
49 { 0x41000000, PXA2XX_PIC_SSP },
50 { 0x41400000, PXA25X_PIC_NSSP },
51 { 0, 0 }
52 };
53
54 #if 0
55 static PXASSPDef pxa26x_ssp[] = {
56 { 0x41000000, PXA2XX_PIC_SSP },
57 { 0x41400000, PXA25X_PIC_NSSP },
58 { 0x41500000, PXA26X_PIC_ASSP },
59 { 0, 0 }
60 };
61 #endif
62
63 static PXASSPDef pxa27x_ssp[] = {
64 { 0x41000000, PXA2XX_PIC_SSP },
65 { 0x41700000, PXA27X_PIC_SSP2 },
66 { 0x41900000, PXA2XX_PIC_SSP3 },
67 { 0, 0 }
68 };
69
70 #define PMCR 0x00 /* Power Manager Control register */
71 #define PSSR 0x04 /* Power Manager Sleep Status register */
72 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
73 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
74 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
75 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
76 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
77 #define PCFR 0x1c /* Power Manager General Configuration register */
78 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
79 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
80 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
81 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
82 #define RCSR 0x30 /* Reset Controller Status register */
83 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
84 #define PTSR 0x38 /* Power Manager Standby Configuration register */
85 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
86 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
87 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
88 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
89 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
90 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
91
92 static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
93 {
94 PXA2xxState *s = (PXA2xxState *) opaque;
95
96 switch (addr) {
97 case PMCR ... PCMD31:
98 if (addr & 3)
99 goto fail;
100
101 return s->pm_regs[addr >> 2];
102 default:
103 fail:
104 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
105 break;
106 }
107 return 0;
108 }
109
110 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
111 uint32_t value)
112 {
113 PXA2xxState *s = (PXA2xxState *) opaque;
114
115 switch (addr) {
116 case PMCR:
117 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
118 s->pm_regs[addr >> 2] |= value & 0x15;
119 break;
120
121 case PSSR: /* Read-clean registers */
122 case RCSR:
123 case PKSR:
124 s->pm_regs[addr >> 2] &= ~value;
125 break;
126
127 default: /* Read-write registers */
128 if (!(addr & 3)) {
129 s->pm_regs[addr >> 2] = value;
130 break;
131 }
132
133 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
134 break;
135 }
136 }
137
138 static CPUReadMemoryFunc * const pxa2xx_pm_readfn[] = {
139 pxa2xx_pm_read,
140 pxa2xx_pm_read,
141 pxa2xx_pm_read,
142 };
143
144 static CPUWriteMemoryFunc * const pxa2xx_pm_writefn[] = {
145 pxa2xx_pm_write,
146 pxa2xx_pm_write,
147 pxa2xx_pm_write,
148 };
149
150 static const VMStateDescription vmstate_pxa2xx_pm = {
151 .name = "pxa2xx_pm",
152 .version_id = 0,
153 .minimum_version_id = 0,
154 .minimum_version_id_old = 0,
155 .fields = (VMStateField[]) {
156 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
157 VMSTATE_END_OF_LIST()
158 }
159 };
160
161 #define CCCR 0x00 /* Core Clock Configuration register */
162 #define CKEN 0x04 /* Clock Enable register */
163 #define OSCC 0x08 /* Oscillator Configuration register */
164 #define CCSR 0x0c /* Core Clock Status register */
165
166 static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
167 {
168 PXA2xxState *s = (PXA2xxState *) opaque;
169
170 switch (addr) {
171 case CCCR:
172 case CKEN:
173 case OSCC:
174 return s->cm_regs[addr >> 2];
175
176 case CCSR:
177 return s->cm_regs[CCCR >> 2] | (3 << 28);
178
179 default:
180 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
181 break;
182 }
183 return 0;
184 }
185
186 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
187 uint32_t value)
188 {
189 PXA2xxState *s = (PXA2xxState *) opaque;
190
191 switch (addr) {
192 case CCCR:
193 case CKEN:
194 s->cm_regs[addr >> 2] = value;
195 break;
196
197 case OSCC:
198 s->cm_regs[addr >> 2] &= ~0x6c;
199 s->cm_regs[addr >> 2] |= value & 0x6e;
200 if ((value >> 1) & 1) /* OON */
201 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
202 break;
203
204 default:
205 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
206 break;
207 }
208 }
209
210 static CPUReadMemoryFunc * const pxa2xx_cm_readfn[] = {
211 pxa2xx_cm_read,
212 pxa2xx_cm_read,
213 pxa2xx_cm_read,
214 };
215
216 static CPUWriteMemoryFunc * const pxa2xx_cm_writefn[] = {
217 pxa2xx_cm_write,
218 pxa2xx_cm_write,
219 pxa2xx_cm_write,
220 };
221
222 static const VMStateDescription vmstate_pxa2xx_cm = {
223 .name = "pxa2xx_cm",
224 .version_id = 0,
225 .minimum_version_id = 0,
226 .minimum_version_id_old = 0,
227 .fields = (VMStateField[]) {
228 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
229 VMSTATE_UINT32(clkcfg, PXA2xxState),
230 VMSTATE_UINT32(pmnc, PXA2xxState),
231 VMSTATE_END_OF_LIST()
232 }
233 };
234
235 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
236 {
237 PXA2xxState *s = (PXA2xxState *) opaque;
238
239 switch (reg) {
240 case 6: /* Clock Configuration register */
241 return s->clkcfg;
242
243 case 7: /* Power Mode register */
244 return 0;
245
246 default:
247 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
248 break;
249 }
250 return 0;
251 }
252
253 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
254 uint32_t value)
255 {
256 PXA2xxState *s = (PXA2xxState *) opaque;
257 static const char *pwrmode[8] = {
258 "Normal", "Idle", "Deep-idle", "Standby",
259 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
260 };
261
262 switch (reg) {
263 case 6: /* Clock Configuration register */
264 s->clkcfg = value & 0xf;
265 if (value & 2)
266 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
267 break;
268
269 case 7: /* Power Mode register */
270 if (value & 8)
271 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
272 switch (value & 7) {
273 case 0:
274 /* Do nothing */
275 break;
276
277 case 1:
278 /* Idle */
279 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
280 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
281 break;
282 }
283 /* Fall through. */
284
285 case 2:
286 /* Deep-Idle */
287 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
288 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
289 goto message;
290
291 case 3:
292 s->env->uncached_cpsr =
293 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
294 s->env->cp15.c1_sys = 0;
295 s->env->cp15.c1_coproc = 0;
296 s->env->cp15.c2_base0 = 0;
297 s->env->cp15.c3 = 0;
298 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
299 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
300
301 /*
302 * The scratch-pad register is almost universally used
303 * for storing the return address on suspend. For the
304 * lack of a resuming bootloader, perform a jump
305 * directly to that address.
306 */
307 memset(s->env->regs, 0, 4 * 15);
308 s->env->regs[15] = s->pm_regs[PSPR >> 2];
309
310 #if 0
311 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
312 cpu_physical_memory_write(0, &buffer, 4);
313 buffer = s->pm_regs[PSPR >> 2];
314 cpu_physical_memory_write(8, &buffer, 4);
315 #endif
316
317 /* Suspend */
318 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
319
320 goto message;
321
322 default:
323 message:
324 printf("%s: machine entered %s mode\n", __FUNCTION__,
325 pwrmode[value & 7]);
326 }
327 break;
328
329 default:
330 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
331 break;
332 }
333 }
334
335 /* Performace Monitoring Registers */
336 #define CPPMNC 0 /* Performance Monitor Control register */
337 #define CPCCNT 1 /* Clock Counter register */
338 #define CPINTEN 4 /* Interrupt Enable register */
339 #define CPFLAG 5 /* Overflow Flag register */
340 #define CPEVTSEL 8 /* Event Selection register */
341
342 #define CPPMN0 0 /* Performance Count register 0 */
343 #define CPPMN1 1 /* Performance Count register 1 */
344 #define CPPMN2 2 /* Performance Count register 2 */
345 #define CPPMN3 3 /* Performance Count register 3 */
346
347 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
348 {
349 PXA2xxState *s = (PXA2xxState *) opaque;
350
351 switch (reg) {
352 case CPPMNC:
353 return s->pmnc;
354 case CPCCNT:
355 if (s->pmnc & 1)
356 return qemu_get_clock_ns(vm_clock);
357 else
358 return 0;
359 case CPINTEN:
360 case CPFLAG:
361 case CPEVTSEL:
362 return 0;
363
364 default:
365 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
366 break;
367 }
368 return 0;
369 }
370
371 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
372 uint32_t value)
373 {
374 PXA2xxState *s = (PXA2xxState *) opaque;
375
376 switch (reg) {
377 case CPPMNC:
378 s->pmnc = value;
379 break;
380
381 case CPCCNT:
382 case CPINTEN:
383 case CPFLAG:
384 case CPEVTSEL:
385 break;
386
387 default:
388 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
389 break;
390 }
391 }
392
393 static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
394 {
395 switch (crm) {
396 case 0:
397 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
398 case 1:
399 return pxa2xx_perf_read(opaque, op2, reg, crm);
400 case 2:
401 switch (reg) {
402 case CPPMN0:
403 case CPPMN1:
404 case CPPMN2:
405 case CPPMN3:
406 return 0;
407 }
408 /* Fall through */
409 default:
410 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
411 break;
412 }
413 return 0;
414 }
415
416 static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
417 uint32_t value)
418 {
419 switch (crm) {
420 case 0:
421 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
422 break;
423 case 1:
424 pxa2xx_perf_write(opaque, op2, reg, crm, value);
425 break;
426 case 2:
427 switch (reg) {
428 case CPPMN0:
429 case CPPMN1:
430 case CPPMN2:
431 case CPPMN3:
432 return;
433 }
434 /* Fall through */
435 default:
436 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
437 break;
438 }
439 }
440
441 #define MDCNFG 0x00 /* SDRAM Configuration register */
442 #define MDREFR 0x04 /* SDRAM Refresh Control register */
443 #define MSC0 0x08 /* Static Memory Control register 0 */
444 #define MSC1 0x0c /* Static Memory Control register 1 */
445 #define MSC2 0x10 /* Static Memory Control register 2 */
446 #define MECR 0x14 /* Expansion Memory Bus Config register */
447 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
448 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
449 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
450 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
451 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
452 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
453 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
454 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
455 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
456 #define ARB_CNTL 0x48 /* Arbiter Control register */
457 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
458 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
459 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
460 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
461 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
462 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
463 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
464
465 static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
466 {
467 PXA2xxState *s = (PXA2xxState *) opaque;
468
469 switch (addr) {
470 case MDCNFG ... SA1110:
471 if ((addr & 3) == 0)
472 return s->mm_regs[addr >> 2];
473
474 default:
475 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
476 break;
477 }
478 return 0;
479 }
480
481 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
482 uint32_t value)
483 {
484 PXA2xxState *s = (PXA2xxState *) opaque;
485
486 switch (addr) {
487 case MDCNFG ... SA1110:
488 if ((addr & 3) == 0) {
489 s->mm_regs[addr >> 2] = value;
490 break;
491 }
492
493 default:
494 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
495 break;
496 }
497 }
498
499 static CPUReadMemoryFunc * const pxa2xx_mm_readfn[] = {
500 pxa2xx_mm_read,
501 pxa2xx_mm_read,
502 pxa2xx_mm_read,
503 };
504
505 static CPUWriteMemoryFunc * const pxa2xx_mm_writefn[] = {
506 pxa2xx_mm_write,
507 pxa2xx_mm_write,
508 pxa2xx_mm_write,
509 };
510
511 static const VMStateDescription vmstate_pxa2xx_mm = {
512 .name = "pxa2xx_mm",
513 .version_id = 0,
514 .minimum_version_id = 0,
515 .minimum_version_id_old = 0,
516 .fields = (VMStateField[]) {
517 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
518 VMSTATE_END_OF_LIST()
519 }
520 };
521
522 /* Synchronous Serial Ports */
523 typedef struct {
524 SysBusDevice busdev;
525 qemu_irq irq;
526 int enable;
527 SSIBus *bus;
528
529 uint32_t sscr[2];
530 uint32_t sspsp;
531 uint32_t ssto;
532 uint32_t ssitr;
533 uint32_t sssr;
534 uint8_t sstsa;
535 uint8_t ssrsa;
536 uint8_t ssacd;
537
538 uint32_t rx_fifo[16];
539 int rx_level;
540 int rx_start;
541 } PXA2xxSSPState;
542
543 #define SSCR0 0x00 /* SSP Control register 0 */
544 #define SSCR1 0x04 /* SSP Control register 1 */
545 #define SSSR 0x08 /* SSP Status register */
546 #define SSITR 0x0c /* SSP Interrupt Test register */
547 #define SSDR 0x10 /* SSP Data register */
548 #define SSTO 0x28 /* SSP Time-Out register */
549 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
550 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
551 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
552 #define SSTSS 0x38 /* SSP Time Slot Status register */
553 #define SSACD 0x3c /* SSP Audio Clock Divider register */
554
555 /* Bitfields for above registers */
556 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
557 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
558 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
559 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
560 #define SSCR0_SSE (1 << 7)
561 #define SSCR0_RIM (1 << 22)
562 #define SSCR0_TIM (1 << 23)
563 #define SSCR0_MOD (1 << 31)
564 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
565 #define SSCR1_RIE (1 << 0)
566 #define SSCR1_TIE (1 << 1)
567 #define SSCR1_LBM (1 << 2)
568 #define SSCR1_MWDS (1 << 5)
569 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
570 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
571 #define SSCR1_EFWR (1 << 14)
572 #define SSCR1_PINTE (1 << 18)
573 #define SSCR1_TINTE (1 << 19)
574 #define SSCR1_RSRE (1 << 20)
575 #define SSCR1_TSRE (1 << 21)
576 #define SSCR1_EBCEI (1 << 29)
577 #define SSITR_INT (7 << 5)
578 #define SSSR_TNF (1 << 2)
579 #define SSSR_RNE (1 << 3)
580 #define SSSR_TFS (1 << 5)
581 #define SSSR_RFS (1 << 6)
582 #define SSSR_ROR (1 << 7)
583 #define SSSR_PINT (1 << 18)
584 #define SSSR_TINT (1 << 19)
585 #define SSSR_EOC (1 << 20)
586 #define SSSR_TUR (1 << 21)
587 #define SSSR_BCE (1 << 23)
588 #define SSSR_RW 0x00bc0080
589
590 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
591 {
592 int level = 0;
593
594 level |= s->ssitr & SSITR_INT;
595 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
596 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
597 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
598 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
599 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
600 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
601 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
602 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
603 qemu_set_irq(s->irq, !!level);
604 }
605
606 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
607 {
608 s->sssr &= ~(0xf << 12); /* Clear RFL */
609 s->sssr &= ~(0xf << 8); /* Clear TFL */
610 s->sssr &= ~SSSR_TFS;
611 s->sssr &= ~SSSR_TNF;
612 if (s->enable) {
613 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
614 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
615 s->sssr |= SSSR_RFS;
616 else
617 s->sssr &= ~SSSR_RFS;
618 if (s->rx_level)
619 s->sssr |= SSSR_RNE;
620 else
621 s->sssr &= ~SSSR_RNE;
622 /* TX FIFO is never filled, so it is always in underrun
623 condition if SSP is enabled */
624 s->sssr |= SSSR_TFS;
625 s->sssr |= SSSR_TNF;
626 }
627
628 pxa2xx_ssp_int_update(s);
629 }
630
631 static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
632 {
633 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
634 uint32_t retval;
635
636 switch (addr) {
637 case SSCR0:
638 return s->sscr[0];
639 case SSCR1:
640 return s->sscr[1];
641 case SSPSP:
642 return s->sspsp;
643 case SSTO:
644 return s->ssto;
645 case SSITR:
646 return s->ssitr;
647 case SSSR:
648 return s->sssr | s->ssitr;
649 case SSDR:
650 if (!s->enable)
651 return 0xffffffff;
652 if (s->rx_level < 1) {
653 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
654 return 0xffffffff;
655 }
656 s->rx_level --;
657 retval = s->rx_fifo[s->rx_start ++];
658 s->rx_start &= 0xf;
659 pxa2xx_ssp_fifo_update(s);
660 return retval;
661 case SSTSA:
662 return s->sstsa;
663 case SSRSA:
664 return s->ssrsa;
665 case SSTSS:
666 return 0;
667 case SSACD:
668 return s->ssacd;
669 default:
670 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
671 break;
672 }
673 return 0;
674 }
675
676 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
677 uint32_t value)
678 {
679 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
680
681 switch (addr) {
682 case SSCR0:
683 s->sscr[0] = value & 0xc7ffffff;
684 s->enable = value & SSCR0_SSE;
685 if (value & SSCR0_MOD)
686 printf("%s: Attempt to use network mode\n", __FUNCTION__);
687 if (s->enable && SSCR0_DSS(value) < 4)
688 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
689 SSCR0_DSS(value));
690 if (!(value & SSCR0_SSE)) {
691 s->sssr = 0;
692 s->ssitr = 0;
693 s->rx_level = 0;
694 }
695 pxa2xx_ssp_fifo_update(s);
696 break;
697
698 case SSCR1:
699 s->sscr[1] = value;
700 if (value & (SSCR1_LBM | SSCR1_EFWR))
701 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
702 pxa2xx_ssp_fifo_update(s);
703 break;
704
705 case SSPSP:
706 s->sspsp = value;
707 break;
708
709 case SSTO:
710 s->ssto = value;
711 break;
712
713 case SSITR:
714 s->ssitr = value & SSITR_INT;
715 pxa2xx_ssp_int_update(s);
716 break;
717
718 case SSSR:
719 s->sssr &= ~(value & SSSR_RW);
720 pxa2xx_ssp_int_update(s);
721 break;
722
723 case SSDR:
724 if (SSCR0_UWIRE(s->sscr[0])) {
725 if (s->sscr[1] & SSCR1_MWDS)
726 value &= 0xffff;
727 else
728 value &= 0xff;
729 } else
730 /* Note how 32bits overflow does no harm here */
731 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
732
733 /* Data goes from here to the Tx FIFO and is shifted out from
734 * there directly to the slave, no need to buffer it.
735 */
736 if (s->enable) {
737 uint32_t readval;
738 readval = ssi_transfer(s->bus, value);
739 if (s->rx_level < 0x10) {
740 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
741 } else {
742 s->sssr |= SSSR_ROR;
743 }
744 }
745 pxa2xx_ssp_fifo_update(s);
746 break;
747
748 case SSTSA:
749 s->sstsa = value;
750 break;
751
752 case SSRSA:
753 s->ssrsa = value;
754 break;
755
756 case SSACD:
757 s->ssacd = value;
758 break;
759
760 default:
761 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
762 break;
763 }
764 }
765
766 static CPUReadMemoryFunc * const pxa2xx_ssp_readfn[] = {
767 pxa2xx_ssp_read,
768 pxa2xx_ssp_read,
769 pxa2xx_ssp_read,
770 };
771
772 static CPUWriteMemoryFunc * const pxa2xx_ssp_writefn[] = {
773 pxa2xx_ssp_write,
774 pxa2xx_ssp_write,
775 pxa2xx_ssp_write,
776 };
777
778 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
779 {
780 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
781 int i;
782
783 qemu_put_be32(f, s->enable);
784
785 qemu_put_be32s(f, &s->sscr[0]);
786 qemu_put_be32s(f, &s->sscr[1]);
787 qemu_put_be32s(f, &s->sspsp);
788 qemu_put_be32s(f, &s->ssto);
789 qemu_put_be32s(f, &s->ssitr);
790 qemu_put_be32s(f, &s->sssr);
791 qemu_put_8s(f, &s->sstsa);
792 qemu_put_8s(f, &s->ssrsa);
793 qemu_put_8s(f, &s->ssacd);
794
795 qemu_put_byte(f, s->rx_level);
796 for (i = 0; i < s->rx_level; i ++)
797 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
798 }
799
800 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
801 {
802 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
803 int i;
804
805 s->enable = qemu_get_be32(f);
806
807 qemu_get_be32s(f, &s->sscr[0]);
808 qemu_get_be32s(f, &s->sscr[1]);
809 qemu_get_be32s(f, &s->sspsp);
810 qemu_get_be32s(f, &s->ssto);
811 qemu_get_be32s(f, &s->ssitr);
812 qemu_get_be32s(f, &s->sssr);
813 qemu_get_8s(f, &s->sstsa);
814 qemu_get_8s(f, &s->ssrsa);
815 qemu_get_8s(f, &s->ssacd);
816
817 s->rx_level = qemu_get_byte(f);
818 s->rx_start = 0;
819 for (i = 0; i < s->rx_level; i ++)
820 s->rx_fifo[i] = qemu_get_byte(f);
821
822 return 0;
823 }
824
825 static int pxa2xx_ssp_init(SysBusDevice *dev)
826 {
827 int iomemtype;
828 PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);
829
830 sysbus_init_irq(dev, &s->irq);
831
832 iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,
833 pxa2xx_ssp_writefn, s,
834 DEVICE_NATIVE_ENDIAN);
835 sysbus_init_mmio(dev, 0x1000, iomemtype);
836 register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
837 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
838
839 s->bus = ssi_create_bus(&dev->qdev, "ssi");
840 return 0;
841 }
842
843 /* Real-Time Clock */
844 #define RCNR 0x00 /* RTC Counter register */
845 #define RTAR 0x04 /* RTC Alarm register */
846 #define RTSR 0x08 /* RTC Status register */
847 #define RTTR 0x0c /* RTC Timer Trim register */
848 #define RDCR 0x10 /* RTC Day Counter register */
849 #define RYCR 0x14 /* RTC Year Counter register */
850 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
851 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
852 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
853 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
854 #define SWCR 0x28 /* RTC Stopwatch Counter register */
855 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
856 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
857 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
858 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
859
860 typedef struct {
861 SysBusDevice busdev;
862 uint32_t rttr;
863 uint32_t rtsr;
864 uint32_t rtar;
865 uint32_t rdar1;
866 uint32_t rdar2;
867 uint32_t ryar1;
868 uint32_t ryar2;
869 uint32_t swar1;
870 uint32_t swar2;
871 uint32_t piar;
872 uint32_t last_rcnr;
873 uint32_t last_rdcr;
874 uint32_t last_rycr;
875 uint32_t last_swcr;
876 uint32_t last_rtcpicr;
877 int64_t last_hz;
878 int64_t last_sw;
879 int64_t last_pi;
880 QEMUTimer *rtc_hz;
881 QEMUTimer *rtc_rdal1;
882 QEMUTimer *rtc_rdal2;
883 QEMUTimer *rtc_swal1;
884 QEMUTimer *rtc_swal2;
885 QEMUTimer *rtc_pi;
886 qemu_irq rtc_irq;
887 } PXA2xxRTCState;
888
889 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
890 {
891 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
892 }
893
894 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
895 {
896 int64_t rt = qemu_get_clock_ms(rt_clock);
897 s->last_rcnr += ((rt - s->last_hz) << 15) /
898 (1000 * ((s->rttr & 0xffff) + 1));
899 s->last_rdcr += ((rt - s->last_hz) << 15) /
900 (1000 * ((s->rttr & 0xffff) + 1));
901 s->last_hz = rt;
902 }
903
904 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
905 {
906 int64_t rt = qemu_get_clock_ms(rt_clock);
907 if (s->rtsr & (1 << 12))
908 s->last_swcr += (rt - s->last_sw) / 10;
909 s->last_sw = rt;
910 }
911
912 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
913 {
914 int64_t rt = qemu_get_clock_ms(rt_clock);
915 if (s->rtsr & (1 << 15))
916 s->last_swcr += rt - s->last_pi;
917 s->last_pi = rt;
918 }
919
920 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
921 uint32_t rtsr)
922 {
923 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
924 qemu_mod_timer(s->rtc_hz, s->last_hz +
925 (((s->rtar - s->last_rcnr) * 1000 *
926 ((s->rttr & 0xffff) + 1)) >> 15));
927 else
928 qemu_del_timer(s->rtc_hz);
929
930 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
931 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
932 (((s->rdar1 - s->last_rdcr) * 1000 *
933 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
934 else
935 qemu_del_timer(s->rtc_rdal1);
936
937 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
938 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
939 (((s->rdar2 - s->last_rdcr) * 1000 *
940 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
941 else
942 qemu_del_timer(s->rtc_rdal2);
943
944 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
945 qemu_mod_timer(s->rtc_swal1, s->last_sw +
946 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
947 else
948 qemu_del_timer(s->rtc_swal1);
949
950 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
951 qemu_mod_timer(s->rtc_swal2, s->last_sw +
952 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
953 else
954 qemu_del_timer(s->rtc_swal2);
955
956 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
957 qemu_mod_timer(s->rtc_pi, s->last_pi +
958 (s->piar & 0xffff) - s->last_rtcpicr);
959 else
960 qemu_del_timer(s->rtc_pi);
961 }
962
963 static inline void pxa2xx_rtc_hz_tick(void *opaque)
964 {
965 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
966 s->rtsr |= (1 << 0);
967 pxa2xx_rtc_alarm_update(s, s->rtsr);
968 pxa2xx_rtc_int_update(s);
969 }
970
971 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
972 {
973 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
974 s->rtsr |= (1 << 4);
975 pxa2xx_rtc_alarm_update(s, s->rtsr);
976 pxa2xx_rtc_int_update(s);
977 }
978
979 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
980 {
981 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
982 s->rtsr |= (1 << 6);
983 pxa2xx_rtc_alarm_update(s, s->rtsr);
984 pxa2xx_rtc_int_update(s);
985 }
986
987 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
988 {
989 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
990 s->rtsr |= (1 << 8);
991 pxa2xx_rtc_alarm_update(s, s->rtsr);
992 pxa2xx_rtc_int_update(s);
993 }
994
995 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
996 {
997 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
998 s->rtsr |= (1 << 10);
999 pxa2xx_rtc_alarm_update(s, s->rtsr);
1000 pxa2xx_rtc_int_update(s);
1001 }
1002
1003 static inline void pxa2xx_rtc_pi_tick(void *opaque)
1004 {
1005 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1006 s->rtsr |= (1 << 13);
1007 pxa2xx_rtc_piupdate(s);
1008 s->last_rtcpicr = 0;
1009 pxa2xx_rtc_alarm_update(s, s->rtsr);
1010 pxa2xx_rtc_int_update(s);
1011 }
1012
1013 static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1014 {
1015 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1016
1017 switch (addr) {
1018 case RTTR:
1019 return s->rttr;
1020 case RTSR:
1021 return s->rtsr;
1022 case RTAR:
1023 return s->rtar;
1024 case RDAR1:
1025 return s->rdar1;
1026 case RDAR2:
1027 return s->rdar2;
1028 case RYAR1:
1029 return s->ryar1;
1030 case RYAR2:
1031 return s->ryar2;
1032 case SWAR1:
1033 return s->swar1;
1034 case SWAR2:
1035 return s->swar2;
1036 case PIAR:
1037 return s->piar;
1038 case RCNR:
1039 return s->last_rcnr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
1040 (1000 * ((s->rttr & 0xffff) + 1));
1041 case RDCR:
1042 return s->last_rdcr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
1043 (1000 * ((s->rttr & 0xffff) + 1));
1044 case RYCR:
1045 return s->last_rycr;
1046 case SWCR:
1047 if (s->rtsr & (1 << 12))
1048 return s->last_swcr + (qemu_get_clock_ms(rt_clock) - s->last_sw) / 10;
1049 else
1050 return s->last_swcr;
1051 default:
1052 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1053 break;
1054 }
1055 return 0;
1056 }
1057
1058 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1059 uint32_t value)
1060 {
1061 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1062
1063 switch (addr) {
1064 case RTTR:
1065 if (!(s->rttr & (1 << 31))) {
1066 pxa2xx_rtc_hzupdate(s);
1067 s->rttr = value;
1068 pxa2xx_rtc_alarm_update(s, s->rtsr);
1069 }
1070 break;
1071
1072 case RTSR:
1073 if ((s->rtsr ^ value) & (1 << 15))
1074 pxa2xx_rtc_piupdate(s);
1075
1076 if ((s->rtsr ^ value) & (1 << 12))
1077 pxa2xx_rtc_swupdate(s);
1078
1079 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1080 pxa2xx_rtc_alarm_update(s, value);
1081
1082 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1083 pxa2xx_rtc_int_update(s);
1084 break;
1085
1086 case RTAR:
1087 s->rtar = value;
1088 pxa2xx_rtc_alarm_update(s, s->rtsr);
1089 break;
1090
1091 case RDAR1:
1092 s->rdar1 = value;
1093 pxa2xx_rtc_alarm_update(s, s->rtsr);
1094 break;
1095
1096 case RDAR2:
1097 s->rdar2 = value;
1098 pxa2xx_rtc_alarm_update(s, s->rtsr);
1099 break;
1100
1101 case RYAR1:
1102 s->ryar1 = value;
1103 pxa2xx_rtc_alarm_update(s, s->rtsr);
1104 break;
1105
1106 case RYAR2:
1107 s->ryar2 = value;
1108 pxa2xx_rtc_alarm_update(s, s->rtsr);
1109 break;
1110
1111 case SWAR1:
1112 pxa2xx_rtc_swupdate(s);
1113 s->swar1 = value;
1114 s->last_swcr = 0;
1115 pxa2xx_rtc_alarm_update(s, s->rtsr);
1116 break;
1117
1118 case SWAR2:
1119 s->swar2 = value;
1120 pxa2xx_rtc_alarm_update(s, s->rtsr);
1121 break;
1122
1123 case PIAR:
1124 s->piar = value;
1125 pxa2xx_rtc_alarm_update(s, s->rtsr);
1126 break;
1127
1128 case RCNR:
1129 pxa2xx_rtc_hzupdate(s);
1130 s->last_rcnr = value;
1131 pxa2xx_rtc_alarm_update(s, s->rtsr);
1132 break;
1133
1134 case RDCR:
1135 pxa2xx_rtc_hzupdate(s);
1136 s->last_rdcr = value;
1137 pxa2xx_rtc_alarm_update(s, s->rtsr);
1138 break;
1139
1140 case RYCR:
1141 s->last_rycr = value;
1142 break;
1143
1144 case SWCR:
1145 pxa2xx_rtc_swupdate(s);
1146 s->last_swcr = value;
1147 pxa2xx_rtc_alarm_update(s, s->rtsr);
1148 break;
1149
1150 case RTCPICR:
1151 pxa2xx_rtc_piupdate(s);
1152 s->last_rtcpicr = value & 0xffff;
1153 pxa2xx_rtc_alarm_update(s, s->rtsr);
1154 break;
1155
1156 default:
1157 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1158 }
1159 }
1160
1161 static CPUReadMemoryFunc * const pxa2xx_rtc_readfn[] = {
1162 pxa2xx_rtc_read,
1163 pxa2xx_rtc_read,
1164 pxa2xx_rtc_read,
1165 };
1166
1167 static CPUWriteMemoryFunc * const pxa2xx_rtc_writefn[] = {
1168 pxa2xx_rtc_write,
1169 pxa2xx_rtc_write,
1170 pxa2xx_rtc_write,
1171 };
1172
1173 static int pxa2xx_rtc_init(SysBusDevice *dev)
1174 {
1175 PXA2xxRTCState *s = FROM_SYSBUS(PXA2xxRTCState, dev);
1176 struct tm tm;
1177 int wom;
1178 int iomemtype;
1179
1180 s->rttr = 0x7fff;
1181 s->rtsr = 0;
1182
1183 qemu_get_timedate(&tm, 0);
1184 wom = ((tm.tm_mday - 1) / 7) + 1;
1185
1186 s->last_rcnr = (uint32_t) mktimegm(&tm);
1187 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1188 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1189 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1190 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1191 s->last_swcr = (tm.tm_hour << 19) |
1192 (tm.tm_min << 13) | (tm.tm_sec << 7);
1193 s->last_rtcpicr = 0;
1194 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rt_clock);
1195
1196 s->rtc_hz = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_hz_tick, s);
1197 s->rtc_rdal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1198 s->rtc_rdal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1199 s->rtc_swal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal1_tick, s);
1200 s->rtc_swal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal2_tick, s);
1201 s->rtc_pi = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_pi_tick, s);
1202
1203 sysbus_init_irq(dev, &s->rtc_irq);
1204
1205 iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
1206 pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
1207 sysbus_init_mmio(dev, 0x10000, iomemtype);
1208
1209 return 0;
1210 }
1211
1212 static void pxa2xx_rtc_pre_save(void *opaque)
1213 {
1214 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1215
1216 pxa2xx_rtc_hzupdate(s);
1217 pxa2xx_rtc_piupdate(s);
1218 pxa2xx_rtc_swupdate(s);
1219 }
1220
1221 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1222 {
1223 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1224
1225 pxa2xx_rtc_alarm_update(s, s->rtsr);
1226
1227 return 0;
1228 }
1229
1230 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1231 .name = "pxa2xx_rtc",
1232 .version_id = 0,
1233 .minimum_version_id = 0,
1234 .minimum_version_id_old = 0,
1235 .pre_save = pxa2xx_rtc_pre_save,
1236 .post_load = pxa2xx_rtc_post_load,
1237 .fields = (VMStateField[]) {
1238 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1239 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1240 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1241 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1242 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1243 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1244 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1245 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1246 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1247 VMSTATE_UINT32(piar, PXA2xxRTCState),
1248 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1249 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1250 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1251 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1252 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1253 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1254 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1255 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1256 VMSTATE_END_OF_LIST(),
1257 },
1258 };
1259
1260 static SysBusDeviceInfo pxa2xx_rtc_sysbus_info = {
1261 .init = pxa2xx_rtc_init,
1262 .qdev.name = "pxa2xx_rtc",
1263 .qdev.desc = "PXA2xx RTC Controller",
1264 .qdev.size = sizeof(PXA2xxRTCState),
1265 .qdev.vmsd = &vmstate_pxa2xx_rtc_regs,
1266 };
1267
1268 /* I2C Interface */
1269 typedef struct {
1270 i2c_slave i2c;
1271 PXA2xxI2CState *host;
1272 } PXA2xxI2CSlaveState;
1273
1274 struct PXA2xxI2CState {
1275 SysBusDevice busdev;
1276 PXA2xxI2CSlaveState *slave;
1277 i2c_bus *bus;
1278 qemu_irq irq;
1279 uint32_t offset;
1280 uint32_t region_size;
1281
1282 uint16_t control;
1283 uint16_t status;
1284 uint8_t ibmr;
1285 uint8_t data;
1286 };
1287
1288 #define IBMR 0x80 /* I2C Bus Monitor register */
1289 #define IDBR 0x88 /* I2C Data Buffer register */
1290 #define ICR 0x90 /* I2C Control register */
1291 #define ISR 0x98 /* I2C Status register */
1292 #define ISAR 0xa0 /* I2C Slave Address register */
1293
1294 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1295 {
1296 uint16_t level = 0;
1297 level |= s->status & s->control & (1 << 10); /* BED */
1298 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1299 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1300 level |= s->status & (1 << 9); /* SAD */
1301 qemu_set_irq(s->irq, !!level);
1302 }
1303
1304 /* These are only stubs now. */
1305 static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1306 {
1307 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1308 PXA2xxI2CState *s = slave->host;
1309
1310 switch (event) {
1311 case I2C_START_SEND:
1312 s->status |= (1 << 9); /* set SAD */
1313 s->status &= ~(1 << 0); /* clear RWM */
1314 break;
1315 case I2C_START_RECV:
1316 s->status |= (1 << 9); /* set SAD */
1317 s->status |= 1 << 0; /* set RWM */
1318 break;
1319 case I2C_FINISH:
1320 s->status |= (1 << 4); /* set SSD */
1321 break;
1322 case I2C_NACK:
1323 s->status |= 1 << 1; /* set ACKNAK */
1324 break;
1325 }
1326 pxa2xx_i2c_update(s);
1327 }
1328
1329 static int pxa2xx_i2c_rx(i2c_slave *i2c)
1330 {
1331 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1332 PXA2xxI2CState *s = slave->host;
1333 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1334 return 0;
1335
1336 if (s->status & (1 << 0)) { /* RWM */
1337 s->status |= 1 << 6; /* set ITE */
1338 }
1339 pxa2xx_i2c_update(s);
1340
1341 return s->data;
1342 }
1343
1344 static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1345 {
1346 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1347 PXA2xxI2CState *s = slave->host;
1348 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1349 return 1;
1350
1351 if (!(s->status & (1 << 0))) { /* RWM */
1352 s->status |= 1 << 7; /* set IRF */
1353 s->data = data;
1354 }
1355 pxa2xx_i2c_update(s);
1356
1357 return 1;
1358 }
1359
1360 static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1361 {
1362 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1363
1364 addr -= s->offset;
1365 switch (addr) {
1366 case ICR:
1367 return s->control;
1368 case ISR:
1369 return s->status | (i2c_bus_busy(s->bus) << 2);
1370 case ISAR:
1371 return s->slave->i2c.address;
1372 case IDBR:
1373 return s->data;
1374 case IBMR:
1375 if (s->status & (1 << 2))
1376 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1377 else
1378 s->ibmr = 0;
1379 return s->ibmr;
1380 default:
1381 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1382 break;
1383 }
1384 return 0;
1385 }
1386
1387 static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1388 uint32_t value)
1389 {
1390 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1391 int ack;
1392
1393 addr -= s->offset;
1394 switch (addr) {
1395 case ICR:
1396 s->control = value & 0xfff7;
1397 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1398 /* TODO: slave mode */
1399 if (value & (1 << 0)) { /* START condition */
1400 if (s->data & 1)
1401 s->status |= 1 << 0; /* set RWM */
1402 else
1403 s->status &= ~(1 << 0); /* clear RWM */
1404 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1405 } else {
1406 if (s->status & (1 << 0)) { /* RWM */
1407 s->data = i2c_recv(s->bus);
1408 if (value & (1 << 2)) /* ACKNAK */
1409 i2c_nack(s->bus);
1410 ack = 1;
1411 } else
1412 ack = !i2c_send(s->bus, s->data);
1413 }
1414
1415 if (value & (1 << 1)) /* STOP condition */
1416 i2c_end_transfer(s->bus);
1417
1418 if (ack) {
1419 if (value & (1 << 0)) /* START condition */
1420 s->status |= 1 << 6; /* set ITE */
1421 else
1422 if (s->status & (1 << 0)) /* RWM */
1423 s->status |= 1 << 7; /* set IRF */
1424 else
1425 s->status |= 1 << 6; /* set ITE */
1426 s->status &= ~(1 << 1); /* clear ACKNAK */
1427 } else {
1428 s->status |= 1 << 6; /* set ITE */
1429 s->status |= 1 << 10; /* set BED */
1430 s->status |= 1 << 1; /* set ACKNAK */
1431 }
1432 }
1433 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1434 if (value & (1 << 4)) /* MA */
1435 i2c_end_transfer(s->bus);
1436 pxa2xx_i2c_update(s);
1437 break;
1438
1439 case ISR:
1440 s->status &= ~(value & 0x07f0);
1441 pxa2xx_i2c_update(s);
1442 break;
1443
1444 case ISAR:
1445 i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
1446 break;
1447
1448 case IDBR:
1449 s->data = value & 0xff;
1450 break;
1451
1452 default:
1453 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1454 }
1455 }
1456
1457 static CPUReadMemoryFunc * const pxa2xx_i2c_readfn[] = {
1458 pxa2xx_i2c_read,
1459 pxa2xx_i2c_read,
1460 pxa2xx_i2c_read,
1461 };
1462
1463 static CPUWriteMemoryFunc * const pxa2xx_i2c_writefn[] = {
1464 pxa2xx_i2c_write,
1465 pxa2xx_i2c_write,
1466 pxa2xx_i2c_write,
1467 };
1468
1469 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1470 .name = "pxa2xx_i2c_slave",
1471 .version_id = 1,
1472 .minimum_version_id = 1,
1473 .minimum_version_id_old = 1,
1474 .fields = (VMStateField []) {
1475 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState),
1476 VMSTATE_END_OF_LIST()
1477 }
1478 };
1479
1480 static const VMStateDescription vmstate_pxa2xx_i2c = {
1481 .name = "pxa2xx_i2c",
1482 .version_id = 1,
1483 .minimum_version_id = 1,
1484 .minimum_version_id_old = 1,
1485 .fields = (VMStateField []) {
1486 VMSTATE_UINT16(control, PXA2xxI2CState),
1487 VMSTATE_UINT16(status, PXA2xxI2CState),
1488 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1489 VMSTATE_UINT8(data, PXA2xxI2CState),
1490 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1491 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *),
1492 VMSTATE_END_OF_LIST()
1493 }
1494 };
1495
1496 static int pxa2xx_i2c_slave_init(i2c_slave *i2c)
1497 {
1498 /* Nothing to do. */
1499 return 0;
1500 }
1501
1502 static I2CSlaveInfo pxa2xx_i2c_slave_info = {
1503 .qdev.name = "pxa2xx-i2c-slave",
1504 .qdev.size = sizeof(PXA2xxI2CSlaveState),
1505 .init = pxa2xx_i2c_slave_init,
1506 .event = pxa2xx_i2c_event,
1507 .recv = pxa2xx_i2c_rx,
1508 .send = pxa2xx_i2c_tx
1509 };
1510
1511 PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
1512 qemu_irq irq, uint32_t region_size)
1513 {
1514 DeviceState *dev;
1515 SysBusDevice *i2c_dev;
1516 PXA2xxI2CState *s;
1517
1518 i2c_dev = sysbus_from_qdev(qdev_create(NULL, "pxa2xx_i2c"));
1519 qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1);
1520 qdev_prop_set_uint32(&i2c_dev->qdev, "offset",
1521 base - (base & (~region_size) & TARGET_PAGE_MASK));
1522
1523 qdev_init_nofail(&i2c_dev->qdev);
1524
1525 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1526 sysbus_connect_irq(i2c_dev, 0, irq);
1527
1528 s = FROM_SYSBUS(PXA2xxI2CState, i2c_dev);
1529 /* FIXME: Should the slave device really be on a separate bus? */
1530 dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0);
1531 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev));
1532 s->slave->host = s;
1533
1534 return s;
1535 }
1536
1537 static int pxa2xx_i2c_initfn(SysBusDevice *dev)
1538 {
1539 PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev);
1540 int iomemtype;
1541
1542 s->bus = i2c_init_bus(&dev->qdev, "i2c");
1543
1544 iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn,
1545 pxa2xx_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
1546 sysbus_init_mmio(dev, s->region_size, iomemtype);
1547 sysbus_init_irq(dev, &s->irq);
1548
1549 return 0;
1550 }
1551
1552 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1553 {
1554 return s->bus;
1555 }
1556
1557 static SysBusDeviceInfo pxa2xx_i2c_info = {
1558 .init = pxa2xx_i2c_initfn,
1559 .qdev.name = "pxa2xx_i2c",
1560 .qdev.desc = "PXA2xx I2C Bus Controller",
1561 .qdev.size = sizeof(PXA2xxI2CState),
1562 .qdev.vmsd = &vmstate_pxa2xx_i2c,
1563 .qdev.props = (Property[]) {
1564 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1565 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1566 DEFINE_PROP_END_OF_LIST(),
1567 },
1568 };
1569
1570 /* PXA Inter-IC Sound Controller */
1571 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1572 {
1573 i2s->rx_len = 0;
1574 i2s->tx_len = 0;
1575 i2s->fifo_len = 0;
1576 i2s->clk = 0x1a;
1577 i2s->control[0] = 0x00;
1578 i2s->control[1] = 0x00;
1579 i2s->status = 0x00;
1580 i2s->mask = 0x00;
1581 }
1582
1583 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1584 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1585 #define SACR_DREC(val) (val & (1 << 3))
1586 #define SACR_DPRL(val) (val & (1 << 4))
1587
1588 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1589 {
1590 int rfs, tfs;
1591 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1592 !SACR_DREC(i2s->control[1]);
1593 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1594 i2s->enable && !SACR_DPRL(i2s->control[1]);
1595
1596 qemu_set_irq(i2s->rx_dma, rfs);
1597 qemu_set_irq(i2s->tx_dma, tfs);
1598
1599 i2s->status &= 0xe0;
1600 if (i2s->fifo_len < 16 || !i2s->enable)
1601 i2s->status |= 1 << 0; /* TNF */
1602 if (i2s->rx_len)
1603 i2s->status |= 1 << 1; /* RNE */
1604 if (i2s->enable)
1605 i2s->status |= 1 << 2; /* BSY */
1606 if (tfs)
1607 i2s->status |= 1 << 3; /* TFS */
1608 if (rfs)
1609 i2s->status |= 1 << 4; /* RFS */
1610 if (!(i2s->tx_len && i2s->enable))
1611 i2s->status |= i2s->fifo_len << 8; /* TFL */
1612 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1613
1614 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1615 }
1616
1617 #define SACR0 0x00 /* Serial Audio Global Control register */
1618 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1619 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1620 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1621 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1622 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1623 #define SADR 0x80 /* Serial Audio Data register */
1624
1625 static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1626 {
1627 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1628
1629 switch (addr) {
1630 case SACR0:
1631 return s->control[0];
1632 case SACR1:
1633 return s->control[1];
1634 case SASR0:
1635 return s->status;
1636 case SAIMR:
1637 return s->mask;
1638 case SAICR:
1639 return 0;
1640 case SADIV:
1641 return s->clk;
1642 case SADR:
1643 if (s->rx_len > 0) {
1644 s->rx_len --;
1645 pxa2xx_i2s_update(s);
1646 return s->codec_in(s->opaque);
1647 }
1648 return 0;
1649 default:
1650 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1651 break;
1652 }
1653 return 0;
1654 }
1655
1656 static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1657 uint32_t value)
1658 {
1659 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1660 uint32_t *sample;
1661
1662 switch (addr) {
1663 case SACR0:
1664 if (value & (1 << 3)) /* RST */
1665 pxa2xx_i2s_reset(s);
1666 s->control[0] = value & 0xff3d;
1667 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1668 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1669 s->codec_out(s->opaque, *sample);
1670 s->status &= ~(1 << 7); /* I2SOFF */
1671 }
1672 if (value & (1 << 4)) /* EFWR */
1673 printf("%s: Attempt to use special function\n", __FUNCTION__);
1674 s->enable = (value & 9) == 1; /* ENB && !RST*/
1675 pxa2xx_i2s_update(s);
1676 break;
1677 case SACR1:
1678 s->control[1] = value & 0x0039;
1679 if (value & (1 << 5)) /* ENLBF */
1680 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1681 if (value & (1 << 4)) /* DPRL */
1682 s->fifo_len = 0;
1683 pxa2xx_i2s_update(s);
1684 break;
1685 case SAIMR:
1686 s->mask = value & 0x0078;
1687 pxa2xx_i2s_update(s);
1688 break;
1689 case SAICR:
1690 s->status &= ~(value & (3 << 5));
1691 pxa2xx_i2s_update(s);
1692 break;
1693 case SADIV:
1694 s->clk = value & 0x007f;
1695 break;
1696 case SADR:
1697 if (s->tx_len && s->enable) {
1698 s->tx_len --;
1699 pxa2xx_i2s_update(s);
1700 s->codec_out(s->opaque, value);
1701 } else if (s->fifo_len < 16) {
1702 s->fifo[s->fifo_len ++] = value;
1703 pxa2xx_i2s_update(s);
1704 }
1705 break;
1706 default:
1707 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1708 }
1709 }
1710
1711 static CPUReadMemoryFunc * const pxa2xx_i2s_readfn[] = {
1712 pxa2xx_i2s_read,
1713 pxa2xx_i2s_read,
1714 pxa2xx_i2s_read,
1715 };
1716
1717 static CPUWriteMemoryFunc * const pxa2xx_i2s_writefn[] = {
1718 pxa2xx_i2s_write,
1719 pxa2xx_i2s_write,
1720 pxa2xx_i2s_write,
1721 };
1722
1723 static const VMStateDescription vmstate_pxa2xx_i2s = {
1724 .name = "pxa2xx_i2s",
1725 .version_id = 0,
1726 .minimum_version_id = 0,
1727 .minimum_version_id_old = 0,
1728 .fields = (VMStateField[]) {
1729 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1730 VMSTATE_UINT32(status, PXA2xxI2SState),
1731 VMSTATE_UINT32(mask, PXA2xxI2SState),
1732 VMSTATE_UINT32(clk, PXA2xxI2SState),
1733 VMSTATE_INT32(enable, PXA2xxI2SState),
1734 VMSTATE_INT32(rx_len, PXA2xxI2SState),
1735 VMSTATE_INT32(tx_len, PXA2xxI2SState),
1736 VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1737 VMSTATE_END_OF_LIST()
1738 }
1739 };
1740
1741 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1742 {
1743 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1744 uint32_t *sample;
1745
1746 /* Signal FIFO errors */
1747 if (s->enable && s->tx_len)
1748 s->status |= 1 << 5; /* TUR */
1749 if (s->enable && s->rx_len)
1750 s->status |= 1 << 6; /* ROR */
1751
1752 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1753 * handle the cases where it makes a difference. */
1754 s->tx_len = tx - s->fifo_len;
1755 s->rx_len = rx;
1756 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1757 if (s->enable)
1758 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1759 s->codec_out(s->opaque, *sample);
1760 pxa2xx_i2s_update(s);
1761 }
1762
1763 static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
1764 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1765 {
1766 int iomemtype;
1767 PXA2xxI2SState *s = (PXA2xxI2SState *)
1768 g_malloc0(sizeof(PXA2xxI2SState));
1769
1770 s->irq = irq;
1771 s->rx_dma = rx_dma;
1772 s->tx_dma = tx_dma;
1773 s->data_req = pxa2xx_i2s_data_req;
1774
1775 pxa2xx_i2s_reset(s);
1776
1777 iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn,
1778 pxa2xx_i2s_writefn, s, DEVICE_NATIVE_ENDIAN);
1779 cpu_register_physical_memory(base, 0x100000, iomemtype);
1780
1781 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1782
1783 return s;
1784 }
1785
1786 /* PXA Fast Infra-red Communications Port */
1787 struct PXA2xxFIrState {
1788 qemu_irq irq;
1789 qemu_irq rx_dma;
1790 qemu_irq tx_dma;
1791 int enable;
1792 CharDriverState *chr;
1793
1794 uint8_t control[3];
1795 uint8_t status[2];
1796
1797 int rx_len;
1798 int rx_start;
1799 uint8_t rx_fifo[64];
1800 };
1801
1802 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1803 {
1804 s->control[0] = 0x00;
1805 s->control[1] = 0x00;
1806 s->control[2] = 0x00;
1807 s->status[0] = 0x00;
1808 s->status[1] = 0x00;
1809 s->enable = 0;
1810 }
1811
1812 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1813 {
1814 static const int tresh[4] = { 8, 16, 32, 0 };
1815 int intr = 0;
1816 if ((s->control[0] & (1 << 4)) && /* RXE */
1817 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1818 s->status[0] |= 1 << 4; /* RFS */
1819 else
1820 s->status[0] &= ~(1 << 4); /* RFS */
1821 if (s->control[0] & (1 << 3)) /* TXE */
1822 s->status[0] |= 1 << 3; /* TFS */
1823 else
1824 s->status[0] &= ~(1 << 3); /* TFS */
1825 if (s->rx_len)
1826 s->status[1] |= 1 << 2; /* RNE */
1827 else
1828 s->status[1] &= ~(1 << 2); /* RNE */
1829 if (s->control[0] & (1 << 4)) /* RXE */
1830 s->status[1] |= 1 << 0; /* RSY */
1831 else
1832 s->status[1] &= ~(1 << 0); /* RSY */
1833
1834 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1835 (s->status[0] & (1 << 4)); /* RFS */
1836 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1837 (s->status[0] & (1 << 3)); /* TFS */
1838 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1839 (s->status[0] & (1 << 6)); /* EOC */
1840 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1841 (s->status[0] & (1 << 1)); /* TUR */
1842 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1843
1844 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1845 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1846
1847 qemu_set_irq(s->irq, intr && s->enable);
1848 }
1849
1850 #define ICCR0 0x00 /* FICP Control register 0 */
1851 #define ICCR1 0x04 /* FICP Control register 1 */
1852 #define ICCR2 0x08 /* FICP Control register 2 */
1853 #define ICDR 0x0c /* FICP Data register */
1854 #define ICSR0 0x14 /* FICP Status register 0 */
1855 #define ICSR1 0x18 /* FICP Status register 1 */
1856 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1857
1858 static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1859 {
1860 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1861 uint8_t ret;
1862
1863 switch (addr) {
1864 case ICCR0:
1865 return s->control[0];
1866 case ICCR1:
1867 return s->control[1];
1868 case ICCR2:
1869 return s->control[2];
1870 case ICDR:
1871 s->status[0] &= ~0x01;
1872 s->status[1] &= ~0x72;
1873 if (s->rx_len) {
1874 s->rx_len --;
1875 ret = s->rx_fifo[s->rx_start ++];
1876 s->rx_start &= 63;
1877 pxa2xx_fir_update(s);
1878 return ret;
1879 }
1880 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1881 break;
1882 case ICSR0:
1883 return s->status[0];
1884 case ICSR1:
1885 return s->status[1] | (1 << 3); /* TNF */
1886 case ICFOR:
1887 return s->rx_len;
1888 default:
1889 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1890 break;
1891 }
1892 return 0;
1893 }
1894
1895 static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1896 uint32_t value)
1897 {
1898 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1899 uint8_t ch;
1900
1901 switch (addr) {
1902 case ICCR0:
1903 s->control[0] = value;
1904 if (!(value & (1 << 4))) /* RXE */
1905 s->rx_len = s->rx_start = 0;
1906 if (!(value & (1 << 3))) { /* TXE */
1907 /* Nop */
1908 }
1909 s->enable = value & 1; /* ITR */
1910 if (!s->enable)
1911 s->status[0] = 0;
1912 pxa2xx_fir_update(s);
1913 break;
1914 case ICCR1:
1915 s->control[1] = value;
1916 break;
1917 case ICCR2:
1918 s->control[2] = value & 0x3f;
1919 pxa2xx_fir_update(s);
1920 break;
1921 case ICDR:
1922 if (s->control[2] & (1 << 2)) /* TXP */
1923 ch = value;
1924 else
1925 ch = ~value;
1926 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1927 qemu_chr_fe_write(s->chr, &ch, 1);
1928 break;
1929 case ICSR0:
1930 s->status[0] &= ~(value & 0x66);
1931 pxa2xx_fir_update(s);
1932 break;
1933 case ICFOR:
1934 break;
1935 default:
1936 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1937 }
1938 }
1939
1940 static CPUReadMemoryFunc * const pxa2xx_fir_readfn[] = {
1941 pxa2xx_fir_read,
1942 pxa2xx_fir_read,
1943 pxa2xx_fir_read,
1944 };
1945
1946 static CPUWriteMemoryFunc * const pxa2xx_fir_writefn[] = {
1947 pxa2xx_fir_write,
1948 pxa2xx_fir_write,
1949 pxa2xx_fir_write,
1950 };
1951
1952 static int pxa2xx_fir_is_empty(void *opaque)
1953 {
1954 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1955 return (s->rx_len < 64);
1956 }
1957
1958 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1959 {
1960 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1961 if (!(s->control[0] & (1 << 4))) /* RXE */
1962 return;
1963
1964 while (size --) {
1965 s->status[1] |= 1 << 4; /* EOF */
1966 if (s->rx_len >= 64) {
1967 s->status[1] |= 1 << 6; /* ROR */
1968 break;
1969 }
1970
1971 if (s->control[2] & (1 << 3)) /* RXP */
1972 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1973 else
1974 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1975 }
1976
1977 pxa2xx_fir_update(s);
1978 }
1979
1980 static void pxa2xx_fir_event(void *opaque, int event)
1981 {
1982 }
1983
1984 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1985 {
1986 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1987 int i;
1988
1989 qemu_put_be32(f, s->enable);
1990
1991 qemu_put_8s(f, &s->control[0]);
1992 qemu_put_8s(f, &s->control[1]);
1993 qemu_put_8s(f, &s->control[2]);
1994 qemu_put_8s(f, &s->status[0]);
1995 qemu_put_8s(f, &s->status[1]);
1996
1997 qemu_put_byte(f, s->rx_len);
1998 for (i = 0; i < s->rx_len; i ++)
1999 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
2000 }
2001
2002 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
2003 {
2004 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
2005 int i;
2006
2007 s->enable = qemu_get_be32(f);
2008
2009 qemu_get_8s(f, &s->control[0]);
2010 qemu_get_8s(f, &s->control[1]);
2011 qemu_get_8s(f, &s->control[2]);
2012 qemu_get_8s(f, &s->status[0]);
2013 qemu_get_8s(f, &s->status[1]);
2014
2015 s->rx_len = qemu_get_byte(f);
2016 s->rx_start = 0;
2017 for (i = 0; i < s->rx_len; i ++)
2018 s->rx_fifo[i] = qemu_get_byte(f);
2019
2020 return 0;
2021 }
2022
2023 static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
2024 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
2025 CharDriverState *chr)
2026 {
2027 int iomemtype;
2028 PXA2xxFIrState *s = (PXA2xxFIrState *)
2029 g_malloc0(sizeof(PXA2xxFIrState));
2030
2031 s->irq = irq;
2032 s->rx_dma = rx_dma;
2033 s->tx_dma = tx_dma;
2034 s->chr = chr;
2035
2036 pxa2xx_fir_reset(s);
2037
2038 iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn,
2039 pxa2xx_fir_writefn, s, DEVICE_NATIVE_ENDIAN);
2040 cpu_register_physical_memory(base, 0x1000, iomemtype);
2041
2042 if (chr)
2043 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2044 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2045
2046 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
2047 pxa2xx_fir_load, s);
2048
2049 return s;
2050 }
2051
2052 static void pxa2xx_reset(void *opaque, int line, int level)
2053 {
2054 PXA2xxState *s = (PXA2xxState *) opaque;
2055
2056 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2057 cpu_reset(s->env);
2058 /* TODO: reset peripherals */
2059 }
2060 }
2061
2062 /* Initialise a PXA270 integrated chip (ARM based core). */
2063 PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
2064 {
2065 PXA2xxState *s;
2066 int iomemtype, i;
2067 DriveInfo *dinfo;
2068 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2069
2070 if (revision && strncmp(revision, "pxa27", 5)) {
2071 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2072 exit(1);
2073 }
2074 if (!revision)
2075 revision = "pxa270";
2076
2077 s->env = cpu_init(revision);
2078 if (!s->env) {
2079 fprintf(stderr, "Unable to find CPU definition\n");
2080 exit(1);
2081 }
2082 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2083
2084 /* SDRAM & Internal Memory Storage */
2085 cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
2086 sdram_size, qemu_ram_alloc(NULL, "pxa270.sdram",
2087 sdram_size) | IO_MEM_RAM);
2088 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
2089 0x40000, qemu_ram_alloc(NULL, "pxa270.internal",
2090 0x40000) | IO_MEM_RAM);
2091
2092 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2093
2094 s->dma = pxa27x_dma_init(0x40000000,
2095 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2096
2097 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2098 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2099 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2100 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2101 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2102 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2103 NULL);
2104
2105 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2106
2107 dinfo = drive_get(IF_SD, 0, 0);
2108 if (!dinfo) {
2109 fprintf(stderr, "qemu: missing SecureDigital device\n");
2110 exit(1);
2111 }
2112 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2113 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2114 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2115 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2116
2117 for (i = 0; pxa270_serial[i].io_base; i++) {
2118 if (serial_hds[i]) {
2119 serial_mm_init(get_system_memory(), pxa270_serial[i].io_base, 2,
2120 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2121 14857000 / 16, serial_hds[i],
2122 DEVICE_NATIVE_ENDIAN);
2123 } else {
2124 break;
2125 }
2126 }
2127 if (serial_hds[i])
2128 s->fir = pxa2xx_fir_init(0x40800000,
2129 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2130 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2131 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2132 serial_hds[i]);
2133
2134 s->lcd = pxa2xx_lcdc_init(0x44000000,
2135 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2136
2137 s->cm_base = 0x41300000;
2138 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2139 s->clkcfg = 0x00000009; /* Turbo mode active */
2140 iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2141 pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
2142 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2143 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2144
2145 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2146
2147 s->mm_base = 0x48000000;
2148 s->mm_regs[MDMRS >> 2] = 0x00020002;
2149 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2150 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2151 iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2152 pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
2153 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2154 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2155
2156 s->pm_base = 0x40f00000;
2157 iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2158 pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
2159 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2160 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2161
2162 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2163 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2164 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2165 DeviceState *dev;
2166 dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
2167 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2168 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2169 }
2170
2171 if (usb_enabled) {
2172 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2173 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2174 }
2175
2176 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2177 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2178
2179 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2180 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2181
2182 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2183 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2184 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2185 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2186
2187 s->i2s = pxa2xx_i2s_init(0x40400000,
2188 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2189 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2190 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2191
2192 s->kp = pxa27x_keypad_init(0x41500000,
2193 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2194
2195 /* GPIO1 resets the processor */
2196 /* The handler can be overridden by board-specific code */
2197 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2198 return s;
2199 }
2200
2201 /* Initialise a PXA255 integrated chip (ARM based core). */
2202 PXA2xxState *pxa255_init(unsigned int sdram_size)
2203 {
2204 PXA2xxState *s;
2205 int iomemtype, i;
2206 DriveInfo *dinfo;
2207
2208 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2209
2210 s->env = cpu_init("pxa255");
2211 if (!s->env) {
2212 fprintf(stderr, "Unable to find CPU definition\n");
2213 exit(1);
2214 }
2215 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2216
2217 /* SDRAM & Internal Memory Storage */
2218 cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
2219 qemu_ram_alloc(NULL, "pxa255.sdram",
2220 sdram_size) | IO_MEM_RAM);
2221 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
2222 qemu_ram_alloc(NULL, "pxa255.internal",
2223 PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
2224
2225 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2226
2227 s->dma = pxa255_dma_init(0x40000000,
2228 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2229
2230 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2231 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2232 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2233 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2234 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2235 NULL);
2236
2237 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
2238
2239 dinfo = drive_get(IF_SD, 0, 0);
2240 if (!dinfo) {
2241 fprintf(stderr, "qemu: missing SecureDigital device\n");
2242 exit(1);
2243 }
2244 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2245 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2246 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2247 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2248
2249 for (i = 0; pxa255_serial[i].io_base; i++) {
2250 if (serial_hds[i]) {
2251 serial_mm_init(get_system_memory(), pxa255_serial[i].io_base, 2,
2252 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2253 14745600 / 16, serial_hds[i],
2254 DEVICE_NATIVE_ENDIAN);
2255 } else {
2256 break;
2257 }
2258 }
2259 if (serial_hds[i])
2260 s->fir = pxa2xx_fir_init(0x40800000,
2261 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2262 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2263 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2264 serial_hds[i]);
2265
2266 s->lcd = pxa2xx_lcdc_init(0x44000000,
2267 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2268
2269 s->cm_base = 0x41300000;
2270 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2271 s->clkcfg = 0x00000009; /* Turbo mode active */
2272 iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2273 pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
2274 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2275 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2276
2277 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2278
2279 s->mm_base = 0x48000000;
2280 s->mm_regs[MDMRS >> 2] = 0x00020002;
2281 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2282 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2283 iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2284 pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
2285 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2286 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2287
2288 s->pm_base = 0x40f00000;
2289 iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2290 pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
2291 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2292 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2293
2294 for (i = 0; pxa255_ssp[i].io_base; i ++);
2295 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2296 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2297 DeviceState *dev;
2298 dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
2299 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2300 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2301 }
2302
2303 if (usb_enabled) {
2304 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2305 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2306 }
2307
2308 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2309 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2310
2311 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2312 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2313
2314 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2315 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2316 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2317 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2318
2319 s->i2s = pxa2xx_i2s_init(0x40400000,
2320 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2321 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2322 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2323
2324 /* GPIO1 resets the processor */
2325 /* The handler can be overridden by board-specific code */
2326 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2327 return s;
2328 }
2329
2330 static void pxa2xx_register_devices(void)
2331 {
2332 i2c_register_slave(&pxa2xx_i2c_slave_info);
2333 sysbus_register_dev("pxa2xx-ssp", sizeof(PXA2xxSSPState), pxa2xx_ssp_init);
2334 sysbus_register_withprop(&pxa2xx_i2c_info);
2335 sysbus_register_withprop(&pxa2xx_rtc_sysbus_info);
2336 }
2337
2338 device_init(pxa2xx_register_devices)
QEMU mirror