hw/pxa2xx_gpio.c

   1 /*
   2  * Intel XScale PXA255/270 GPIO controller emulation.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "vl.h"
  11
  12 #define PXA2XX_GPIO_BANKS       4
  13
  14 struct pxa2xx_gpio_info_s {
  15     target_phys_addr_t base;
  16     qemu_irq *pic;
  17     int lines;
  18     CPUState *cpu_env;
  19     qemu_irq *in;
  20
  21     /* XXX: GNU C vectors are more suitable */
  22     uint32_t ilevel[PXA2XX_GPIO_BANKS];
  23     uint32_t olevel[PXA2XX_GPIO_BANKS];
  24     uint32_t dir[PXA2XX_GPIO_BANKS];
  25     uint32_t rising[PXA2XX_GPIO_BANKS];
  26     uint32_t falling[PXA2XX_GPIO_BANKS];
  27     uint32_t status[PXA2XX_GPIO_BANKS];
  28     uint32_t gpsr[PXA2XX_GPIO_BANKS];
  29     uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
  30
  31     uint32_t prev_level[PXA2XX_GPIO_BANKS];
  32     qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
  33     qemu_irq read_notify;
  34 };
  35
  36 static struct {
  37     enum {
  38         GPIO_NONE,
  39         GPLR,
  40         GPSR,
  41         GPCR,
  42         GPDR,
  43         GRER,
  44         GFER,
  45         GEDR,
  46         GAFR_L,
  47         GAFR_U,
  48     } reg;
  49     int bank;
  50 } pxa2xx_gpio_regs[0x200] = {
  51     [0 ... 0x1ff] = { GPIO_NONE, 0 },
  52 #define PXA2XX_REG(reg, a0, a1, a2, a3) \
  53     [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
  54
  55     PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
  56     PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
  57     PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
  58     PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
  59     PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
  60     PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
  61     PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
  62     PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
  63     PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
  64 };
  65
  66 static void pxa2xx_gpio_irq_update(struct pxa2xx_gpio_info_s *s)
  67 {
  68     if (s->status[0] & (1 << 0))
  69         qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_0]);
  70     else
  71         qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_0]);
  72
  73     if (s->status[0] & (1 << 1))
  74         qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_1]);
  75     else
  76         qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_1]);
  77
  78     if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
  79         qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_X]);
  80     else
  81         qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_X]);
  82 }
  83
  84 /* Bitmap of pins used as standby and sleep wake-up sources.  */
  85 static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
  86     0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
  87 };
  88
  89 static void pxa2xx_gpio_set(void *opaque, int line, int level)
  90 {
  91     struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
  92     int bank;
  93     uint32_t mask;
  94
  95     if (line >= s->lines) {
  96         printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
  97         return;
  98     }
  99
 100     bank = line >> 5;
 101     mask = 1 << (line & 31);
 102
 103     if (level) {
 104         s->status[bank] |= s->rising[bank] & mask &
 105                 ~s->ilevel[bank] & ~s->dir[bank];
 106         s->ilevel[bank] |= mask;
 107     } else {
 108         s->status[bank] |= s->falling[bank] & mask &
 109                 s->ilevel[bank] & ~s->dir[bank];
 110         s->ilevel[bank] &= ~mask;
 111     }
 112
 113     if (s->status[bank] & mask)
 114         pxa2xx_gpio_irq_update(s);
 115
 116     /* Wake-up GPIOs */
 117     if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank]))
 118         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
 119 }
 120
 121 static void pxa2xx_gpio_handler_update(struct pxa2xx_gpio_info_s *s) {
 122     uint32_t level, diff;
 123     int i, bit, line;
 124     for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
 125         level = s->olevel[i] & s->dir[i];
 126
 127         for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
 128             bit = ffs(diff) - 1;
 129             line = bit + 32 * i;
 130             qemu_set_irq(s->handler[line], (level >> bit) & 1);
 131         }
 132
 133         s->prev_level[i] = level;
 134     }
 135 }
 136
 137 static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
 138 {
 139     struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
 140     uint32_t ret;
 141     int bank;
 142     offset -= s->base;
 143     if (offset >= 0x200)
 144         return 0;
 145
 146     bank = pxa2xx_gpio_regs[offset].bank;
 147     switch (pxa2xx_gpio_regs[offset].reg) {
 148     case GPDR:          /* GPIO Pin-Direction registers */
 149         return s->dir[bank];
 150
 151     case GPSR:          /* GPIO Pin-Output Set registers */
 152         printf("%s: Read from a write-only register " REG_FMT "\n",
 153                         __FUNCTION__, offset);
 154         return s->gpsr[bank];   /* Return last written value.  */
 155
 156     case GRER:          /* GPIO Rising-Edge Detect Enable registers */
 157         return s->rising[bank];
 158
 159     case GFER:          /* GPIO Falling-Edge Detect Enable registers */
 160         return s->falling[bank];
 161
 162     case GAFR_L:        /* GPIO Alternate Function registers */
 163         return s->gafr[bank * 2];
 164
 165     case GAFR_U:        /* GPIO Alternate Function registers */
 166         return s->gafr[bank * 2 + 1];
 167
 168     case GPLR:          /* GPIO Pin-Level registers */
 169         ret = (s->olevel[bank] & s->dir[bank]) |
 170                 (s->ilevel[bank] & ~s->dir[bank]);
 171         qemu_irq_raise(s->read_notify);
 172         return ret;
 173
 174     case GEDR:          /* GPIO Edge Detect Status registers */
 175         return s->status[bank];
 176
 177     default:
 178         cpu_abort(cpu_single_env,
 179                 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 180     }
 181
 182     return 0;
 183 }
 184
 185 static void pxa2xx_gpio_write(void *opaque,
 186                 target_phys_addr_t offset, uint32_t value)
 187 {
 188     struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
 189     int bank;
 190     offset -= s->base;
 191     if (offset >= 0x200)
 192         return;
 193
 194     bank = pxa2xx_gpio_regs[offset].bank;
 195     switch (pxa2xx_gpio_regs[offset].reg) {
 196     case GPDR:          /* GPIO Pin-Direction registers */
 197         s->dir[bank] = value;
 198         pxa2xx_gpio_handler_update(s);
 199         break;
 200
 201     case GPSR:          /* GPIO Pin-Output Set registers */
 202         s->olevel[bank] |= value;
 203         pxa2xx_gpio_handler_update(s);
 204         s->gpsr[bank] = value;
 205         break;
 206
 207     case GPCR:          /* GPIO Pin-Output Clear registers */
 208         s->olevel[bank] &= ~value;
 209         pxa2xx_gpio_handler_update(s);
 210         break;
 211
 212     case GRER:          /* GPIO Rising-Edge Detect Enable registers */
 213         s->rising[bank] = value;
 214         break;
 215
 216     case GFER:          /* GPIO Falling-Edge Detect Enable registers */
 217         s->falling[bank] = value;
 218         break;
 219
 220     case GAFR_L:        /* GPIO Alternate Function registers */
 221         s->gafr[bank * 2] = value;
 222         break;
 223
 224     case GAFR_U:        /* GPIO Alternate Function registers */
 225         s->gafr[bank * 2 + 1] = value;
 226         break;
 227
 228     case GEDR:          /* GPIO Edge Detect Status registers */
 229         s->status[bank] &= ~value;
 230         pxa2xx_gpio_irq_update(s);
 231         break;
 232
 233     default:
 234         cpu_abort(cpu_single_env,
 235                 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 236     }
 237 }
 238
 239 static CPUReadMemoryFunc *pxa2xx_gpio_readfn[] = {
 240     pxa2xx_gpio_read,
 241     pxa2xx_gpio_read,
 242     pxa2xx_gpio_read
 243 };
 244
 245 static CPUWriteMemoryFunc *pxa2xx_gpio_writefn[] = {
 246     pxa2xx_gpio_write,
 247     pxa2xx_gpio_write,
 248     pxa2xx_gpio_write
 249 };
 250
 251 static void pxa2xx_gpio_save(QEMUFile *f, void *opaque)
 252 {
 253     struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
 254     int i;
 255
 256     qemu_put_be32(f, s->lines);
 257
 258     for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
 259         qemu_put_be32s(f, &s->ilevel[i]);
 260         qemu_put_be32s(f, &s->olevel[i]);
 261         qemu_put_be32s(f, &s->dir[i]);
 262         qemu_put_be32s(f, &s->rising[i]);
 263         qemu_put_be32s(f, &s->falling[i]);
 264         qemu_put_be32s(f, &s->status[i]);
 265         qemu_put_be32s(f, &s->gafr[i * 2 + 0]);
 266         qemu_put_be32s(f, &s->gafr[i * 2 + 1]);
 267
 268         qemu_put_be32s(f, &s->prev_level[i]);
 269     }
 270 }
 271
 272 static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id)
 273 {
 274     struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
 275     int i;
 276
 277     if (qemu_get_be32(f) != s->lines)
 278         return -EINVAL;
 279
 280     for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
 281         qemu_get_be32s(f, &s->ilevel[i]);
 282         qemu_get_be32s(f, &s->olevel[i]);
 283         qemu_get_be32s(f, &s->dir[i]);
 284         qemu_get_be32s(f, &s->rising[i]);
 285         qemu_get_be32s(f, &s->falling[i]);
 286         qemu_get_be32s(f, &s->status[i]);
 287         qemu_get_be32s(f, &s->gafr[i * 2 + 0]);
 288         qemu_get_be32s(f, &s->gafr[i * 2 + 1]);
 289
 290         qemu_get_be32s(f, &s->prev_level[i]);
 291     }
 292
 293     return 0;
 294 }
 295
 296 struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
 297                 CPUState *env, qemu_irq *pic, int lines)
 298 {
 299     int iomemtype;
 300     struct pxa2xx_gpio_info_s *s;
 301
 302     s = (struct pxa2xx_gpio_info_s *)
 303             qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s));
 304     memset(s, 0, sizeof(struct pxa2xx_gpio_info_s));
 305     s->base = base;
 306     s->pic = pic;
 307     s->lines = lines;
 308     s->cpu_env = env;
 309     s->in = qemu_allocate_irqs(pxa2xx_gpio_set, s, lines);
 310
 311     iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn,
 312                     pxa2xx_gpio_writefn, s);
 313     cpu_register_physical_memory(base, 0x00001000, iomemtype);
 314
 315     register_savevm("pxa2xx_gpio", 0, 0,
 316                     pxa2xx_gpio_save, pxa2xx_gpio_load, s);
 317
 318     return s;
 319 }
 320
 321 qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s)
 322 {
 323     return s->in;
 324 }
 325
 326 void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s,
 327                 int line, qemu_irq handler)
 328 {
 329     if (line >= s->lines) {
 330         printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
 331         return;
 332     }
 333
 334     s->handler[line] = handler;
 335 }
 336
 337 /*
 338  * Registers a callback to notify on GPLR reads.  This normally
 339  * shouldn't be needed but it is used for the hack on Spitz machines.
 340  */
 341 void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler)
 342 {
 343     s->read_notify = handler;
 344 }