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[mirror_qemu.git] / hw / pxa2xx_lcd.c
1 /*
2 * Intel XScale PXA255/270 LCDC emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPLv2.
8 */
9
10 #include "hw.h"
11 #include "console.h"
12 #include "pxa.h"
13 #include "pixel_ops.h"
14 /* FIXME: For graphic_rotate. Should probably be done in common code. */
15 #include "sysemu.h"
16 #include "framebuffer.h"
17
18 struct DMAChannel {
19 target_phys_addr_t branch;
20 uint8_t up;
21 uint8_t palette[1024];
22 uint8_t pbuffer[1024];
23 void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
24 int *miny, int *maxy);
25
26 target_phys_addr_t descriptor;
27 target_phys_addr_t source;
28 uint32_t id;
29 uint32_t command;
30 };
31
32 struct PXA2xxLCDState {
33 MemoryRegion *sysmem;
34 MemoryRegion iomem;
35 qemu_irq irq;
36 int irqlevel;
37
38 int invalidated;
39 DisplayState *ds;
40 drawfn *line_fn[2];
41 int dest_width;
42 int xres, yres;
43 int pal_for;
44 int transp;
45 enum {
46 pxa_lcdc_2bpp = 1,
47 pxa_lcdc_4bpp = 2,
48 pxa_lcdc_8bpp = 3,
49 pxa_lcdc_16bpp = 4,
50 pxa_lcdc_18bpp = 5,
51 pxa_lcdc_18pbpp = 6,
52 pxa_lcdc_19bpp = 7,
53 pxa_lcdc_19pbpp = 8,
54 pxa_lcdc_24bpp = 9,
55 pxa_lcdc_25bpp = 10,
56 } bpp;
57
58 uint32_t control[6];
59 uint32_t status[2];
60 uint32_t ovl1c[2];
61 uint32_t ovl2c[2];
62 uint32_t ccr;
63 uint32_t cmdcr;
64 uint32_t trgbr;
65 uint32_t tcr;
66 uint32_t liidr;
67 uint8_t bscntr;
68
69 struct DMAChannel dma_ch[7];
70
71 qemu_irq vsync_cb;
72 int orientation;
73 };
74
75 typedef struct QEMU_PACKED {
76 uint32_t fdaddr;
77 uint32_t fsaddr;
78 uint32_t fidr;
79 uint32_t ldcmd;
80 } PXAFrameDescriptor;
81
82 #define LCCR0 0x000 /* LCD Controller Control register 0 */
83 #define LCCR1 0x004 /* LCD Controller Control register 1 */
84 #define LCCR2 0x008 /* LCD Controller Control register 2 */
85 #define LCCR3 0x00c /* LCD Controller Control register 3 */
86 #define LCCR4 0x010 /* LCD Controller Control register 4 */
87 #define LCCR5 0x014 /* LCD Controller Control register 5 */
88
89 #define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
90 #define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
91 #define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
92 #define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
93 #define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
94 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
95 #define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
96
97 #define LCSR1 0x034 /* LCD Controller Status register 1 */
98 #define LCSR0 0x038 /* LCD Controller Status register 0 */
99 #define LIIDR 0x03c /* LCD Controller Interrupt ID register */
100
101 #define TRGBR 0x040 /* TMED RGB Seed register */
102 #define TCR 0x044 /* TMED Control register */
103
104 #define OVL1C1 0x050 /* Overlay 1 Control register 1 */
105 #define OVL1C2 0x060 /* Overlay 1 Control register 2 */
106 #define OVL2C1 0x070 /* Overlay 2 Control register 1 */
107 #define OVL2C2 0x080 /* Overlay 2 Control register 2 */
108 #define CCR 0x090 /* Cursor Control register */
109
110 #define CMDCR 0x100 /* Command Control register */
111 #define PRSR 0x104 /* Panel Read Status register */
112
113 #define PXA_LCDDMA_CHANS 7
114 #define DMA_FDADR 0x00 /* Frame Descriptor Address register */
115 #define DMA_FSADR 0x04 /* Frame Source Address register */
116 #define DMA_FIDR 0x08 /* Frame ID register */
117 #define DMA_LDCMD 0x0c /* Command register */
118
119 /* LCD Buffer Strength Control register */
120 #define BSCNTR 0x04000054
121
122 /* Bitfield masks */
123 #define LCCR0_ENB (1 << 0)
124 #define LCCR0_CMS (1 << 1)
125 #define LCCR0_SDS (1 << 2)
126 #define LCCR0_LDM (1 << 3)
127 #define LCCR0_SOFM0 (1 << 4)
128 #define LCCR0_IUM (1 << 5)
129 #define LCCR0_EOFM0 (1 << 6)
130 #define LCCR0_PAS (1 << 7)
131 #define LCCR0_DPD (1 << 9)
132 #define LCCR0_DIS (1 << 10)
133 #define LCCR0_QDM (1 << 11)
134 #define LCCR0_PDD (0xff << 12)
135 #define LCCR0_BSM0 (1 << 20)
136 #define LCCR0_OUM (1 << 21)
137 #define LCCR0_LCDT (1 << 22)
138 #define LCCR0_RDSTM (1 << 23)
139 #define LCCR0_CMDIM (1 << 24)
140 #define LCCR0_OUC (1 << 25)
141 #define LCCR0_LDDALT (1 << 26)
142 #define LCCR1_PPL(x) ((x) & 0x3ff)
143 #define LCCR2_LPP(x) ((x) & 0x3ff)
144 #define LCCR3_API (15 << 16)
145 #define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
146 #define LCCR3_PDFOR(x) (((x) >> 30) & 3)
147 #define LCCR4_K1(x) (((x) >> 0) & 7)
148 #define LCCR4_K2(x) (((x) >> 3) & 7)
149 #define LCCR4_K3(x) (((x) >> 6) & 7)
150 #define LCCR4_PALFOR(x) (((x) >> 15) & 3)
151 #define LCCR5_SOFM(ch) (1 << (ch - 1))
152 #define LCCR5_EOFM(ch) (1 << (ch + 7))
153 #define LCCR5_BSM(ch) (1 << (ch + 15))
154 #define LCCR5_IUM(ch) (1 << (ch + 23))
155 #define OVLC1_EN (1 << 31)
156 #define CCR_CEN (1 << 31)
157 #define FBR_BRA (1 << 0)
158 #define FBR_BINT (1 << 1)
159 #define FBR_SRCADDR (0xfffffff << 4)
160 #define LCSR0_LDD (1 << 0)
161 #define LCSR0_SOF0 (1 << 1)
162 #define LCSR0_BER (1 << 2)
163 #define LCSR0_ABC (1 << 3)
164 #define LCSR0_IU0 (1 << 4)
165 #define LCSR0_IU1 (1 << 5)
166 #define LCSR0_OU (1 << 6)
167 #define LCSR0_QD (1 << 7)
168 #define LCSR0_EOF0 (1 << 8)
169 #define LCSR0_BS0 (1 << 9)
170 #define LCSR0_SINT (1 << 10)
171 #define LCSR0_RDST (1 << 11)
172 #define LCSR0_CMDINT (1 << 12)
173 #define LCSR0_BERCH(x) (((x) & 7) << 28)
174 #define LCSR1_SOF(ch) (1 << (ch - 1))
175 #define LCSR1_EOF(ch) (1 << (ch + 7))
176 #define LCSR1_BS(ch) (1 << (ch + 15))
177 #define LCSR1_IU(ch) (1 << (ch + 23))
178 #define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
179 #define LDCMD_EOFINT (1 << 21)
180 #define LDCMD_SOFINT (1 << 22)
181 #define LDCMD_PAL (1 << 26)
182
183 /* Route internal interrupt lines to the global IC */
184 static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
185 {
186 int level = 0;
187 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
188 level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
189 level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
190 level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
191 level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
192 level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
193 level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
194 level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
195 level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
196 level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
197 level |= (s->status[1] & ~s->control[5]);
198
199 qemu_set_irq(s->irq, !!level);
200 s->irqlevel = level;
201 }
202
203 /* Set Branch Status interrupt high and poke associated registers */
204 static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch)
205 {
206 int unmasked;
207 if (ch == 0) {
208 s->status[0] |= LCSR0_BS0;
209 unmasked = !(s->control[0] & LCCR0_BSM0);
210 } else {
211 s->status[1] |= LCSR1_BS(ch);
212 unmasked = !(s->control[5] & LCCR5_BSM(ch));
213 }
214
215 if (unmasked) {
216 if (s->irqlevel)
217 s->status[0] |= LCSR0_SINT;
218 else
219 s->liidr = s->dma_ch[ch].id;
220 }
221 }
222
223 /* Set Start Of Frame Status interrupt high and poke associated registers */
224 static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch)
225 {
226 int unmasked;
227 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
228 return;
229
230 if (ch == 0) {
231 s->status[0] |= LCSR0_SOF0;
232 unmasked = !(s->control[0] & LCCR0_SOFM0);
233 } else {
234 s->status[1] |= LCSR1_SOF(ch);
235 unmasked = !(s->control[5] & LCCR5_SOFM(ch));
236 }
237
238 if (unmasked) {
239 if (s->irqlevel)
240 s->status[0] |= LCSR0_SINT;
241 else
242 s->liidr = s->dma_ch[ch].id;
243 }
244 }
245
246 /* Set End Of Frame Status interrupt high and poke associated registers */
247 static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch)
248 {
249 int unmasked;
250 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
251 return;
252
253 if (ch == 0) {
254 s->status[0] |= LCSR0_EOF0;
255 unmasked = !(s->control[0] & LCCR0_EOFM0);
256 } else {
257 s->status[1] |= LCSR1_EOF(ch);
258 unmasked = !(s->control[5] & LCCR5_EOFM(ch));
259 }
260
261 if (unmasked) {
262 if (s->irqlevel)
263 s->status[0] |= LCSR0_SINT;
264 else
265 s->liidr = s->dma_ch[ch].id;
266 }
267 }
268
269 /* Set Bus Error Status interrupt high and poke associated registers */
270 static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch)
271 {
272 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
273 if (s->irqlevel)
274 s->status[0] |= LCSR0_SINT;
275 else
276 s->liidr = s->dma_ch[ch].id;
277 }
278
279 /* Set Read Status interrupt high and poke associated registers */
280 static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
281 {
282 s->status[0] |= LCSR0_RDST;
283 if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
284 s->status[0] |= LCSR0_SINT;
285 }
286
287 /* Load new Frame Descriptors from DMA */
288 static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
289 {
290 PXAFrameDescriptor desc;
291 target_phys_addr_t descptr;
292 int i;
293
294 for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
295 s->dma_ch[i].source = 0;
296
297 if (!s->dma_ch[i].up)
298 continue;
299
300 if (s->dma_ch[i].branch & FBR_BRA) {
301 descptr = s->dma_ch[i].branch & FBR_SRCADDR;
302 if (s->dma_ch[i].branch & FBR_BINT)
303 pxa2xx_dma_bs_set(s, i);
304 s->dma_ch[i].branch &= ~FBR_BRA;
305 } else
306 descptr = s->dma_ch[i].descriptor;
307
308 if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
309 sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size))
310 continue;
311
312 cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc));
313 s->dma_ch[i].descriptor = tswap32(desc.fdaddr);
314 s->dma_ch[i].source = tswap32(desc.fsaddr);
315 s->dma_ch[i].id = tswap32(desc.fidr);
316 s->dma_ch[i].command = tswap32(desc.ldcmd);
317 }
318 }
319
320 static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset,
321 unsigned size)
322 {
323 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
324 int ch;
325
326 switch (offset) {
327 case LCCR0:
328 return s->control[0];
329 case LCCR1:
330 return s->control[1];
331 case LCCR2:
332 return s->control[2];
333 case LCCR3:
334 return s->control[3];
335 case LCCR4:
336 return s->control[4];
337 case LCCR5:
338 return s->control[5];
339
340 case OVL1C1:
341 return s->ovl1c[0];
342 case OVL1C2:
343 return s->ovl1c[1];
344 case OVL2C1:
345 return s->ovl2c[0];
346 case OVL2C2:
347 return s->ovl2c[1];
348
349 case CCR:
350 return s->ccr;
351
352 case CMDCR:
353 return s->cmdcr;
354
355 case TRGBR:
356 return s->trgbr;
357 case TCR:
358 return s->tcr;
359
360 case 0x200 ... 0x1000: /* DMA per-channel registers */
361 ch = (offset - 0x200) >> 4;
362 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
363 goto fail;
364
365 switch (offset & 0xf) {
366 case DMA_FDADR:
367 return s->dma_ch[ch].descriptor;
368 case DMA_FSADR:
369 return s->dma_ch[ch].source;
370 case DMA_FIDR:
371 return s->dma_ch[ch].id;
372 case DMA_LDCMD:
373 return s->dma_ch[ch].command;
374 default:
375 goto fail;
376 }
377
378 case FBR0:
379 return s->dma_ch[0].branch;
380 case FBR1:
381 return s->dma_ch[1].branch;
382 case FBR2:
383 return s->dma_ch[2].branch;
384 case FBR3:
385 return s->dma_ch[3].branch;
386 case FBR4:
387 return s->dma_ch[4].branch;
388 case FBR5:
389 return s->dma_ch[5].branch;
390 case FBR6:
391 return s->dma_ch[6].branch;
392
393 case BSCNTR:
394 return s->bscntr;
395
396 case PRSR:
397 return 0;
398
399 case LCSR0:
400 return s->status[0];
401 case LCSR1:
402 return s->status[1];
403 case LIIDR:
404 return s->liidr;
405
406 default:
407 fail:
408 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
409 }
410
411 return 0;
412 }
413
414 static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset,
415 uint64_t value, unsigned size)
416 {
417 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
418 int ch;
419
420 switch (offset) {
421 case LCCR0:
422 /* ACK Quick Disable done */
423 if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
424 s->status[0] |= LCSR0_QD;
425
426 if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
427 printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
428
429 if ((s->control[3] & LCCR3_API) &&
430 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
431 s->status[0] |= LCSR0_ABC;
432
433 s->control[0] = value & 0x07ffffff;
434 pxa2xx_lcdc_int_update(s);
435
436 s->dma_ch[0].up = !!(value & LCCR0_ENB);
437 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
438 break;
439
440 case LCCR1:
441 s->control[1] = value;
442 break;
443
444 case LCCR2:
445 s->control[2] = value;
446 break;
447
448 case LCCR3:
449 s->control[3] = value & 0xefffffff;
450 s->bpp = LCCR3_BPP(value);
451 break;
452
453 case LCCR4:
454 s->control[4] = value & 0x83ff81ff;
455 break;
456
457 case LCCR5:
458 s->control[5] = value & 0x3f3f3f3f;
459 break;
460
461 case OVL1C1:
462 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
463 printf("%s: Overlay 1 not supported\n", __FUNCTION__);
464
465 s->ovl1c[0] = value & 0x80ffffff;
466 s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
467 break;
468
469 case OVL1C2:
470 s->ovl1c[1] = value & 0x000fffff;
471 break;
472
473 case OVL2C1:
474 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
475 printf("%s: Overlay 2 not supported\n", __FUNCTION__);
476
477 s->ovl2c[0] = value & 0x80ffffff;
478 s->dma_ch[2].up = !!(value & OVLC1_EN);
479 s->dma_ch[3].up = !!(value & OVLC1_EN);
480 s->dma_ch[4].up = !!(value & OVLC1_EN);
481 break;
482
483 case OVL2C2:
484 s->ovl2c[1] = value & 0x007fffff;
485 break;
486
487 case CCR:
488 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
489 printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
490
491 s->ccr = value & 0x81ffffe7;
492 s->dma_ch[5].up = !!(value & CCR_CEN);
493 break;
494
495 case CMDCR:
496 s->cmdcr = value & 0xff;
497 break;
498
499 case TRGBR:
500 s->trgbr = value & 0x00ffffff;
501 break;
502
503 case TCR:
504 s->tcr = value & 0x7fff;
505 break;
506
507 case 0x200 ... 0x1000: /* DMA per-channel registers */
508 ch = (offset - 0x200) >> 4;
509 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
510 goto fail;
511
512 switch (offset & 0xf) {
513 case DMA_FDADR:
514 s->dma_ch[ch].descriptor = value & 0xfffffff0;
515 break;
516
517 default:
518 goto fail;
519 }
520 break;
521
522 case FBR0:
523 s->dma_ch[0].branch = value & 0xfffffff3;
524 break;
525 case FBR1:
526 s->dma_ch[1].branch = value & 0xfffffff3;
527 break;
528 case FBR2:
529 s->dma_ch[2].branch = value & 0xfffffff3;
530 break;
531 case FBR3:
532 s->dma_ch[3].branch = value & 0xfffffff3;
533 break;
534 case FBR4:
535 s->dma_ch[4].branch = value & 0xfffffff3;
536 break;
537 case FBR5:
538 s->dma_ch[5].branch = value & 0xfffffff3;
539 break;
540 case FBR6:
541 s->dma_ch[6].branch = value & 0xfffffff3;
542 break;
543
544 case BSCNTR:
545 s->bscntr = value & 0xf;
546 break;
547
548 case PRSR:
549 break;
550
551 case LCSR0:
552 s->status[0] &= ~(value & 0xfff);
553 if (value & LCSR0_BER)
554 s->status[0] &= ~LCSR0_BERCH(7);
555 break;
556
557 case LCSR1:
558 s->status[1] &= ~(value & 0x3e3f3f);
559 break;
560
561 default:
562 fail:
563 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
564 }
565 }
566
567 static const MemoryRegionOps pxa2xx_lcdc_ops = {
568 .read = pxa2xx_lcdc_read,
569 .write = pxa2xx_lcdc_write,
570 .endianness = DEVICE_NATIVE_ENDIAN,
571 };
572
573 /* Load new palette for a given DMA channel, convert to internal format */
574 static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
575 {
576 int i, n, format, r, g, b, alpha;
577 uint32_t *dest, *src;
578 s->pal_for = LCCR4_PALFOR(s->control[4]);
579 format = s->pal_for;
580
581 switch (bpp) {
582 case pxa_lcdc_2bpp:
583 n = 4;
584 break;
585 case pxa_lcdc_4bpp:
586 n = 16;
587 break;
588 case pxa_lcdc_8bpp:
589 n = 256;
590 break;
591 default:
592 format = 0;
593 return;
594 }
595
596 src = (uint32_t *) s->dma_ch[ch].pbuffer;
597 dest = (uint32_t *) s->dma_ch[ch].palette;
598 alpha = r = g = b = 0;
599
600 for (i = 0; i < n; i ++) {
601 switch (format) {
602 case 0: /* 16 bpp, no transparency */
603 alpha = 0;
604 if (s->control[0] & LCCR0_CMS)
605 r = g = b = *src & 0xff;
606 else {
607 r = (*src & 0xf800) >> 8;
608 g = (*src & 0x07e0) >> 3;
609 b = (*src & 0x001f) << 3;
610 }
611 break;
612 case 1: /* 16 bpp plus transparency */
613 alpha = *src & (1 << 24);
614 if (s->control[0] & LCCR0_CMS)
615 r = g = b = *src & 0xff;
616 else {
617 r = (*src & 0xf800) >> 8;
618 g = (*src & 0x07e0) >> 3;
619 b = (*src & 0x001f) << 3;
620 }
621 break;
622 case 2: /* 18 bpp plus transparency */
623 alpha = *src & (1 << 24);
624 if (s->control[0] & LCCR0_CMS)
625 r = g = b = *src & 0xff;
626 else {
627 r = (*src & 0xf80000) >> 16;
628 g = (*src & 0x00fc00) >> 8;
629 b = (*src & 0x0000f8);
630 }
631 break;
632 case 3: /* 24 bpp plus transparency */
633 alpha = *src & (1 << 24);
634 if (s->control[0] & LCCR0_CMS)
635 r = g = b = *src & 0xff;
636 else {
637 r = (*src & 0xff0000) >> 16;
638 g = (*src & 0x00ff00) >> 8;
639 b = (*src & 0x0000ff);
640 }
641 break;
642 }
643 switch (ds_get_bits_per_pixel(s->ds)) {
644 case 8:
645 *dest = rgb_to_pixel8(r, g, b) | alpha;
646 break;
647 case 15:
648 *dest = rgb_to_pixel15(r, g, b) | alpha;
649 break;
650 case 16:
651 *dest = rgb_to_pixel16(r, g, b) | alpha;
652 break;
653 case 24:
654 *dest = rgb_to_pixel24(r, g, b) | alpha;
655 break;
656 case 32:
657 *dest = rgb_to_pixel32(r, g, b) | alpha;
658 break;
659 }
660 src ++;
661 dest ++;
662 }
663 }
664
665 static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
666 target_phys_addr_t addr, int *miny, int *maxy)
667 {
668 int src_width, dest_width;
669 drawfn fn = NULL;
670 if (s->dest_width)
671 fn = s->line_fn[s->transp][s->bpp];
672 if (!fn)
673 return;
674
675 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
676 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
677 src_width *= 3;
678 else if (s->bpp > pxa_lcdc_16bpp)
679 src_width *= 4;
680 else if (s->bpp > pxa_lcdc_8bpp)
681 src_width *= 2;
682
683 dest_width = s->xres * s->dest_width;
684 *miny = 0;
685 framebuffer_update_display(s->ds, s->sysmem,
686 addr, s->xres, s->yres,
687 src_width, dest_width, s->dest_width,
688 s->invalidated,
689 fn, s->dma_ch[0].palette, miny, maxy);
690 }
691
692 static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
693 target_phys_addr_t addr, int *miny, int *maxy)
694 {
695 int src_width, dest_width;
696 drawfn fn = NULL;
697 if (s->dest_width)
698 fn = s->line_fn[s->transp][s->bpp];
699 if (!fn)
700 return;
701
702 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
703 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
704 src_width *= 3;
705 else if (s->bpp > pxa_lcdc_16bpp)
706 src_width *= 4;
707 else if (s->bpp > pxa_lcdc_8bpp)
708 src_width *= 2;
709
710 dest_width = s->yres * s->dest_width;
711 *miny = 0;
712 framebuffer_update_display(s->ds, s->sysmem,
713 addr, s->xres, s->yres,
714 src_width, s->dest_width, -dest_width,
715 s->invalidated,
716 fn, s->dma_ch[0].palette,
717 miny, maxy);
718 }
719
720 static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
721 target_phys_addr_t addr, int *miny, int *maxy)
722 {
723 int src_width, dest_width;
724 drawfn fn = NULL;
725 if (s->dest_width) {
726 fn = s->line_fn[s->transp][s->bpp];
727 }
728 if (!fn) {
729 return;
730 }
731
732 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
733 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
734 src_width *= 3;
735 } else if (s->bpp > pxa_lcdc_16bpp) {
736 src_width *= 4;
737 } else if (s->bpp > pxa_lcdc_8bpp) {
738 src_width *= 2;
739 }
740
741 dest_width = s->xres * s->dest_width;
742 *miny = 0;
743 framebuffer_update_display(s->ds, s->sysmem,
744 addr, s->xres, s->yres,
745 src_width, -dest_width, -s->dest_width,
746 s->invalidated,
747 fn, s->dma_ch[0].palette, miny, maxy);
748 }
749
750 static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
751 target_phys_addr_t addr, int *miny, int *maxy)
752 {
753 int src_width, dest_width;
754 drawfn fn = NULL;
755 if (s->dest_width) {
756 fn = s->line_fn[s->transp][s->bpp];
757 }
758 if (!fn) {
759 return;
760 }
761
762 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
763 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
764 src_width *= 3;
765 } else if (s->bpp > pxa_lcdc_16bpp) {
766 src_width *= 4;
767 } else if (s->bpp > pxa_lcdc_8bpp) {
768 src_width *= 2;
769 }
770
771 dest_width = s->yres * s->dest_width;
772 *miny = 0;
773 framebuffer_update_display(s->ds, s->sysmem,
774 addr, s->xres, s->yres,
775 src_width, -s->dest_width, dest_width,
776 s->invalidated,
777 fn, s->dma_ch[0].palette,
778 miny, maxy);
779 }
780
781 static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
782 {
783 int width, height;
784 if (!(s->control[0] & LCCR0_ENB))
785 return;
786
787 width = LCCR1_PPL(s->control[1]) + 1;
788 height = LCCR2_LPP(s->control[2]) + 1;
789
790 if (width != s->xres || height != s->yres) {
791 if (s->orientation == 90 || s->orientation == 270) {
792 qemu_console_resize(s->ds, height, width);
793 } else {
794 qemu_console_resize(s->ds, width, height);
795 }
796 s->invalidated = 1;
797 s->xres = width;
798 s->yres = height;
799 }
800 }
801
802 static void pxa2xx_update_display(void *opaque)
803 {
804 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
805 target_phys_addr_t fbptr;
806 int miny, maxy;
807 int ch;
808 if (!(s->control[0] & LCCR0_ENB))
809 return;
810
811 pxa2xx_descriptor_load(s);
812
813 pxa2xx_lcdc_resize(s);
814 miny = s->yres;
815 maxy = 0;
816 s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
817 /* Note: With overlay planes the order depends on LCCR0 bit 25. */
818 for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
819 if (s->dma_ch[ch].up) {
820 if (!s->dma_ch[ch].source) {
821 pxa2xx_dma_ber_set(s, ch);
822 continue;
823 }
824 fbptr = s->dma_ch[ch].source;
825 if (!(fbptr >= PXA2XX_SDRAM_BASE &&
826 fbptr <= PXA2XX_SDRAM_BASE + ram_size)) {
827 pxa2xx_dma_ber_set(s, ch);
828 continue;
829 }
830
831 if (s->dma_ch[ch].command & LDCMD_PAL) {
832 cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer,
833 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
834 sizeof(s->dma_ch[ch].pbuffer)));
835 pxa2xx_palette_parse(s, ch, s->bpp);
836 } else {
837 /* Do we need to reparse palette */
838 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
839 pxa2xx_palette_parse(s, ch, s->bpp);
840
841 /* ACK frame start */
842 pxa2xx_dma_sof_set(s, ch);
843
844 s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy);
845 s->invalidated = 0;
846
847 /* ACK frame completed */
848 pxa2xx_dma_eof_set(s, ch);
849 }
850 }
851
852 if (s->control[0] & LCCR0_DIS) {
853 /* ACK last frame completed */
854 s->control[0] &= ~LCCR0_ENB;
855 s->status[0] |= LCSR0_LDD;
856 }
857
858 if (miny >= 0) {
859 switch (s->orientation) {
860 case 0:
861 dpy_update(s->ds, 0, miny, s->xres, maxy - miny + 1);
862 break;
863 case 90:
864 dpy_update(s->ds, miny, 0, maxy - miny + 1, s->xres);
865 break;
866 case 180:
867 maxy = s->yres - maxy - 1;
868 miny = s->yres - miny - 1;
869 dpy_update(s->ds, 0, maxy, s->xres, miny - maxy + 1);
870 break;
871 case 270:
872 maxy = s->yres - maxy - 1;
873 miny = s->yres - miny - 1;
874 dpy_update(s->ds, maxy, 0, miny - maxy + 1, s->xres);
875 break;
876 }
877 }
878 pxa2xx_lcdc_int_update(s);
879
880 qemu_irq_raise(s->vsync_cb);
881 }
882
883 static void pxa2xx_invalidate_display(void *opaque)
884 {
885 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
886 s->invalidated = 1;
887 }
888
889 static void pxa2xx_screen_dump(void *opaque, const char *filename)
890 {
891 /* TODO */
892 }
893
894 static void pxa2xx_lcdc_orientation(void *opaque, int angle)
895 {
896 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
897
898 switch (angle) {
899 case 0:
900 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot0;
901 break;
902 case 90:
903 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot90;
904 break;
905 case 180:
906 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot180;
907 break;
908 case 270:
909 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot270;
910 break;
911 }
912
913 s->orientation = angle;
914 s->xres = s->yres = -1;
915 pxa2xx_lcdc_resize(s);
916 }
917
918 static const VMStateDescription vmstate_dma_channel = {
919 .name = "dma_channel",
920 .version_id = 0,
921 .minimum_version_id = 0,
922 .minimum_version_id_old = 0,
923 .fields = (VMStateField[]) {
924 VMSTATE_UINTTL(branch, struct DMAChannel),
925 VMSTATE_UINT8(up, struct DMAChannel),
926 VMSTATE_BUFFER(pbuffer, struct DMAChannel),
927 VMSTATE_UINTTL(descriptor, struct DMAChannel),
928 VMSTATE_UINTTL(source, struct DMAChannel),
929 VMSTATE_UINT32(id, struct DMAChannel),
930 VMSTATE_UINT32(command, struct DMAChannel),
931 VMSTATE_END_OF_LIST()
932 }
933 };
934
935 static int pxa2xx_lcdc_post_load(void *opaque, int version_id)
936 {
937 PXA2xxLCDState *s = opaque;
938
939 s->bpp = LCCR3_BPP(s->control[3]);
940 s->xres = s->yres = s->pal_for = -1;
941
942 return 0;
943 }
944
945 static const VMStateDescription vmstate_pxa2xx_lcdc = {
946 .name = "pxa2xx_lcdc",
947 .version_id = 0,
948 .minimum_version_id = 0,
949 .minimum_version_id_old = 0,
950 .post_load = pxa2xx_lcdc_post_load,
951 .fields = (VMStateField[]) {
952 VMSTATE_INT32(irqlevel, PXA2xxLCDState),
953 VMSTATE_INT32(transp, PXA2xxLCDState),
954 VMSTATE_UINT32_ARRAY(control, PXA2xxLCDState, 6),
955 VMSTATE_UINT32_ARRAY(status, PXA2xxLCDState, 2),
956 VMSTATE_UINT32_ARRAY(ovl1c, PXA2xxLCDState, 2),
957 VMSTATE_UINT32_ARRAY(ovl2c, PXA2xxLCDState, 2),
958 VMSTATE_UINT32(ccr, PXA2xxLCDState),
959 VMSTATE_UINT32(cmdcr, PXA2xxLCDState),
960 VMSTATE_UINT32(trgbr, PXA2xxLCDState),
961 VMSTATE_UINT32(tcr, PXA2xxLCDState),
962 VMSTATE_UINT32(liidr, PXA2xxLCDState),
963 VMSTATE_UINT8(bscntr, PXA2xxLCDState),
964 VMSTATE_STRUCT_ARRAY(dma_ch, PXA2xxLCDState, 7, 0,
965 vmstate_dma_channel, struct DMAChannel),
966 VMSTATE_END_OF_LIST()
967 }
968 };
969
970 #define BITS 8
971 #include "pxa2xx_template.h"
972 #define BITS 15
973 #include "pxa2xx_template.h"
974 #define BITS 16
975 #include "pxa2xx_template.h"
976 #define BITS 24
977 #include "pxa2xx_template.h"
978 #define BITS 32
979 #include "pxa2xx_template.h"
980
981 PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
982 target_phys_addr_t base, qemu_irq irq)
983 {
984 PXA2xxLCDState *s;
985
986 s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState));
987 s->invalidated = 1;
988 s->irq = irq;
989 s->sysmem = sysmem;
990
991 pxa2xx_lcdc_orientation(s, graphic_rotate);
992
993 memory_region_init_io(&s->iomem, &pxa2xx_lcdc_ops, s,
994 "pxa2xx-lcd-controller", 0x00100000);
995 memory_region_add_subregion(sysmem, base, &s->iomem);
996
997 s->ds = graphic_console_init(pxa2xx_update_display,
998 pxa2xx_invalidate_display,
999 pxa2xx_screen_dump, NULL, s);
1000
1001 switch (ds_get_bits_per_pixel(s->ds)) {
1002 case 0:
1003 s->dest_width = 0;
1004 break;
1005 case 8:
1006 s->line_fn[0] = pxa2xx_draw_fn_8;
1007 s->line_fn[1] = pxa2xx_draw_fn_8t;
1008 s->dest_width = 1;
1009 break;
1010 case 15:
1011 s->line_fn[0] = pxa2xx_draw_fn_15;
1012 s->line_fn[1] = pxa2xx_draw_fn_15t;
1013 s->dest_width = 2;
1014 break;
1015 case 16:
1016 s->line_fn[0] = pxa2xx_draw_fn_16;
1017 s->line_fn[1] = pxa2xx_draw_fn_16t;
1018 s->dest_width = 2;
1019 break;
1020 case 24:
1021 s->line_fn[0] = pxa2xx_draw_fn_24;
1022 s->line_fn[1] = pxa2xx_draw_fn_24t;
1023 s->dest_width = 3;
1024 break;
1025 case 32:
1026 s->line_fn[0] = pxa2xx_draw_fn_32;
1027 s->line_fn[1] = pxa2xx_draw_fn_32t;
1028 s->dest_width = 4;
1029 break;
1030 default:
1031 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
1032 exit(1);
1033 }
1034
1035 vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s);
1036
1037 return s;
1038 }
1039
1040 void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
1041 {
1042 s->vsync_cb = handler;
1043 }
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