2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "qemu-queue.h"
31 #undef SPICE_RING_PROD_ITEM
32 #define SPICE_RING_PROD_ITEM(r, ret) { \
33 typeof(r) start = r; \
34 typeof(r) end = r + 1; \
35 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
36 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
37 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
43 #undef SPICE_RING_CONS_ITEM
44 #define SPICE_RING_CONS_ITEM(r, ret) { \
45 typeof(r) start = r; \
46 typeof(r) end = r + 1; \
47 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
48 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
49 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
56 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
58 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
60 #define QXL_MODE(_x, _y, _b, _o) \
64 .stride = (_x) * (_b) / 8, \
65 .x_mili = PIXEL_SIZE * (_x), \
66 .y_mili = PIXEL_SIZE * (_y), \
70 #define QXL_MODE_16_32(x_res, y_res, orientation) \
71 QXL_MODE(x_res, y_res, 16, orientation), \
72 QXL_MODE(x_res, y_res, 32, orientation)
74 #define QXL_MODE_EX(x_res, y_res) \
75 QXL_MODE_16_32(x_res, y_res, 0), \
76 QXL_MODE_16_32(y_res, x_res, 1), \
77 QXL_MODE_16_32(x_res, y_res, 2), \
78 QXL_MODE_16_32(y_res, x_res, 3)
80 static QXLMode qxl_modes
[] = {
81 QXL_MODE_EX(640, 480),
82 QXL_MODE_EX(800, 480),
83 QXL_MODE_EX(800, 600),
84 QXL_MODE_EX(832, 624),
85 QXL_MODE_EX(960, 640),
86 QXL_MODE_EX(1024, 600),
87 QXL_MODE_EX(1024, 768),
88 QXL_MODE_EX(1152, 864),
89 QXL_MODE_EX(1152, 870),
90 QXL_MODE_EX(1280, 720),
91 QXL_MODE_EX(1280, 760),
92 QXL_MODE_EX(1280, 768),
93 QXL_MODE_EX(1280, 800),
94 QXL_MODE_EX(1280, 960),
95 QXL_MODE_EX(1280, 1024),
96 QXL_MODE_EX(1360, 768),
97 QXL_MODE_EX(1366, 768),
98 QXL_MODE_EX(1400, 1050),
99 QXL_MODE_EX(1440, 900),
100 QXL_MODE_EX(1600, 900),
101 QXL_MODE_EX(1600, 1200),
102 QXL_MODE_EX(1680, 1050),
103 QXL_MODE_EX(1920, 1080),
104 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
105 /* these modes need more than 8 MB video memory */
106 QXL_MODE_EX(1920, 1200),
107 QXL_MODE_EX(1920, 1440),
108 QXL_MODE_EX(2048, 1536),
109 QXL_MODE_EX(2560, 1440),
110 QXL_MODE_EX(2560, 1600),
112 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
113 /* these modes need more than 16 MB video memory */
114 QXL_MODE_EX(2560, 2048),
115 QXL_MODE_EX(2800, 2100),
116 QXL_MODE_EX(3200, 2400),
120 static PCIQXLDevice
*qxl0
;
122 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
);
123 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
);
124 static void qxl_reset_memslots(PCIQXLDevice
*d
);
125 static void qxl_reset_surfaces(PCIQXLDevice
*d
);
126 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
);
128 void qxl_guest_bug(PCIQXLDevice
*qxl
, const char *msg
, ...)
130 #if SPICE_INTERFACE_QXL_MINOR >= 1
131 qxl_send_events(qxl
, QXL_INTERRUPT_ERROR
);
133 if (qxl
->guestdebug
) {
136 fprintf(stderr
, "qxl-%d: guest bug: ", qxl
->id
);
137 vfprintf(stderr
, msg
, ap
);
138 fprintf(stderr
, "\n");
144 void qxl_spice_update_area(PCIQXLDevice
*qxl
, uint32_t surface_id
,
145 struct QXLRect
*area
, struct QXLRect
*dirty_rects
,
146 uint32_t num_dirty_rects
,
147 uint32_t clear_dirty_region
,
150 if (async
== QXL_SYNC
) {
151 qxl
->ssd
.worker
->update_area(qxl
->ssd
.worker
, surface_id
, area
,
152 dirty_rects
, num_dirty_rects
, clear_dirty_region
);
154 #if SPICE_INTERFACE_QXL_MINOR >= 1
155 spice_qxl_update_area_async(&qxl
->ssd
.qxl
, surface_id
, area
,
156 clear_dirty_region
, 0);
163 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice
*qxl
,
166 qemu_mutex_lock(&qxl
->track_lock
);
167 qxl
->guest_surfaces
.cmds
[id
] = 0;
168 qxl
->guest_surfaces
.count
--;
169 qemu_mutex_unlock(&qxl
->track_lock
);
172 static void qxl_spice_destroy_surface_wait(PCIQXLDevice
*qxl
, uint32_t id
,
176 #if SPICE_INTERFACE_QXL_MINOR < 1
179 spice_qxl_destroy_surface_async(&qxl
->ssd
.qxl
, id
,
183 qxl
->ssd
.worker
->destroy_surface_wait(qxl
->ssd
.worker
, id
);
184 qxl_spice_destroy_surface_wait_complete(qxl
, id
);
188 #if SPICE_INTERFACE_QXL_MINOR >= 1
189 static void qxl_spice_flush_surfaces_async(PCIQXLDevice
*qxl
)
191 spice_qxl_flush_surfaces_async(&qxl
->ssd
.qxl
, 0);
195 void qxl_spice_loadvm_commands(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
,
198 qxl
->ssd
.worker
->loadvm_commands(qxl
->ssd
.worker
, ext
, count
);
201 void qxl_spice_oom(PCIQXLDevice
*qxl
)
203 qxl
->ssd
.worker
->oom(qxl
->ssd
.worker
);
206 void qxl_spice_reset_memslots(PCIQXLDevice
*qxl
)
208 qxl
->ssd
.worker
->reset_memslots(qxl
->ssd
.worker
);
211 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice
*qxl
)
213 qemu_mutex_lock(&qxl
->track_lock
);
214 memset(&qxl
->guest_surfaces
.cmds
, 0, sizeof(qxl
->guest_surfaces
.cmds
));
215 qxl
->guest_surfaces
.count
= 0;
216 qemu_mutex_unlock(&qxl
->track_lock
);
219 static void qxl_spice_destroy_surfaces(PCIQXLDevice
*qxl
, qxl_async_io async
)
222 #if SPICE_INTERFACE_QXL_MINOR < 1
225 spice_qxl_destroy_surfaces_async(&qxl
->ssd
.qxl
, 0);
228 qxl
->ssd
.worker
->destroy_surfaces(qxl
->ssd
.worker
);
229 qxl_spice_destroy_surfaces_complete(qxl
);
233 void qxl_spice_reset_image_cache(PCIQXLDevice
*qxl
)
235 qxl
->ssd
.worker
->reset_image_cache(qxl
->ssd
.worker
);
238 void qxl_spice_reset_cursor(PCIQXLDevice
*qxl
)
240 qxl
->ssd
.worker
->reset_cursor(qxl
->ssd
.worker
);
244 static inline uint32_t msb_mask(uint32_t val
)
249 mask
= ~(val
- 1) & val
;
251 } while (mask
< val
);
256 static ram_addr_t
qxl_rom_size(void)
258 uint32_t rom_size
= sizeof(QXLRom
) + sizeof(QXLModes
) + sizeof(qxl_modes
);
259 rom_size
= MAX(rom_size
, TARGET_PAGE_SIZE
);
260 rom_size
= msb_mask(rom_size
* 2 - 1);
264 static void init_qxl_rom(PCIQXLDevice
*d
)
266 QXLRom
*rom
= memory_region_get_ram_ptr(&d
->rom_bar
);
267 QXLModes
*modes
= (QXLModes
*)(rom
+ 1);
268 uint32_t ram_header_size
;
269 uint32_t surface0_area_size
;
271 uint32_t fb
, maxfb
= 0;
274 memset(rom
, 0, d
->rom_size
);
276 rom
->magic
= cpu_to_le32(QXL_ROM_MAGIC
);
277 rom
->id
= cpu_to_le32(d
->id
);
278 rom
->log_level
= cpu_to_le32(d
->guestdebug
);
279 rom
->modes_offset
= cpu_to_le32(sizeof(QXLRom
));
281 rom
->slot_gen_bits
= MEMSLOT_GENERATION_BITS
;
282 rom
->slot_id_bits
= MEMSLOT_SLOT_BITS
;
283 rom
->slots_start
= 1;
284 rom
->slots_end
= NUM_MEMSLOTS
- 1;
285 rom
->n_surfaces
= cpu_to_le32(NUM_SURFACES
);
287 modes
->n_modes
= cpu_to_le32(ARRAY_SIZE(qxl_modes
));
288 for (i
= 0; i
< modes
->n_modes
; i
++) {
289 fb
= qxl_modes
[i
].y_res
* qxl_modes
[i
].stride
;
293 modes
->modes
[i
].id
= cpu_to_le32(i
);
294 modes
->modes
[i
].x_res
= cpu_to_le32(qxl_modes
[i
].x_res
);
295 modes
->modes
[i
].y_res
= cpu_to_le32(qxl_modes
[i
].y_res
);
296 modes
->modes
[i
].bits
= cpu_to_le32(qxl_modes
[i
].bits
);
297 modes
->modes
[i
].stride
= cpu_to_le32(qxl_modes
[i
].stride
);
298 modes
->modes
[i
].x_mili
= cpu_to_le32(qxl_modes
[i
].x_mili
);
299 modes
->modes
[i
].y_mili
= cpu_to_le32(qxl_modes
[i
].y_mili
);
300 modes
->modes
[i
].orientation
= cpu_to_le32(qxl_modes
[i
].orientation
);
302 if (maxfb
< VGA_RAM_SIZE
&& d
->id
== 0)
303 maxfb
= VGA_RAM_SIZE
;
305 ram_header_size
= ALIGN(sizeof(QXLRam
), 4096);
306 surface0_area_size
= ALIGN(maxfb
, 4096);
307 num_pages
= d
->vga
.vram_size
;
308 num_pages
-= ram_header_size
;
309 num_pages
-= surface0_area_size
;
310 num_pages
= num_pages
/ TARGET_PAGE_SIZE
;
312 rom
->draw_area_offset
= cpu_to_le32(0);
313 rom
->surface0_area_size
= cpu_to_le32(surface0_area_size
);
314 rom
->pages_offset
= cpu_to_le32(surface0_area_size
);
315 rom
->num_pages
= cpu_to_le32(num_pages
);
316 rom
->ram_header_offset
= cpu_to_le32(d
->vga
.vram_size
- ram_header_size
);
318 d
->shadow_rom
= *rom
;
323 static void init_qxl_ram(PCIQXLDevice
*d
)
328 buf
= d
->vga
.vram_ptr
;
329 d
->ram
= (QXLRam
*)(buf
+ le32_to_cpu(d
->shadow_rom
.ram_header_offset
));
330 d
->ram
->magic
= cpu_to_le32(QXL_RAM_MAGIC
);
331 d
->ram
->int_pending
= cpu_to_le32(0);
332 d
->ram
->int_mask
= cpu_to_le32(0);
333 SPICE_RING_INIT(&d
->ram
->cmd_ring
);
334 SPICE_RING_INIT(&d
->ram
->cursor_ring
);
335 SPICE_RING_INIT(&d
->ram
->release_ring
);
336 SPICE_RING_PROD_ITEM(&d
->ram
->release_ring
, item
);
338 qxl_ring_set_dirty(d
);
341 /* can be called from spice server thread context */
342 static void qxl_set_dirty(MemoryRegion
*mr
, ram_addr_t addr
, ram_addr_t end
)
345 memory_region_set_dirty(mr
, addr
);
346 addr
+= TARGET_PAGE_SIZE
;
350 static void qxl_rom_set_dirty(PCIQXLDevice
*qxl
)
352 qxl_set_dirty(&qxl
->rom_bar
, 0, qxl
->rom_size
);
355 /* called from spice server thread context only */
356 static void qxl_ram_set_dirty(PCIQXLDevice
*qxl
, void *ptr
)
358 void *base
= qxl
->vga
.vram_ptr
;
362 offset
&= ~(TARGET_PAGE_SIZE
-1);
363 assert(offset
< qxl
->vga
.vram_size
);
364 qxl_set_dirty(&qxl
->vga
.vram
, offset
, offset
+ TARGET_PAGE_SIZE
);
367 /* can be called from spice server thread context */
368 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
)
370 ram_addr_t addr
= qxl
->shadow_rom
.ram_header_offset
;
371 ram_addr_t end
= qxl
->vga
.vram_size
;
372 qxl_set_dirty(&qxl
->vga
.vram
, addr
, end
);
376 * keep track of some command state, for savevm/loadvm.
377 * called from spice server thread context only
379 static void qxl_track_command(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
)
381 switch (le32_to_cpu(ext
->cmd
.type
)) {
382 case QXL_CMD_SURFACE
:
384 QXLSurfaceCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
385 uint32_t id
= le32_to_cpu(cmd
->surface_id
);
386 PANIC_ON(id
>= NUM_SURFACES
);
387 qemu_mutex_lock(&qxl
->track_lock
);
388 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
) {
389 qxl
->guest_surfaces
.cmds
[id
] = ext
->cmd
.data
;
390 qxl
->guest_surfaces
.count
++;
391 if (qxl
->guest_surfaces
.max
< qxl
->guest_surfaces
.count
)
392 qxl
->guest_surfaces
.max
= qxl
->guest_surfaces
.count
;
394 if (cmd
->type
== QXL_SURFACE_CMD_DESTROY
) {
395 qxl
->guest_surfaces
.cmds
[id
] = 0;
396 qxl
->guest_surfaces
.count
--;
398 qemu_mutex_unlock(&qxl
->track_lock
);
403 QXLCursorCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
404 if (cmd
->type
== QXL_CURSOR_SET
) {
405 qxl
->guest_cursor
= ext
->cmd
.data
;
412 /* spice display interface callbacks */
414 static void interface_attach_worker(QXLInstance
*sin
, QXLWorker
*qxl_worker
)
416 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
418 dprint(qxl
, 1, "%s:\n", __FUNCTION__
);
419 qxl
->ssd
.worker
= qxl_worker
;
422 static void interface_set_compression_level(QXLInstance
*sin
, int level
)
424 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
426 dprint(qxl
, 1, "%s: %d\n", __FUNCTION__
, level
);
427 qxl
->shadow_rom
.compression_level
= cpu_to_le32(level
);
428 qxl
->rom
->compression_level
= cpu_to_le32(level
);
429 qxl_rom_set_dirty(qxl
);
432 static void interface_set_mm_time(QXLInstance
*sin
, uint32_t mm_time
)
434 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
436 qxl
->shadow_rom
.mm_clock
= cpu_to_le32(mm_time
);
437 qxl
->rom
->mm_clock
= cpu_to_le32(mm_time
);
438 qxl_rom_set_dirty(qxl
);
441 static void interface_get_init_info(QXLInstance
*sin
, QXLDevInitInfo
*info
)
443 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
445 dprint(qxl
, 1, "%s:\n", __FUNCTION__
);
446 info
->memslot_gen_bits
= MEMSLOT_GENERATION_BITS
;
447 info
->memslot_id_bits
= MEMSLOT_SLOT_BITS
;
448 info
->num_memslots
= NUM_MEMSLOTS
;
449 info
->num_memslots_groups
= NUM_MEMSLOTS_GROUPS
;
450 info
->internal_groupslot_id
= 0;
451 info
->qxl_ram_size
= le32_to_cpu(qxl
->shadow_rom
.num_pages
) << TARGET_PAGE_BITS
;
452 info
->n_surfaces
= NUM_SURFACES
;
455 static const char *qxl_mode_to_string(int mode
)
458 case QXL_MODE_COMPAT
:
460 case QXL_MODE_NATIVE
:
462 case QXL_MODE_UNDEFINED
:
470 static const char *io_port_to_string(uint32_t io_port
)
472 if (io_port
>= QXL_IO_RANGE_SIZE
) {
473 return "out of range";
475 static const char *io_port_to_string
[QXL_IO_RANGE_SIZE
+ 1] = {
476 [QXL_IO_NOTIFY_CMD
] = "QXL_IO_NOTIFY_CMD",
477 [QXL_IO_NOTIFY_CURSOR
] = "QXL_IO_NOTIFY_CURSOR",
478 [QXL_IO_UPDATE_AREA
] = "QXL_IO_UPDATE_AREA",
479 [QXL_IO_UPDATE_IRQ
] = "QXL_IO_UPDATE_IRQ",
480 [QXL_IO_NOTIFY_OOM
] = "QXL_IO_NOTIFY_OOM",
481 [QXL_IO_RESET
] = "QXL_IO_RESET",
482 [QXL_IO_SET_MODE
] = "QXL_IO_SET_MODE",
483 [QXL_IO_LOG
] = "QXL_IO_LOG",
484 [QXL_IO_MEMSLOT_ADD
] = "QXL_IO_MEMSLOT_ADD",
485 [QXL_IO_MEMSLOT_DEL
] = "QXL_IO_MEMSLOT_DEL",
486 [QXL_IO_DETACH_PRIMARY
] = "QXL_IO_DETACH_PRIMARY",
487 [QXL_IO_ATTACH_PRIMARY
] = "QXL_IO_ATTACH_PRIMARY",
488 [QXL_IO_CREATE_PRIMARY
] = "QXL_IO_CREATE_PRIMARY",
489 [QXL_IO_DESTROY_PRIMARY
] = "QXL_IO_DESTROY_PRIMARY",
490 [QXL_IO_DESTROY_SURFACE_WAIT
] = "QXL_IO_DESTROY_SURFACE_WAIT",
491 [QXL_IO_DESTROY_ALL_SURFACES
] = "QXL_IO_DESTROY_ALL_SURFACES",
492 #if SPICE_INTERFACE_QXL_MINOR >= 1
493 [QXL_IO_UPDATE_AREA_ASYNC
] = "QXL_IO_UPDATE_AREA_ASYNC",
494 [QXL_IO_MEMSLOT_ADD_ASYNC
] = "QXL_IO_MEMSLOT_ADD_ASYNC",
495 [QXL_IO_CREATE_PRIMARY_ASYNC
] = "QXL_IO_CREATE_PRIMARY_ASYNC",
496 [QXL_IO_DESTROY_PRIMARY_ASYNC
] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
497 [QXL_IO_DESTROY_SURFACE_ASYNC
] = "QXL_IO_DESTROY_SURFACE_ASYNC",
498 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC
]
499 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
500 [QXL_IO_FLUSH_SURFACES_ASYNC
] = "QXL_IO_FLUSH_SURFACES_ASYNC",
501 [QXL_IO_FLUSH_RELEASE
] = "QXL_IO_FLUSH_RELEASE",
504 return io_port_to_string
[io_port
];
507 /* called from spice server thread context only */
508 static int interface_get_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
510 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
511 SimpleSpiceUpdate
*update
;
512 QXLCommandRing
*ring
;
518 dprint(qxl
, 2, "%s: vga\n", __FUNCTION__
);
520 qemu_mutex_lock(&qxl
->ssd
.lock
);
521 if (qxl
->ssd
.update
!= NULL
) {
522 update
= qxl
->ssd
.update
;
523 qxl
->ssd
.update
= NULL
;
527 qemu_mutex_unlock(&qxl
->ssd
.lock
);
529 dprint(qxl
, 2, "%s %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
530 qxl_log_command(qxl
, "vga", ext
);
533 case QXL_MODE_COMPAT
:
534 case QXL_MODE_NATIVE
:
535 case QXL_MODE_UNDEFINED
:
536 dprint(qxl
, 4, "%s: %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
537 ring
= &qxl
->ram
->cmd_ring
;
538 if (SPICE_RING_IS_EMPTY(ring
)) {
541 dprint(qxl
, 2, "%s: %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
542 SPICE_RING_CONS_ITEM(ring
, cmd
);
544 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
545 ext
->flags
= qxl
->cmdflags
;
546 SPICE_RING_POP(ring
, notify
);
547 qxl_ring_set_dirty(qxl
);
549 qxl_send_events(qxl
, QXL_INTERRUPT_DISPLAY
);
551 qxl
->guest_primary
.commands
++;
552 qxl_track_command(qxl
, ext
);
553 qxl_log_command(qxl
, "cmd", ext
);
560 /* called from spice server thread context only */
561 static int interface_req_cmd_notification(QXLInstance
*sin
)
563 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
567 case QXL_MODE_COMPAT
:
568 case QXL_MODE_NATIVE
:
569 case QXL_MODE_UNDEFINED
:
570 SPICE_RING_CONS_WAIT(&qxl
->ram
->cmd_ring
, wait
);
571 qxl_ring_set_dirty(qxl
);
580 /* called from spice server thread context only */
581 static inline void qxl_push_free_res(PCIQXLDevice
*d
, int flush
)
583 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
587 #define QXL_FREE_BUNCH_SIZE 32
589 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
590 /* ring full -- can't push */
593 if (!flush
&& d
->oom_running
) {
594 /* collect everything from oom handler before pushing */
597 if (!flush
&& d
->num_free_res
< QXL_FREE_BUNCH_SIZE
) {
598 /* collect a bit more before pushing */
602 SPICE_RING_PUSH(ring
, notify
);
603 dprint(d
, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
604 d
->num_free_res
, notify
? "yes" : "no",
605 ring
->prod
- ring
->cons
, ring
->num_items
,
606 ring
->prod
, ring
->cons
);
608 qxl_send_events(d
, QXL_INTERRUPT_DISPLAY
);
610 SPICE_RING_PROD_ITEM(ring
, item
);
613 d
->last_release
= NULL
;
614 qxl_ring_set_dirty(d
);
617 /* called from spice server thread context only */
618 static void interface_release_resource(QXLInstance
*sin
,
619 struct QXLReleaseInfoExt ext
)
621 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
622 QXLReleaseRing
*ring
;
625 if (ext
.group_id
== MEMSLOT_GROUP_HOST
) {
626 /* host group -> vga mode update request */
627 qemu_spice_destroy_update(&qxl
->ssd
, (void*)ext
.info
->id
);
632 * ext->info points into guest-visible memory
633 * pci bar 0, $command.release_info
635 ring
= &qxl
->ram
->release_ring
;
636 SPICE_RING_PROD_ITEM(ring
, item
);
638 /* stick head into the ring */
641 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
643 qxl_ring_set_dirty(qxl
);
645 /* append item to the list */
646 qxl
->last_release
->next
= ext
.info
->id
;
647 qxl_ram_set_dirty(qxl
, &qxl
->last_release
->next
);
649 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
651 qxl
->last_release
= ext
.info
;
653 dprint(qxl
, 3, "%4d\r", qxl
->num_free_res
);
654 qxl_push_free_res(qxl
, 0);
657 /* called from spice server thread context only */
658 static int interface_get_cursor_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
660 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
666 case QXL_MODE_COMPAT
:
667 case QXL_MODE_NATIVE
:
668 case QXL_MODE_UNDEFINED
:
669 ring
= &qxl
->ram
->cursor_ring
;
670 if (SPICE_RING_IS_EMPTY(ring
)) {
673 SPICE_RING_CONS_ITEM(ring
, cmd
);
675 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
676 ext
->flags
= qxl
->cmdflags
;
677 SPICE_RING_POP(ring
, notify
);
678 qxl_ring_set_dirty(qxl
);
680 qxl_send_events(qxl
, QXL_INTERRUPT_CURSOR
);
682 qxl
->guest_primary
.commands
++;
683 qxl_track_command(qxl
, ext
);
684 qxl_log_command(qxl
, "csr", ext
);
686 qxl_render_cursor(qxl
, ext
);
694 /* called from spice server thread context only */
695 static int interface_req_cursor_notification(QXLInstance
*sin
)
697 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
701 case QXL_MODE_COMPAT
:
702 case QXL_MODE_NATIVE
:
703 case QXL_MODE_UNDEFINED
:
704 SPICE_RING_CONS_WAIT(&qxl
->ram
->cursor_ring
, wait
);
705 qxl_ring_set_dirty(qxl
);
714 /* called from spice server thread context */
715 static void interface_notify_update(QXLInstance
*sin
, uint32_t update_id
)
717 fprintf(stderr
, "%s: abort()\n", __FUNCTION__
);
721 /* called from spice server thread context only */
722 static int interface_flush_resources(QXLInstance
*sin
)
724 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
727 dprint(qxl
, 1, "free: guest flush (have %d)\n", qxl
->num_free_res
);
728 ret
= qxl
->num_free_res
;
730 qxl_push_free_res(qxl
, 1);
735 static void qxl_create_guest_primary_complete(PCIQXLDevice
*d
);
737 #if SPICE_INTERFACE_QXL_MINOR >= 1
739 /* called from spice server thread context only */
740 static void interface_async_complete(QXLInstance
*sin
, uint64_t cookie
)
742 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
743 uint32_t current_async
;
745 qemu_mutex_lock(&qxl
->async_lock
);
746 current_async
= qxl
->current_async
;
747 qxl
->current_async
= QXL_UNDEFINED_IO
;
748 qemu_mutex_unlock(&qxl
->async_lock
);
750 dprint(qxl
, 2, "async_complete: %d (%ld) done\n", current_async
, cookie
);
751 switch (current_async
) {
752 case QXL_IO_CREATE_PRIMARY_ASYNC
:
753 qxl_create_guest_primary_complete(qxl
);
755 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
756 qxl_spice_destroy_surfaces_complete(qxl
);
758 case QXL_IO_DESTROY_SURFACE_ASYNC
:
759 qxl_spice_destroy_surface_wait_complete(qxl
, (uint32_t)cookie
);
762 qxl_send_events(qxl
, QXL_INTERRUPT_IO_CMD
);
767 static const QXLInterface qxl_interface
= {
768 .base
.type
= SPICE_INTERFACE_QXL
,
769 .base
.description
= "qxl gpu",
770 .base
.major_version
= SPICE_INTERFACE_QXL_MAJOR
,
771 .base
.minor_version
= SPICE_INTERFACE_QXL_MINOR
,
773 .attache_worker
= interface_attach_worker
,
774 .set_compression_level
= interface_set_compression_level
,
775 .set_mm_time
= interface_set_mm_time
,
776 .get_init_info
= interface_get_init_info
,
778 /* the callbacks below are called from spice server thread context */
779 .get_command
= interface_get_command
,
780 .req_cmd_notification
= interface_req_cmd_notification
,
781 .release_resource
= interface_release_resource
,
782 .get_cursor_command
= interface_get_cursor_command
,
783 .req_cursor_notification
= interface_req_cursor_notification
,
784 .notify_update
= interface_notify_update
,
785 .flush_resources
= interface_flush_resources
,
786 #if SPICE_INTERFACE_QXL_MINOR >= 1
787 .async_complete
= interface_async_complete
,
791 static void qxl_enter_vga_mode(PCIQXLDevice
*d
)
793 if (d
->mode
== QXL_MODE_VGA
) {
796 dprint(d
, 1, "%s\n", __FUNCTION__
);
797 qemu_spice_create_host_primary(&d
->ssd
);
798 d
->mode
= QXL_MODE_VGA
;
799 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
802 static void qxl_exit_vga_mode(PCIQXLDevice
*d
)
804 if (d
->mode
!= QXL_MODE_VGA
) {
807 dprint(d
, 1, "%s\n", __FUNCTION__
);
808 qxl_destroy_primary(d
, QXL_SYNC
);
811 static void qxl_set_irq(PCIQXLDevice
*d
)
813 uint32_t pending
= le32_to_cpu(d
->ram
->int_pending
);
814 uint32_t mask
= le32_to_cpu(d
->ram
->int_mask
);
815 int level
= !!(pending
& mask
);
816 qemu_set_irq(d
->pci
.irq
[0], level
);
817 qxl_ring_set_dirty(d
);
820 static void qxl_check_state(PCIQXLDevice
*d
)
822 QXLRam
*ram
= d
->ram
;
824 assert(SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
825 assert(SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
828 static void qxl_reset_state(PCIQXLDevice
*d
)
830 QXLRam
*ram
= d
->ram
;
831 QXLRom
*rom
= d
->rom
;
833 assert(!d
->ssd
.running
|| SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
834 assert(!d
->ssd
.running
|| SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
835 d
->shadow_rom
.update_id
= cpu_to_le32(0);
836 *rom
= d
->shadow_rom
;
837 qxl_rom_set_dirty(d
);
840 d
->last_release
= NULL
;
841 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
844 static void qxl_soft_reset(PCIQXLDevice
*d
)
846 dprint(d
, 1, "%s:\n", __FUNCTION__
);
850 qxl_enter_vga_mode(d
);
852 d
->mode
= QXL_MODE_UNDEFINED
;
856 static void qxl_hard_reset(PCIQXLDevice
*d
, int loadvm
)
858 dprint(d
, 1, "%s: start%s\n", __FUNCTION__
,
859 loadvm
? " (loadvm)" : "");
861 qxl_spice_reset_cursor(d
);
862 qxl_spice_reset_image_cache(d
);
863 qxl_reset_surfaces(d
);
864 qxl_reset_memslots(d
);
866 /* pre loadvm reset must not touch QXLRam. This lives in
867 * device memory, is migrated together with RAM and thus
868 * already loaded at this point */
872 qemu_spice_create_host_memslot(&d
->ssd
);
875 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
878 static void qxl_reset_handler(DeviceState
*dev
)
880 PCIQXLDevice
*d
= DO_UPCAST(PCIQXLDevice
, pci
.qdev
, dev
);
881 qxl_hard_reset(d
, 0);
884 static void qxl_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
886 VGACommonState
*vga
= opaque
;
887 PCIQXLDevice
*qxl
= container_of(vga
, PCIQXLDevice
, vga
);
889 if (qxl
->mode
!= QXL_MODE_VGA
) {
890 dprint(qxl
, 1, "%s\n", __FUNCTION__
);
891 qxl_destroy_primary(qxl
, QXL_SYNC
);
894 vga_ioport_write(opaque
, addr
, val
);
897 static void qxl_add_memslot(PCIQXLDevice
*d
, uint32_t slot_id
, uint64_t delta
,
900 static const int regions
[] = {
902 QXL_VRAM_RANGE_INDEX
,
904 uint64_t guest_start
;
910 QXLDevMemSlot memslot
;
913 guest_start
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_start
);
914 guest_end
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_end
);
916 dprint(d
, 1, "%s: slot %d: guest phys 0x%" PRIx64
" - 0x%" PRIx64
"\n",
917 __FUNCTION__
, slot_id
,
918 guest_start
, guest_end
);
920 PANIC_ON(slot_id
>= NUM_MEMSLOTS
);
921 PANIC_ON(guest_start
> guest_end
);
923 for (i
= 0; i
< ARRAY_SIZE(regions
); i
++) {
924 pci_region
= regions
[i
];
925 pci_start
= d
->pci
.io_regions
[pci_region
].addr
;
926 pci_end
= pci_start
+ d
->pci
.io_regions
[pci_region
].size
;
928 if (pci_start
== -1) {
931 /* start address in range ? */
932 if (guest_start
< pci_start
|| guest_start
> pci_end
) {
935 /* end address in range ? */
936 if (guest_end
> pci_end
) {
942 PANIC_ON(i
== ARRAY_SIZE(regions
)); /* finished loop without match */
944 switch (pci_region
) {
945 case QXL_RAM_RANGE_INDEX
:
946 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vga
.vram
);
948 case QXL_VRAM_RANGE_INDEX
:
949 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vram_bar
);
952 /* should not happen */
956 memslot
.slot_id
= slot_id
;
957 memslot
.slot_group_id
= MEMSLOT_GROUP_GUEST
; /* guest group */
958 memslot
.virt_start
= virt_start
+ (guest_start
- pci_start
);
959 memslot
.virt_end
= virt_start
+ (guest_end
- pci_start
);
960 memslot
.addr_delta
= memslot
.virt_start
- delta
;
961 memslot
.generation
= d
->rom
->slot_generation
= 0;
962 qxl_rom_set_dirty(d
);
964 dprint(d
, 1, "%s: slot %d: host virt 0x%" PRIx64
" - 0x%" PRIx64
"\n",
965 __FUNCTION__
, memslot
.slot_id
,
966 memslot
.virt_start
, memslot
.virt_end
);
968 qemu_spice_add_memslot(&d
->ssd
, &memslot
, async
);
969 d
->guest_slots
[slot_id
].ptr
= (void*)memslot
.virt_start
;
970 d
->guest_slots
[slot_id
].size
= memslot
.virt_end
- memslot
.virt_start
;
971 d
->guest_slots
[slot_id
].delta
= delta
;
972 d
->guest_slots
[slot_id
].active
= 1;
975 static void qxl_del_memslot(PCIQXLDevice
*d
, uint32_t slot_id
)
977 dprint(d
, 1, "%s: slot %d\n", __FUNCTION__
, slot_id
);
978 qemu_spice_del_memslot(&d
->ssd
, MEMSLOT_GROUP_HOST
, slot_id
);
979 d
->guest_slots
[slot_id
].active
= 0;
982 static void qxl_reset_memslots(PCIQXLDevice
*d
)
984 dprint(d
, 1, "%s:\n", __FUNCTION__
);
985 qxl_spice_reset_memslots(d
);
986 memset(&d
->guest_slots
, 0, sizeof(d
->guest_slots
));
989 static void qxl_reset_surfaces(PCIQXLDevice
*d
)
991 dprint(d
, 1, "%s:\n", __FUNCTION__
);
992 d
->mode
= QXL_MODE_UNDEFINED
;
993 qxl_spice_destroy_surfaces(d
, QXL_SYNC
);
996 /* called from spice server thread context only */
997 void *qxl_phys2virt(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
, int group_id
)
999 uint64_t phys
= le64_to_cpu(pqxl
);
1000 uint32_t slot
= (phys
>> (64 - 8)) & 0xff;
1001 uint64_t offset
= phys
& 0xffffffffffff;
1004 case MEMSLOT_GROUP_HOST
:
1005 return (void*)offset
;
1006 case MEMSLOT_GROUP_GUEST
:
1007 PANIC_ON(slot
> NUM_MEMSLOTS
);
1008 PANIC_ON(!qxl
->guest_slots
[slot
].active
);
1009 PANIC_ON(offset
< qxl
->guest_slots
[slot
].delta
);
1010 offset
-= qxl
->guest_slots
[slot
].delta
;
1011 PANIC_ON(offset
> qxl
->guest_slots
[slot
].size
)
1012 return qxl
->guest_slots
[slot
].ptr
+ offset
;
1018 static void qxl_create_guest_primary_complete(PCIQXLDevice
*qxl
)
1020 /* for local rendering */
1021 qxl_render_resize(qxl
);
1024 static void qxl_create_guest_primary(PCIQXLDevice
*qxl
, int loadvm
,
1027 QXLDevSurfaceCreate surface
;
1028 QXLSurfaceCreate
*sc
= &qxl
->guest_primary
.surface
;
1030 assert(qxl
->mode
!= QXL_MODE_NATIVE
);
1031 qxl_exit_vga_mode(qxl
);
1033 dprint(qxl
, 1, "%s: %dx%d\n", __FUNCTION__
,
1034 le32_to_cpu(sc
->width
), le32_to_cpu(sc
->height
));
1036 surface
.format
= le32_to_cpu(sc
->format
);
1037 surface
.height
= le32_to_cpu(sc
->height
);
1038 surface
.mem
= le64_to_cpu(sc
->mem
);
1039 surface
.position
= le32_to_cpu(sc
->position
);
1040 surface
.stride
= le32_to_cpu(sc
->stride
);
1041 surface
.width
= le32_to_cpu(sc
->width
);
1042 surface
.type
= le32_to_cpu(sc
->type
);
1043 surface
.flags
= le32_to_cpu(sc
->flags
);
1045 surface
.mouse_mode
= true;
1046 surface
.group_id
= MEMSLOT_GROUP_GUEST
;
1048 surface
.flags
|= QXL_SURF_FLAG_KEEP_DATA
;
1051 qxl
->mode
= QXL_MODE_NATIVE
;
1053 qemu_spice_create_primary_surface(&qxl
->ssd
, 0, &surface
, async
);
1055 if (async
== QXL_SYNC
) {
1056 qxl_create_guest_primary_complete(qxl
);
1060 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1061 * done (in QXL_SYNC case), 0 otherwise. */
1062 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
)
1064 if (d
->mode
== QXL_MODE_UNDEFINED
) {
1068 dprint(d
, 1, "%s\n", __FUNCTION__
);
1070 d
->mode
= QXL_MODE_UNDEFINED
;
1071 qemu_spice_destroy_primary_surface(&d
->ssd
, 0, async
);
1075 static void qxl_set_mode(PCIQXLDevice
*d
, int modenr
, int loadvm
)
1077 pcibus_t start
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1078 pcibus_t end
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].size
+ start
;
1079 QXLMode
*mode
= d
->modes
->modes
+ modenr
;
1080 uint64_t devmem
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1085 QXLSurfaceCreate surface
= {
1086 .width
= mode
->x_res
,
1087 .height
= mode
->y_res
,
1088 .stride
= -mode
->x_res
* 4,
1089 .format
= SPICE_SURFACE_FMT_32_xRGB
,
1090 .flags
= loadvm
? QXL_SURF_FLAG_KEEP_DATA
: 0,
1092 .mem
= devmem
+ d
->shadow_rom
.draw_area_offset
,
1095 dprint(d
, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%lx ]\n", __FUNCTION__
,
1096 modenr
, mode
->x_res
, mode
->y_res
, mode
->bits
, devmem
);
1098 qxl_hard_reset(d
, 0);
1101 d
->guest_slots
[0].slot
= slot
;
1102 qxl_add_memslot(d
, 0, devmem
, QXL_SYNC
);
1104 d
->guest_primary
.surface
= surface
;
1105 qxl_create_guest_primary(d
, 0, QXL_SYNC
);
1107 d
->mode
= QXL_MODE_COMPAT
;
1108 d
->cmdflags
= QXL_COMMAND_FLAG_COMPAT
;
1109 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1110 if (mode
->bits
== 16) {
1111 d
->cmdflags
|= QXL_COMMAND_FLAG_COMPAT_16BPP
;
1114 d
->shadow_rom
.mode
= cpu_to_le32(modenr
);
1115 d
->rom
->mode
= cpu_to_le32(modenr
);
1116 qxl_rom_set_dirty(d
);
1119 static void ioport_write(void *opaque
, target_phys_addr_t addr
,
1120 uint64_t val
, unsigned size
)
1122 PCIQXLDevice
*d
= opaque
;
1123 uint32_t io_port
= addr
;
1124 qxl_async_io async
= QXL_SYNC
;
1125 #if SPICE_INTERFACE_QXL_MINOR >= 1
1126 uint32_t orig_io_port
= io_port
;
1131 case QXL_IO_SET_MODE
:
1132 case QXL_IO_MEMSLOT_ADD
:
1133 case QXL_IO_MEMSLOT_DEL
:
1134 case QXL_IO_CREATE_PRIMARY
:
1135 case QXL_IO_UPDATE_IRQ
:
1137 #if SPICE_INTERFACE_QXL_MINOR >= 1
1138 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1139 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1143 if (d
->mode
!= QXL_MODE_VGA
) {
1146 dprint(d
, 1, "%s: unexpected port 0x%x (%s) in vga mode\n",
1147 __func__
, io_port
, io_port_to_string(io_port
));
1148 #if SPICE_INTERFACE_QXL_MINOR >= 1
1149 /* be nice to buggy guest drivers */
1150 if (io_port
>= QXL_IO_UPDATE_AREA_ASYNC
&&
1151 io_port
<= QXL_IO_DESTROY_ALL_SURFACES_ASYNC
) {
1152 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1158 #if SPICE_INTERFACE_QXL_MINOR >= 1
1159 /* we change the io_port to avoid ifdeffery in the main switch */
1160 orig_io_port
= io_port
;
1162 case QXL_IO_UPDATE_AREA_ASYNC
:
1163 io_port
= QXL_IO_UPDATE_AREA
;
1165 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1166 io_port
= QXL_IO_MEMSLOT_ADD
;
1168 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1169 io_port
= QXL_IO_CREATE_PRIMARY
;
1171 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
1172 io_port
= QXL_IO_DESTROY_PRIMARY
;
1174 case QXL_IO_DESTROY_SURFACE_ASYNC
:
1175 io_port
= QXL_IO_DESTROY_SURFACE_WAIT
;
1177 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
1178 io_port
= QXL_IO_DESTROY_ALL_SURFACES
;
1180 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1183 qemu_mutex_lock(&d
->async_lock
);
1184 if (d
->current_async
!= QXL_UNDEFINED_IO
) {
1185 qxl_guest_bug(d
, "%d async started before last (%d) complete",
1186 io_port
, d
->current_async
);
1187 qemu_mutex_unlock(&d
->async_lock
);
1190 d
->current_async
= orig_io_port
;
1191 qemu_mutex_unlock(&d
->async_lock
);
1192 dprint(d
, 2, "start async %d (%d)\n", io_port
, val
);
1200 case QXL_IO_UPDATE_AREA
:
1202 QXLRect update
= d
->ram
->update_area
;
1203 qxl_spice_update_area(d
, d
->ram
->update_surface
,
1204 &update
, NULL
, 0, 0, async
);
1207 case QXL_IO_NOTIFY_CMD
:
1208 qemu_spice_wakeup(&d
->ssd
);
1210 case QXL_IO_NOTIFY_CURSOR
:
1211 qemu_spice_wakeup(&d
->ssd
);
1213 case QXL_IO_UPDATE_IRQ
:
1216 case QXL_IO_NOTIFY_OOM
:
1217 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1221 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1228 case QXL_IO_SET_MODE
:
1229 dprint(d
, 1, "QXL_SET_MODE %d\n", (int)val
);
1230 qxl_set_mode(d
, val
, 0);
1233 if (d
->guestdebug
) {
1234 fprintf(stderr
, "qxl/guest-%d: %ld: %s", d
->id
,
1235 qemu_get_clock_ns(vm_clock
), d
->ram
->log_buf
);
1239 dprint(d
, 1, "QXL_IO_RESET\n");
1240 qxl_hard_reset(d
, 0);
1242 case QXL_IO_MEMSLOT_ADD
:
1243 if (val
>= NUM_MEMSLOTS
) {
1244 qxl_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: val out of range");
1247 if (d
->guest_slots
[val
].active
) {
1248 qxl_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: memory slot already active");
1251 d
->guest_slots
[val
].slot
= d
->ram
->mem_slot
;
1252 qxl_add_memslot(d
, val
, 0, async
);
1254 case QXL_IO_MEMSLOT_DEL
:
1255 if (val
>= NUM_MEMSLOTS
) {
1256 qxl_guest_bug(d
, "QXL_IO_MEMSLOT_DEL: val out of range");
1259 qxl_del_memslot(d
, val
);
1261 case QXL_IO_CREATE_PRIMARY
:
1263 qxl_guest_bug(d
, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1267 dprint(d
, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async
);
1268 d
->guest_primary
.surface
= d
->ram
->create_surface
;
1269 qxl_create_guest_primary(d
, 0, async
);
1271 case QXL_IO_DESTROY_PRIMARY
:
1273 qxl_guest_bug(d
, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1277 dprint(d
, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async
,
1278 qxl_mode_to_string(d
->mode
));
1279 if (!qxl_destroy_primary(d
, async
)) {
1280 dprint(d
, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n",
1281 qxl_mode_to_string(d
->mode
));
1285 case QXL_IO_DESTROY_SURFACE_WAIT
:
1286 if (val
>= NUM_SURFACES
) {
1287 qxl_guest_bug(d
, "QXL_IO_DESTROY_SURFACE (async=%d):"
1288 "%d >= NUM_SURFACES", async
, val
);
1291 qxl_spice_destroy_surface_wait(d
, val
, async
);
1293 #if SPICE_INTERFACE_QXL_MINOR >= 1
1294 case QXL_IO_FLUSH_RELEASE
: {
1295 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
1296 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
1298 "ERROR: no flush, full release ring [p%d,%dc]\n",
1299 ring
->prod
, ring
->cons
);
1301 qxl_push_free_res(d
, 1 /* flush */);
1302 dprint(d
, 1, "QXL_IO_FLUSH_RELEASE exit (%s, s#=%d, res#=%d,%p)\n",
1303 qxl_mode_to_string(d
->mode
), d
->guest_surfaces
.count
,
1304 d
->num_free_res
, d
->last_release
);
1307 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1308 dprint(d
, 1, "QXL_IO_FLUSH_SURFACES_ASYNC (%d) (%s, s#=%d, res#=%d)\n",
1309 val
, qxl_mode_to_string(d
->mode
), d
->guest_surfaces
.count
,
1311 qxl_spice_flush_surfaces_async(d
);
1314 case QXL_IO_DESTROY_ALL_SURFACES
:
1315 d
->mode
= QXL_MODE_UNDEFINED
;
1316 qxl_spice_destroy_surfaces(d
, async
);
1319 fprintf(stderr
, "%s: ioport=0x%x, abort()\n", __FUNCTION__
, io_port
);
1324 #if SPICE_INTERFACE_QXL_MINOR >= 1
1326 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1327 qemu_mutex_lock(&d
->async_lock
);
1328 d
->current_async
= QXL_UNDEFINED_IO
;
1329 qemu_mutex_unlock(&d
->async_lock
);
1336 static uint64_t ioport_read(void *opaque
, target_phys_addr_t addr
,
1339 PCIQXLDevice
*d
= opaque
;
1341 dprint(d
, 1, "%s: unexpected\n", __FUNCTION__
);
1345 static const MemoryRegionOps qxl_io_ops
= {
1346 .read
= ioport_read
,
1347 .write
= ioport_write
,
1349 .min_access_size
= 1,
1350 .max_access_size
= 1,
1354 static void pipe_read(void *opaque
)
1356 PCIQXLDevice
*d
= opaque
;
1361 len
= read(d
->pipe
[0], &dummy
, sizeof(dummy
));
1362 } while (len
== sizeof(dummy
));
1366 /* called from spice server thread context only */
1367 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
)
1369 uint32_t old_pending
;
1370 uint32_t le_events
= cpu_to_le32(events
);
1372 assert(d
->ssd
.running
);
1373 old_pending
= __sync_fetch_and_or(&d
->ram
->int_pending
, le_events
);
1374 if ((old_pending
& le_events
) == le_events
) {
1377 if (pthread_self() == d
->main
) {
1380 if (write(d
->pipe
[1], d
, 1) != 1) {
1381 dprint(d
, 1, "%s: write to pipe failed\n", __FUNCTION__
);
1386 static void init_pipe_signaling(PCIQXLDevice
*d
)
1388 if (pipe(d
->pipe
) < 0) {
1389 dprint(d
, 1, "%s: pipe creation failed\n", __FUNCTION__
);
1392 #ifdef CONFIG_IOTHREAD
1393 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
);
1395 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
/* | O_ASYNC */);
1397 fcntl(d
->pipe
[1], F_SETFL
, O_NONBLOCK
);
1398 fcntl(d
->pipe
[0], F_SETOWN
, getpid());
1400 d
->main
= pthread_self();
1401 qemu_set_fd_handler(d
->pipe
[0], pipe_read
, NULL
, d
);
1404 /* graphics console */
1406 static void qxl_hw_update(void *opaque
)
1408 PCIQXLDevice
*qxl
= opaque
;
1409 VGACommonState
*vga
= &qxl
->vga
;
1411 switch (qxl
->mode
) {
1415 case QXL_MODE_COMPAT
:
1416 case QXL_MODE_NATIVE
:
1417 qxl_render_update(qxl
);
1424 static void qxl_hw_invalidate(void *opaque
)
1426 PCIQXLDevice
*qxl
= opaque
;
1427 VGACommonState
*vga
= &qxl
->vga
;
1429 vga
->invalidate(vga
);
1432 static void qxl_hw_screen_dump(void *opaque
, const char *filename
)
1434 PCIQXLDevice
*qxl
= opaque
;
1435 VGACommonState
*vga
= &qxl
->vga
;
1437 switch (qxl
->mode
) {
1438 case QXL_MODE_COMPAT
:
1439 case QXL_MODE_NATIVE
:
1440 qxl_render_update(qxl
);
1441 ppm_save(filename
, qxl
->ssd
.ds
->surface
);
1444 vga
->screen_dump(vga
, filename
);
1451 static void qxl_hw_text_update(void *opaque
, console_ch_t
*chardata
)
1453 PCIQXLDevice
*qxl
= opaque
;
1454 VGACommonState
*vga
= &qxl
->vga
;
1456 if (qxl
->mode
== QXL_MODE_VGA
) {
1457 vga
->text_update(vga
, chardata
);
1462 static void qxl_vm_change_state_handler(void *opaque
, int running
, int reason
)
1464 PCIQXLDevice
*qxl
= opaque
;
1465 qemu_spice_vm_change_state_handler(&qxl
->ssd
, running
, reason
);
1467 if (!running
&& qxl
->mode
== QXL_MODE_NATIVE
) {
1468 /* dirty all vram (which holds surfaces) and devram (primary surface)
1469 * to make sure they are saved */
1470 /* FIXME #1: should go out during "live" stage */
1471 /* FIXME #2: we only need to save the areas which are actually used */
1472 qxl_set_dirty(&qxl
->vram_bar
, 0, qxl
->vram_size
);
1473 qxl_set_dirty(&qxl
->vga
.vram
, qxl
->shadow_rom
.draw_area_offset
,
1474 qxl
->shadow_rom
.surface0_area_size
);
1478 /* display change listener */
1480 static void display_update(struct DisplayState
*ds
, int x
, int y
, int w
, int h
)
1482 if (qxl0
->mode
== QXL_MODE_VGA
) {
1483 qemu_spice_display_update(&qxl0
->ssd
, x
, y
, w
, h
);
1487 static void display_resize(struct DisplayState
*ds
)
1489 if (qxl0
->mode
== QXL_MODE_VGA
) {
1490 qemu_spice_display_resize(&qxl0
->ssd
);
1494 static void display_refresh(struct DisplayState
*ds
)
1496 if (qxl0
->mode
== QXL_MODE_VGA
) {
1497 qemu_spice_display_refresh(&qxl0
->ssd
);
1501 static DisplayChangeListener display_listener
= {
1502 .dpy_update
= display_update
,
1503 .dpy_resize
= display_resize
,
1504 .dpy_refresh
= display_refresh
,
1507 static int qxl_init_common(PCIQXLDevice
*qxl
)
1509 uint8_t* config
= qxl
->pci
.config
;
1510 uint32_t pci_device_rev
;
1513 qxl
->mode
= QXL_MODE_UNDEFINED
;
1514 qxl
->generation
= 1;
1515 qxl
->num_memslots
= NUM_MEMSLOTS
;
1516 qxl
->num_surfaces
= NUM_SURFACES
;
1517 qemu_mutex_init(&qxl
->track_lock
);
1518 qemu_mutex_init(&qxl
->async_lock
);
1519 qxl
->current_async
= QXL_UNDEFINED_IO
;
1521 switch (qxl
->revision
) {
1522 case 1: /* spice 0.4 -- qxl-1 */
1523 pci_device_rev
= QXL_REVISION_STABLE_V04
;
1525 case 2: /* spice 0.6 -- qxl-2 */
1526 pci_device_rev
= QXL_REVISION_STABLE_V06
;
1528 #if SPICE_INTERFACE_QXL_MINOR >= 1
1532 pci_device_rev
= QXL_DEFAULT_REVISION
;
1536 pci_set_byte(&config
[PCI_REVISION_ID
], pci_device_rev
);
1537 pci_set_byte(&config
[PCI_INTERRUPT_PIN
], 1);
1539 qxl
->rom_size
= qxl_rom_size();
1540 memory_region_init_ram(&qxl
->rom_bar
, &qxl
->pci
.qdev
, "qxl.vrom",
1545 if (qxl
->vram_size
< 16 * 1024 * 1024) {
1546 qxl
->vram_size
= 16 * 1024 * 1024;
1548 if (qxl
->revision
== 1) {
1549 qxl
->vram_size
= 4096;
1551 qxl
->vram_size
= msb_mask(qxl
->vram_size
* 2 - 1);
1552 memory_region_init_ram(&qxl
->vram_bar
, &qxl
->pci
.qdev
, "qxl.vram",
1555 io_size
= msb_mask(QXL_IO_RANGE_SIZE
* 2 - 1);
1556 if (qxl
->revision
== 1) {
1560 memory_region_init_io(&qxl
->io_bar
, &qxl_io_ops
, qxl
,
1561 "qxl-ioports", io_size
);
1563 vga_dirty_log_start(&qxl
->vga
);
1567 pci_register_bar_region(&qxl
->pci
, QXL_IO_RANGE_INDEX
,
1568 PCI_BASE_ADDRESS_SPACE_IO
, &qxl
->io_bar
);
1570 pci_register_bar_region(&qxl
->pci
, QXL_ROM_RANGE_INDEX
,
1571 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->rom_bar
);
1573 pci_register_bar_region(&qxl
->pci
, QXL_RAM_RANGE_INDEX
,
1574 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vga
.vram
);
1576 pci_register_bar_region(&qxl
->pci
, QXL_VRAM_RANGE_INDEX
,
1577 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vram_bar
);
1579 qxl
->ssd
.qxl
.base
.sif
= &qxl_interface
.base
;
1580 qxl
->ssd
.qxl
.id
= qxl
->id
;
1581 qemu_spice_add_interface(&qxl
->ssd
.qxl
.base
);
1582 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler
, qxl
);
1584 init_pipe_signaling(qxl
);
1585 qxl_reset_state(qxl
);
1590 static int qxl_init_primary(PCIDevice
*dev
)
1592 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1593 VGACommonState
*vga
= &qxl
->vga
;
1594 ram_addr_t ram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1598 if (ram_size
< 32 * 1024 * 1024) {
1599 ram_size
= 32 * 1024 * 1024;
1601 vga_common_init(vga
, ram_size
);
1603 register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write
, vga
);
1604 register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write
, vga
);
1605 register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write
, vga
);
1606 register_ioport_write(0x3ba, 1, 1, qxl_vga_ioport_write
, vga
);
1607 register_ioport_write(0x3da, 1, 1, qxl_vga_ioport_write
, vga
);
1609 vga
->ds
= graphic_console_init(qxl_hw_update
, qxl_hw_invalidate
,
1610 qxl_hw_screen_dump
, qxl_hw_text_update
, qxl
);
1611 qemu_spice_display_init_common(&qxl
->ssd
, vga
->ds
);
1614 register_displaychangelistener(vga
->ds
, &display_listener
);
1616 return qxl_init_common(qxl
);
1619 static int qxl_init_secondary(PCIDevice
*dev
)
1621 static int device_id
= 1;
1622 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1623 ram_addr_t ram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1625 qxl
->id
= device_id
++;
1627 if (ram_size
< 16 * 1024 * 1024) {
1628 ram_size
= 16 * 1024 * 1024;
1630 qxl
->vga
.vram_size
= ram_size
;
1631 memory_region_init_ram(&qxl
->vga
.vram
, &qxl
->pci
.qdev
, "qxl.vgavram",
1632 qxl
->vga
.vram_size
);
1633 qxl
->vga
.vram_ptr
= memory_region_get_ram_ptr(&qxl
->vga
.vram
);
1635 return qxl_init_common(qxl
);
1638 static void qxl_pre_save(void *opaque
)
1640 PCIQXLDevice
* d
= opaque
;
1641 uint8_t *ram_start
= d
->vga
.vram_ptr
;
1643 dprint(d
, 1, "%s:\n", __FUNCTION__
);
1644 if (d
->last_release
== NULL
) {
1645 d
->last_release_offset
= 0;
1647 d
->last_release_offset
= (uint8_t *)d
->last_release
- ram_start
;
1649 assert(d
->last_release_offset
< d
->vga
.vram_size
);
1652 static int qxl_pre_load(void *opaque
)
1654 PCIQXLDevice
* d
= opaque
;
1656 dprint(d
, 1, "%s: start\n", __FUNCTION__
);
1657 qxl_hard_reset(d
, 1);
1658 qxl_exit_vga_mode(d
);
1659 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
1663 static int qxl_post_load(void *opaque
, int version
)
1665 PCIQXLDevice
* d
= opaque
;
1666 uint8_t *ram_start
= d
->vga
.vram_ptr
;
1667 QXLCommandExt
*cmds
;
1668 int in
, out
, i
, newmode
;
1670 dprint(d
, 1, "%s: start\n", __FUNCTION__
);
1672 assert(d
->last_release_offset
< d
->vga
.vram_size
);
1673 if (d
->last_release_offset
== 0) {
1674 d
->last_release
= NULL
;
1676 d
->last_release
= (QXLReleaseInfo
*)(ram_start
+ d
->last_release_offset
);
1679 d
->modes
= (QXLModes
*)((uint8_t*)d
->rom
+ d
->rom
->modes_offset
);
1681 dprint(d
, 1, "%s: restore mode (%s)\n", __FUNCTION__
,
1682 qxl_mode_to_string(d
->mode
));
1684 d
->mode
= QXL_MODE_UNDEFINED
;
1686 case QXL_MODE_UNDEFINED
:
1689 qxl_enter_vga_mode(d
);
1691 case QXL_MODE_NATIVE
:
1692 for (i
= 0; i
< NUM_MEMSLOTS
; i
++) {
1693 if (!d
->guest_slots
[i
].active
) {
1696 qxl_add_memslot(d
, i
, 0, QXL_SYNC
);
1698 qxl_create_guest_primary(d
, 1, QXL_SYNC
);
1700 /* replay surface-create and cursor-set commands */
1701 cmds
= qemu_mallocz(sizeof(QXLCommandExt
) * (NUM_SURFACES
+ 1));
1702 for (in
= 0, out
= 0; in
< NUM_SURFACES
; in
++) {
1703 if (d
->guest_surfaces
.cmds
[in
] == 0) {
1706 cmds
[out
].cmd
.data
= d
->guest_surfaces
.cmds
[in
];
1707 cmds
[out
].cmd
.type
= QXL_CMD_SURFACE
;
1708 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
1711 cmds
[out
].cmd
.data
= d
->guest_cursor
;
1712 cmds
[out
].cmd
.type
= QXL_CMD_CURSOR
;
1713 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
1715 qxl_spice_loadvm_commands(d
, cmds
, out
);
1719 case QXL_MODE_COMPAT
:
1720 qxl_set_mode(d
, d
->shadow_rom
.mode
, 1);
1723 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
1728 #define QXL_SAVE_VERSION 21
1730 static VMStateDescription qxl_memslot
= {
1731 .name
= "qxl-memslot",
1732 .version_id
= QXL_SAVE_VERSION
,
1733 .minimum_version_id
= QXL_SAVE_VERSION
,
1734 .fields
= (VMStateField
[]) {
1735 VMSTATE_UINT64(slot
.mem_start
, struct guest_slots
),
1736 VMSTATE_UINT64(slot
.mem_end
, struct guest_slots
),
1737 VMSTATE_UINT32(active
, struct guest_slots
),
1738 VMSTATE_END_OF_LIST()
1742 static VMStateDescription qxl_surface
= {
1743 .name
= "qxl-surface",
1744 .version_id
= QXL_SAVE_VERSION
,
1745 .minimum_version_id
= QXL_SAVE_VERSION
,
1746 .fields
= (VMStateField
[]) {
1747 VMSTATE_UINT32(width
, QXLSurfaceCreate
),
1748 VMSTATE_UINT32(height
, QXLSurfaceCreate
),
1749 VMSTATE_INT32(stride
, QXLSurfaceCreate
),
1750 VMSTATE_UINT32(format
, QXLSurfaceCreate
),
1751 VMSTATE_UINT32(position
, QXLSurfaceCreate
),
1752 VMSTATE_UINT32(mouse_mode
, QXLSurfaceCreate
),
1753 VMSTATE_UINT32(flags
, QXLSurfaceCreate
),
1754 VMSTATE_UINT32(type
, QXLSurfaceCreate
),
1755 VMSTATE_UINT64(mem
, QXLSurfaceCreate
),
1756 VMSTATE_END_OF_LIST()
1760 static VMStateDescription qxl_vmstate
= {
1762 .version_id
= QXL_SAVE_VERSION
,
1763 .minimum_version_id
= QXL_SAVE_VERSION
,
1764 .pre_save
= qxl_pre_save
,
1765 .pre_load
= qxl_pre_load
,
1766 .post_load
= qxl_post_load
,
1767 .fields
= (VMStateField
[]) {
1768 VMSTATE_PCI_DEVICE(pci
, PCIQXLDevice
),
1769 VMSTATE_STRUCT(vga
, PCIQXLDevice
, 0, vmstate_vga_common
, VGACommonState
),
1770 VMSTATE_UINT32(shadow_rom
.mode
, PCIQXLDevice
),
1771 VMSTATE_UINT32(num_free_res
, PCIQXLDevice
),
1772 VMSTATE_UINT32(last_release_offset
, PCIQXLDevice
),
1773 VMSTATE_UINT32(mode
, PCIQXLDevice
),
1774 VMSTATE_UINT32(ssd
.unique
, PCIQXLDevice
),
1775 VMSTATE_INT32_EQUAL(num_memslots
, PCIQXLDevice
),
1776 VMSTATE_STRUCT_ARRAY(guest_slots
, PCIQXLDevice
, NUM_MEMSLOTS
, 0,
1777 qxl_memslot
, struct guest_slots
),
1778 VMSTATE_STRUCT(guest_primary
.surface
, PCIQXLDevice
, 0,
1779 qxl_surface
, QXLSurfaceCreate
),
1780 VMSTATE_INT32_EQUAL(num_surfaces
, PCIQXLDevice
),
1781 VMSTATE_ARRAY(guest_surfaces
.cmds
, PCIQXLDevice
, NUM_SURFACES
, 0,
1782 vmstate_info_uint64
, uint64_t),
1783 VMSTATE_UINT64(guest_cursor
, PCIQXLDevice
),
1784 VMSTATE_END_OF_LIST()
1788 static PCIDeviceInfo qxl_info_primary
= {
1789 .qdev
.name
= "qxl-vga",
1790 .qdev
.desc
= "Spice QXL GPU (primary, vga compatible)",
1791 .qdev
.size
= sizeof(PCIQXLDevice
),
1792 .qdev
.reset
= qxl_reset_handler
,
1793 .qdev
.vmsd
= &qxl_vmstate
,
1795 .init
= qxl_init_primary
,
1796 .romfile
= "vgabios-qxl.bin",
1797 .vendor_id
= REDHAT_PCI_VENDOR_ID
,
1798 .device_id
= QXL_DEVICE_ID_STABLE
,
1799 .class_id
= PCI_CLASS_DISPLAY_VGA
,
1800 .qdev
.props
= (Property
[]) {
1801 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
,
1803 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram_size
,
1805 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
,
1806 QXL_DEFAULT_REVISION
),
1807 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
1808 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
1809 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
1810 DEFINE_PROP_END_OF_LIST(),
1814 static PCIDeviceInfo qxl_info_secondary
= {
1816 .qdev
.desc
= "Spice QXL GPU (secondary)",
1817 .qdev
.size
= sizeof(PCIQXLDevice
),
1818 .qdev
.reset
= qxl_reset_handler
,
1819 .qdev
.vmsd
= &qxl_vmstate
,
1820 .init
= qxl_init_secondary
,
1821 .vendor_id
= REDHAT_PCI_VENDOR_ID
,
1822 .device_id
= QXL_DEVICE_ID_STABLE
,
1823 .class_id
= PCI_CLASS_DISPLAY_OTHER
,
1824 .qdev
.props
= (Property
[]) {
1825 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
,
1827 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram_size
,
1829 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
,
1830 QXL_DEFAULT_REVISION
),
1831 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
1832 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
1833 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
1834 DEFINE_PROP_END_OF_LIST(),
1838 static void qxl_register(void)
1840 pci_qdev_register(&qxl_info_primary
);
1841 pci_qdev_register(&qxl_info_secondary
);
1844 device_init(qxl_register
);