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1 /*
2 * QEMU paravirtual RDMA - Generic RDMA backend
3 *
4 * Copyright (C) 2018 Oracle
5 * Copyright (C) 2018 Red Hat Inc
6 *
7 * Authors:
8 * Yuval Shaia <yuval.shaia@oracle.com>
9 * Marcel Apfelbaum <marcel@redhat.com>
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2 or later.
12 * See the COPYING file in the top-level directory.
13 *
14 */
15
16 #include "qemu/osdep.h"
17 #include "sysemu/sysemu.h"
18 #include "qapi/error.h"
19 #include "qapi/qmp/qlist.h"
20 #include "qapi/qmp/qnum.h"
21 #include "qapi/qapi-events-rdma.h"
22
23 #include <infiniband/verbs.h>
24 #include <infiniband/umad_types.h>
25 #include <infiniband/umad.h>
26 #include <rdma/rdma_user_cm.h>
27
28 #include "contrib/rdmacm-mux/rdmacm-mux.h"
29 #include "trace.h"
30 #include "rdma_utils.h"
31 #include "rdma_rm.h"
32 #include "rdma_backend.h"
33
34 #define THR_NAME_LEN 16
35 #define THR_POLL_TO 5000
36
37 #define MAD_HDR_SIZE sizeof(struct ibv_grh)
38
39 typedef struct BackendCtx {
40 void *up_ctx;
41 struct ibv_sge sge; /* Used to save MAD recv buffer */
42 RdmaBackendQP *backend_qp; /* To maintain recv buffers */
43 RdmaBackendSRQ *backend_srq;
44 } BackendCtx;
45
46 struct backend_umad {
47 struct ib_user_mad hdr;
48 char mad[RDMA_MAX_PRIVATE_DATA];
49 };
50
51 static void (*comp_handler)(void *ctx, struct ibv_wc *wc);
52
53 static void dummy_comp_handler(void *ctx, struct ibv_wc *wc)
54 {
55 rdma_error_report("No completion handler is registered");
56 }
57
58 static inline void complete_work(enum ibv_wc_status status, uint32_t vendor_err,
59 void *ctx)
60 {
61 struct ibv_wc wc = {};
62
63 wc.status = status;
64 wc.vendor_err = vendor_err;
65
66 comp_handler(ctx, &wc);
67 }
68
69 static void free_cqe_ctx(gpointer data, gpointer user_data)
70 {
71 BackendCtx *bctx;
72 RdmaDeviceResources *rdma_dev_res = user_data;
73 unsigned long cqe_ctx_id = GPOINTER_TO_INT(data);
74
75 bctx = rdma_rm_get_cqe_ctx(rdma_dev_res, cqe_ctx_id);
76 if (bctx) {
77 rdma_rm_dealloc_cqe_ctx(rdma_dev_res, cqe_ctx_id);
78 atomic_dec(&rdma_dev_res->stats.missing_cqe);
79 }
80 g_free(bctx);
81 }
82
83 static void clean_recv_mads(RdmaBackendDev *backend_dev)
84 {
85 unsigned long cqe_ctx_id;
86
87 do {
88 cqe_ctx_id = rdma_protected_qlist_pop_int64(&backend_dev->
89 recv_mads_list);
90 if (cqe_ctx_id != -ENOENT) {
91 atomic_inc(&backend_dev->rdma_dev_res->stats.missing_cqe);
92 free_cqe_ctx(GINT_TO_POINTER(cqe_ctx_id),
93 backend_dev->rdma_dev_res);
94 }
95 } while (cqe_ctx_id != -ENOENT);
96 }
97
98 static int rdma_poll_cq(RdmaDeviceResources *rdma_dev_res, struct ibv_cq *ibcq)
99 {
100 int i, ne, total_ne = 0;
101 BackendCtx *bctx;
102 struct ibv_wc wc[2];
103 RdmaProtectedGSList *cqe_ctx_list;
104
105 qemu_mutex_lock(&rdma_dev_res->lock);
106 do {
107 ne = ibv_poll_cq(ibcq, ARRAY_SIZE(wc), wc);
108
109 trace_rdma_poll_cq(ne, ibcq);
110
111 for (i = 0; i < ne; i++) {
112 bctx = rdma_rm_get_cqe_ctx(rdma_dev_res, wc[i].wr_id);
113 if (unlikely(!bctx)) {
114 rdma_error_report("No matching ctx for req %"PRId64,
115 wc[i].wr_id);
116 continue;
117 }
118
119 comp_handler(bctx->up_ctx, &wc[i]);
120
121 if (bctx->backend_qp) {
122 cqe_ctx_list = &bctx->backend_qp->cqe_ctx_list;
123 } else {
124 cqe_ctx_list = &bctx->backend_srq->cqe_ctx_list;
125 }
126
127 rdma_protected_gslist_remove_int32(cqe_ctx_list, wc[i].wr_id);
128 rdma_rm_dealloc_cqe_ctx(rdma_dev_res, wc[i].wr_id);
129 g_free(bctx);
130 }
131 total_ne += ne;
132 } while (ne > 0);
133 atomic_sub(&rdma_dev_res->stats.missing_cqe, total_ne);
134 qemu_mutex_unlock(&rdma_dev_res->lock);
135
136 if (ne < 0) {
137 rdma_error_report("ibv_poll_cq fail, rc=%d, errno=%d", ne, errno);
138 }
139
140 rdma_dev_res->stats.completions += total_ne;
141
142 return total_ne;
143 }
144
145 static void *comp_handler_thread(void *arg)
146 {
147 RdmaBackendDev *backend_dev = (RdmaBackendDev *)arg;
148 int rc;
149 struct ibv_cq *ev_cq;
150 void *ev_ctx;
151 int flags;
152 GPollFD pfds[1];
153
154 /* Change to non-blocking mode */
155 flags = fcntl(backend_dev->channel->fd, F_GETFL);
156 rc = fcntl(backend_dev->channel->fd, F_SETFL, flags | O_NONBLOCK);
157 if (rc < 0) {
158 rdma_error_report("Failed to change backend channel FD to non-blocking");
159 return NULL;
160 }
161
162 pfds[0].fd = backend_dev->channel->fd;
163 pfds[0].events = G_IO_IN | G_IO_HUP | G_IO_ERR;
164
165 backend_dev->comp_thread.is_running = true;
166
167 while (backend_dev->comp_thread.run) {
168 do {
169 rc = qemu_poll_ns(pfds, 1, THR_POLL_TO * (int64_t)SCALE_MS);
170 if (!rc) {
171 backend_dev->rdma_dev_res->stats.poll_cq_ppoll_to++;
172 }
173 } while (!rc && backend_dev->comp_thread.run);
174
175 if (backend_dev->comp_thread.run) {
176 rc = ibv_get_cq_event(backend_dev->channel, &ev_cq, &ev_ctx);
177 if (unlikely(rc)) {
178 rdma_error_report("ibv_get_cq_event fail, rc=%d, errno=%d", rc,
179 errno);
180 continue;
181 }
182
183 rc = ibv_req_notify_cq(ev_cq, 0);
184 if (unlikely(rc)) {
185 rdma_error_report("ibv_req_notify_cq fail, rc=%d, errno=%d", rc,
186 errno);
187 }
188
189 backend_dev->rdma_dev_res->stats.poll_cq_from_bk++;
190 rdma_poll_cq(backend_dev->rdma_dev_res, ev_cq);
191
192 ibv_ack_cq_events(ev_cq, 1);
193 }
194 }
195
196 backend_dev->comp_thread.is_running = false;
197
198 qemu_thread_exit(0);
199
200 return NULL;
201 }
202
203 static inline void disable_rdmacm_mux_async(RdmaBackendDev *backend_dev)
204 {
205 atomic_set(&backend_dev->rdmacm_mux.can_receive, 0);
206 }
207
208 static inline void enable_rdmacm_mux_async(RdmaBackendDev *backend_dev)
209 {
210 atomic_set(&backend_dev->rdmacm_mux.can_receive, sizeof(RdmaCmMuxMsg));
211 }
212
213 static inline int rdmacm_mux_can_process_async(RdmaBackendDev *backend_dev)
214 {
215 return atomic_read(&backend_dev->rdmacm_mux.can_receive);
216 }
217
218 static int rdmacm_mux_check_op_status(CharBackend *mad_chr_be)
219 {
220 RdmaCmMuxMsg msg = {};
221 int ret;
222
223 ret = qemu_chr_fe_read_all(mad_chr_be, (uint8_t *)&msg, sizeof(msg));
224 if (ret != sizeof(msg)) {
225 rdma_error_report("Got invalid message from mux: size %d, expecting %d",
226 ret, (int)sizeof(msg));
227 return -EIO;
228 }
229
230 trace_rdmacm_mux_check_op_status(msg.hdr.msg_type, msg.hdr.op_code,
231 msg.hdr.err_code);
232
233 if (msg.hdr.msg_type != RDMACM_MUX_MSG_TYPE_RESP) {
234 rdma_error_report("Got invalid message type %d", msg.hdr.msg_type);
235 return -EIO;
236 }
237
238 if (msg.hdr.err_code != RDMACM_MUX_ERR_CODE_OK) {
239 rdma_error_report("Operation failed in mux, error code %d",
240 msg.hdr.err_code);
241 return -EIO;
242 }
243
244 return 0;
245 }
246
247 static int rdmacm_mux_send(RdmaBackendDev *backend_dev, RdmaCmMuxMsg *msg)
248 {
249 int rc = 0;
250
251 msg->hdr.msg_type = RDMACM_MUX_MSG_TYPE_REQ;
252 trace_rdmacm_mux("send", msg->hdr.msg_type, msg->hdr.op_code);
253 disable_rdmacm_mux_async(backend_dev);
254 rc = qemu_chr_fe_write(backend_dev->rdmacm_mux.chr_be,
255 (const uint8_t *)msg, sizeof(*msg));
256 if (rc != sizeof(*msg)) {
257 enable_rdmacm_mux_async(backend_dev);
258 rdma_error_report("Failed to send request to rdmacm_mux (rc=%d)", rc);
259 return -EIO;
260 }
261
262 rc = rdmacm_mux_check_op_status(backend_dev->rdmacm_mux.chr_be);
263 if (rc) {
264 rdma_error_report("Failed to execute rdmacm_mux request %d (rc=%d)",
265 msg->hdr.op_code, rc);
266 }
267
268 enable_rdmacm_mux_async(backend_dev);
269
270 return 0;
271 }
272
273 static void stop_backend_thread(RdmaBackendThread *thread)
274 {
275 thread->run = false;
276 while (thread->is_running) {
277 sleep(THR_POLL_TO / SCALE_US / 2);
278 }
279 }
280
281 static void start_comp_thread(RdmaBackendDev *backend_dev)
282 {
283 char thread_name[THR_NAME_LEN] = {};
284
285 stop_backend_thread(&backend_dev->comp_thread);
286
287 snprintf(thread_name, sizeof(thread_name), "rdma_comp_%s",
288 ibv_get_device_name(backend_dev->ib_dev));
289 backend_dev->comp_thread.run = true;
290 qemu_thread_create(&backend_dev->comp_thread.thread, thread_name,
291 comp_handler_thread, backend_dev, QEMU_THREAD_DETACHED);
292 }
293
294 void rdma_backend_register_comp_handler(void (*handler)(void *ctx,
295 struct ibv_wc *wc))
296 {
297 comp_handler = handler;
298 }
299
300 void rdma_backend_unregister_comp_handler(void)
301 {
302 rdma_backend_register_comp_handler(dummy_comp_handler);
303 }
304
305 int rdma_backend_query_port(RdmaBackendDev *backend_dev,
306 struct ibv_port_attr *port_attr)
307 {
308 int rc;
309
310 rc = ibv_query_port(backend_dev->context, backend_dev->port_num, port_attr);
311 if (rc) {
312 rdma_error_report("ibv_query_port fail, rc=%d, errno=%d", rc, errno);
313 return -EIO;
314 }
315
316 return 0;
317 }
318
319 void rdma_backend_poll_cq(RdmaDeviceResources *rdma_dev_res, RdmaBackendCQ *cq)
320 {
321 int polled;
322
323 rdma_dev_res->stats.poll_cq_from_guest++;
324 polled = rdma_poll_cq(rdma_dev_res, cq->ibcq);
325 if (!polled) {
326 rdma_dev_res->stats.poll_cq_from_guest_empty++;
327 }
328 }
329
330 static GHashTable *ah_hash;
331
332 static struct ibv_ah *create_ah(RdmaBackendDev *backend_dev, struct ibv_pd *pd,
333 uint8_t sgid_idx, union ibv_gid *dgid)
334 {
335 GBytes *ah_key = g_bytes_new(dgid, sizeof(*dgid));
336 struct ibv_ah *ah = g_hash_table_lookup(ah_hash, ah_key);
337
338 if (ah) {
339 trace_rdma_create_ah_cache_hit(be64_to_cpu(dgid->global.subnet_prefix),
340 be64_to_cpu(dgid->global.interface_id));
341 g_bytes_unref(ah_key);
342 } else {
343 struct ibv_ah_attr ah_attr = {
344 .is_global = 1,
345 .port_num = backend_dev->port_num,
346 .grh.hop_limit = 1,
347 };
348
349 ah_attr.grh.dgid = *dgid;
350 ah_attr.grh.sgid_index = sgid_idx;
351
352 ah = ibv_create_ah(pd, &ah_attr);
353 if (ah) {
354 g_hash_table_insert(ah_hash, ah_key, ah);
355 } else {
356 g_bytes_unref(ah_key);
357 rdma_error_report("Failed to create AH for gid <0x%" PRIx64", 0x%"PRIx64">",
358 be64_to_cpu(dgid->global.subnet_prefix),
359 be64_to_cpu(dgid->global.interface_id));
360 }
361
362 trace_rdma_create_ah_cache_miss(be64_to_cpu(dgid->global.subnet_prefix),
363 be64_to_cpu(dgid->global.interface_id));
364 }
365
366 return ah;
367 }
368
369 static void destroy_ah_hash_key(gpointer data)
370 {
371 g_bytes_unref(data);
372 }
373
374 static void destroy_ah_hast_data(gpointer data)
375 {
376 struct ibv_ah *ah = data;
377
378 ibv_destroy_ah(ah);
379 }
380
381 static void ah_cache_init(void)
382 {
383 ah_hash = g_hash_table_new_full(g_bytes_hash, g_bytes_equal,
384 destroy_ah_hash_key, destroy_ah_hast_data);
385 }
386
387 static int build_host_sge_array(RdmaDeviceResources *rdma_dev_res,
388 struct ibv_sge *dsge, struct ibv_sge *ssge,
389 uint8_t num_sge, uint64_t *total_length)
390 {
391 RdmaRmMR *mr;
392 int ssge_idx;
393
394 for (ssge_idx = 0; ssge_idx < num_sge; ssge_idx++) {
395 mr = rdma_rm_get_mr(rdma_dev_res, ssge[ssge_idx].lkey);
396 if (unlikely(!mr)) {
397 rdma_error_report("Invalid lkey 0x%x", ssge[ssge_idx].lkey);
398 return VENDOR_ERR_INVLKEY | ssge[ssge_idx].lkey;
399 }
400
401 dsge->addr = (uintptr_t)mr->virt + ssge[ssge_idx].addr - mr->start;
402 dsge->length = ssge[ssge_idx].length;
403 dsge->lkey = rdma_backend_mr_lkey(&mr->backend_mr);
404
405 *total_length += dsge->length;
406
407 dsge++;
408 }
409
410 return 0;
411 }
412
413 static void trace_mad_message(const char *title, char *buf, int len)
414 {
415 int i;
416 char *b = g_malloc0(len * 3 + 1);
417 char b1[4];
418
419 for (i = 0; i < len; i++) {
420 sprintf(b1, "%.2X ", buf[i] & 0x000000FF);
421 strcat(b, b1);
422 }
423
424 trace_rdma_mad_message(title, len, b);
425
426 g_free(b);
427 }
428
429 static int mad_send(RdmaBackendDev *backend_dev, uint8_t sgid_idx,
430 union ibv_gid *sgid, struct ibv_sge *sge, uint32_t num_sge)
431 {
432 RdmaCmMuxMsg msg = {};
433 char *hdr, *data;
434 int ret;
435
436 if (num_sge != 2) {
437 return -EINVAL;
438 }
439
440 msg.hdr.op_code = RDMACM_MUX_OP_CODE_MAD;
441 memcpy(msg.hdr.sgid.raw, sgid->raw, sizeof(msg.hdr.sgid));
442
443 msg.umad_len = sge[0].length + sge[1].length;
444
445 if (msg.umad_len > sizeof(msg.umad.mad)) {
446 return -ENOMEM;
447 }
448
449 msg.umad.hdr.addr.qpn = htobe32(1);
450 msg.umad.hdr.addr.grh_present = 1;
451 msg.umad.hdr.addr.gid_index = sgid_idx;
452 memcpy(msg.umad.hdr.addr.gid, sgid->raw, sizeof(msg.umad.hdr.addr.gid));
453 msg.umad.hdr.addr.hop_limit = 0xFF;
454
455 hdr = rdma_pci_dma_map(backend_dev->dev, sge[0].addr, sge[0].length);
456 if (!hdr) {
457 return -ENOMEM;
458 }
459 data = rdma_pci_dma_map(backend_dev->dev, sge[1].addr, sge[1].length);
460 if (!data) {
461 rdma_pci_dma_unmap(backend_dev->dev, hdr, sge[0].length);
462 return -ENOMEM;
463 }
464
465 memcpy(&msg.umad.mad[0], hdr, sge[0].length);
466 memcpy(&msg.umad.mad[sge[0].length], data, sge[1].length);
467
468 rdma_pci_dma_unmap(backend_dev->dev, data, sge[1].length);
469 rdma_pci_dma_unmap(backend_dev->dev, hdr, sge[0].length);
470
471 trace_mad_message("send", msg.umad.mad, msg.umad_len);
472
473 ret = rdmacm_mux_send(backend_dev, &msg);
474 if (ret) {
475 rdma_error_report("Failed to send MAD to rdma_umadmux (%d)", ret);
476 return -EIO;
477 }
478
479 return 0;
480 }
481
482 void rdma_backend_post_send(RdmaBackendDev *backend_dev,
483 RdmaBackendQP *qp, uint8_t qp_type,
484 struct ibv_sge *sge, uint32_t num_sge,
485 uint8_t sgid_idx, union ibv_gid *sgid,
486 union ibv_gid *dgid, uint32_t dqpn, uint32_t dqkey,
487 void *ctx)
488 {
489 BackendCtx *bctx;
490 struct ibv_sge new_sge[MAX_SGE];
491 uint32_t bctx_id;
492 int rc;
493 struct ibv_send_wr wr = {}, *bad_wr;
494
495 if (!qp->ibqp) { /* This field is not initialized for QP0 and QP1 */
496 if (qp_type == IBV_QPT_SMI) {
497 rdma_error_report("Got QP0 request");
498 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_QP0, ctx);
499 } else if (qp_type == IBV_QPT_GSI) {
500 rc = mad_send(backend_dev, sgid_idx, sgid, sge, num_sge);
501 if (rc) {
502 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_MAD_SEND, ctx);
503 backend_dev->rdma_dev_res->stats.mad_tx_err++;
504 } else {
505 complete_work(IBV_WC_SUCCESS, 0, ctx);
506 backend_dev->rdma_dev_res->stats.mad_tx++;
507 }
508 }
509 return;
510 }
511
512 bctx = g_malloc0(sizeof(*bctx));
513 bctx->up_ctx = ctx;
514 bctx->backend_qp = qp;
515
516 rc = rdma_rm_alloc_cqe_ctx(backend_dev->rdma_dev_res, &bctx_id, bctx);
517 if (unlikely(rc)) {
518 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_NOMEM, ctx);
519 goto err_free_bctx;
520 }
521
522 rdma_protected_gslist_append_int32(&qp->cqe_ctx_list, bctx_id);
523
524 rc = build_host_sge_array(backend_dev->rdma_dev_res, new_sge, sge, num_sge,
525 &backend_dev->rdma_dev_res->stats.tx_len);
526 if (rc) {
527 complete_work(IBV_WC_GENERAL_ERR, rc, ctx);
528 goto err_dealloc_cqe_ctx;
529 }
530
531 if (qp_type == IBV_QPT_UD) {
532 wr.wr.ud.ah = create_ah(backend_dev, qp->ibpd, sgid_idx, dgid);
533 if (!wr.wr.ud.ah) {
534 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_FAIL_BACKEND, ctx);
535 goto err_dealloc_cqe_ctx;
536 }
537 wr.wr.ud.remote_qpn = dqpn;
538 wr.wr.ud.remote_qkey = dqkey;
539 }
540
541 wr.num_sge = num_sge;
542 wr.opcode = IBV_WR_SEND;
543 wr.send_flags = IBV_SEND_SIGNALED;
544 wr.sg_list = new_sge;
545 wr.wr_id = bctx_id;
546
547 rc = ibv_post_send(qp->ibqp, &wr, &bad_wr);
548 if (rc) {
549 rdma_error_report("ibv_post_send fail, qpn=0x%x, rc=%d, errno=%d",
550 qp->ibqp->qp_num, rc, errno);
551 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_FAIL_BACKEND, ctx);
552 goto err_dealloc_cqe_ctx;
553 }
554
555 atomic_inc(&backend_dev->rdma_dev_res->stats.missing_cqe);
556 backend_dev->rdma_dev_res->stats.tx++;
557
558 return;
559
560 err_dealloc_cqe_ctx:
561 backend_dev->rdma_dev_res->stats.tx_err++;
562 rdma_rm_dealloc_cqe_ctx(backend_dev->rdma_dev_res, bctx_id);
563
564 err_free_bctx:
565 g_free(bctx);
566 }
567
568 static unsigned int save_mad_recv_buffer(RdmaBackendDev *backend_dev,
569 struct ibv_sge *sge, uint32_t num_sge,
570 void *ctx)
571 {
572 BackendCtx *bctx;
573 int rc;
574 uint32_t bctx_id;
575
576 if (num_sge != 1) {
577 rdma_error_report("Invalid num_sge (%d), expecting 1", num_sge);
578 return VENDOR_ERR_INV_NUM_SGE;
579 }
580
581 if (sge[0].length < RDMA_MAX_PRIVATE_DATA + sizeof(struct ibv_grh)) {
582 rdma_error_report("Too small buffer for MAD");
583 return VENDOR_ERR_INV_MAD_BUFF;
584 }
585
586 bctx = g_malloc0(sizeof(*bctx));
587
588 rc = rdma_rm_alloc_cqe_ctx(backend_dev->rdma_dev_res, &bctx_id, bctx);
589 if (unlikely(rc)) {
590 g_free(bctx);
591 return VENDOR_ERR_NOMEM;
592 }
593
594 bctx->up_ctx = ctx;
595 bctx->sge = *sge;
596
597 rdma_protected_qlist_append_int64(&backend_dev->recv_mads_list, bctx_id);
598
599 return 0;
600 }
601
602 void rdma_backend_post_recv(RdmaBackendDev *backend_dev,
603 RdmaBackendQP *qp, uint8_t qp_type,
604 struct ibv_sge *sge, uint32_t num_sge, void *ctx)
605 {
606 BackendCtx *bctx;
607 struct ibv_sge new_sge[MAX_SGE];
608 uint32_t bctx_id;
609 int rc;
610 struct ibv_recv_wr wr = {}, *bad_wr;
611
612 if (!qp->ibqp) { /* This field does not get initialized for QP0 and QP1 */
613 if (qp_type == IBV_QPT_SMI) {
614 rdma_error_report("Got QP0 request");
615 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_QP0, ctx);
616 }
617 if (qp_type == IBV_QPT_GSI) {
618 rc = save_mad_recv_buffer(backend_dev, sge, num_sge, ctx);
619 if (rc) {
620 complete_work(IBV_WC_GENERAL_ERR, rc, ctx);
621 backend_dev->rdma_dev_res->stats.mad_rx_bufs_err++;
622 } else {
623 backend_dev->rdma_dev_res->stats.mad_rx_bufs++;
624 }
625 }
626 return;
627 }
628
629 bctx = g_malloc0(sizeof(*bctx));
630 bctx->up_ctx = ctx;
631 bctx->backend_qp = qp;
632
633 rc = rdma_rm_alloc_cqe_ctx(backend_dev->rdma_dev_res, &bctx_id, bctx);
634 if (unlikely(rc)) {
635 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_NOMEM, ctx);
636 goto err_free_bctx;
637 }
638
639 rdma_protected_gslist_append_int32(&qp->cqe_ctx_list, bctx_id);
640
641 rc = build_host_sge_array(backend_dev->rdma_dev_res, new_sge, sge, num_sge,
642 &backend_dev->rdma_dev_res->stats.rx_bufs_len);
643 if (rc) {
644 complete_work(IBV_WC_GENERAL_ERR, rc, ctx);
645 goto err_dealloc_cqe_ctx;
646 }
647
648 wr.num_sge = num_sge;
649 wr.sg_list = new_sge;
650 wr.wr_id = bctx_id;
651 rc = ibv_post_recv(qp->ibqp, &wr, &bad_wr);
652 if (rc) {
653 rdma_error_report("ibv_post_recv fail, qpn=0x%x, rc=%d, errno=%d",
654 qp->ibqp->qp_num, rc, errno);
655 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_FAIL_BACKEND, ctx);
656 goto err_dealloc_cqe_ctx;
657 }
658
659 atomic_inc(&backend_dev->rdma_dev_res->stats.missing_cqe);
660 backend_dev->rdma_dev_res->stats.rx_bufs++;
661
662 return;
663
664 err_dealloc_cqe_ctx:
665 backend_dev->rdma_dev_res->stats.rx_bufs_err++;
666 rdma_rm_dealloc_cqe_ctx(backend_dev->rdma_dev_res, bctx_id);
667
668 err_free_bctx:
669 g_free(bctx);
670 }
671
672 void rdma_backend_post_srq_recv(RdmaBackendDev *backend_dev,
673 RdmaBackendSRQ *srq, struct ibv_sge *sge,
674 uint32_t num_sge, void *ctx)
675 {
676 BackendCtx *bctx;
677 struct ibv_sge new_sge[MAX_SGE];
678 uint32_t bctx_id;
679 int rc;
680 struct ibv_recv_wr wr = {}, *bad_wr;
681
682 bctx = g_malloc0(sizeof(*bctx));
683 bctx->up_ctx = ctx;
684 bctx->backend_srq = srq;
685
686 rc = rdma_rm_alloc_cqe_ctx(backend_dev->rdma_dev_res, &bctx_id, bctx);
687 if (unlikely(rc)) {
688 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_NOMEM, ctx);
689 goto err_free_bctx;
690 }
691
692 rdma_protected_gslist_append_int32(&srq->cqe_ctx_list, bctx_id);
693
694 rc = build_host_sge_array(backend_dev->rdma_dev_res, new_sge, sge, num_sge,
695 &backend_dev->rdma_dev_res->stats.rx_bufs_len);
696 if (rc) {
697 complete_work(IBV_WC_GENERAL_ERR, rc, ctx);
698 goto err_dealloc_cqe_ctx;
699 }
700
701 wr.num_sge = num_sge;
702 wr.sg_list = new_sge;
703 wr.wr_id = bctx_id;
704 rc = ibv_post_srq_recv(srq->ibsrq, &wr, &bad_wr);
705 if (rc) {
706 rdma_error_report("ibv_post_srq_recv fail, srqn=0x%x, rc=%d, errno=%d",
707 srq->ibsrq->handle, rc, errno);
708 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_FAIL_BACKEND, ctx);
709 goto err_dealloc_cqe_ctx;
710 }
711
712 atomic_inc(&backend_dev->rdma_dev_res->stats.missing_cqe);
713 backend_dev->rdma_dev_res->stats.rx_bufs++;
714 backend_dev->rdma_dev_res->stats.rx_srq++;
715
716 return;
717
718 err_dealloc_cqe_ctx:
719 backend_dev->rdma_dev_res->stats.rx_bufs_err++;
720 rdma_rm_dealloc_cqe_ctx(backend_dev->rdma_dev_res, bctx_id);
721
722 err_free_bctx:
723 g_free(bctx);
724 }
725
726 int rdma_backend_create_pd(RdmaBackendDev *backend_dev, RdmaBackendPD *pd)
727 {
728 pd->ibpd = ibv_alloc_pd(backend_dev->context);
729
730 if (!pd->ibpd) {
731 rdma_error_report("ibv_alloc_pd fail, errno=%d", errno);
732 return -EIO;
733 }
734
735 return 0;
736 }
737
738 void rdma_backend_destroy_pd(RdmaBackendPD *pd)
739 {
740 if (pd->ibpd) {
741 ibv_dealloc_pd(pd->ibpd);
742 }
743 }
744
745 int rdma_backend_create_mr(RdmaBackendMR *mr, RdmaBackendPD *pd, void *addr,
746 size_t length, int access)
747 {
748 mr->ibmr = ibv_reg_mr(pd->ibpd, addr, length, access);
749 if (!mr->ibmr) {
750 rdma_error_report("ibv_reg_mr fail, errno=%d", errno);
751 return -EIO;
752 }
753
754 mr->ibpd = pd->ibpd;
755
756 return 0;
757 }
758
759 void rdma_backend_destroy_mr(RdmaBackendMR *mr)
760 {
761 if (mr->ibmr) {
762 ibv_dereg_mr(mr->ibmr);
763 }
764 }
765
766 int rdma_backend_create_cq(RdmaBackendDev *backend_dev, RdmaBackendCQ *cq,
767 int cqe)
768 {
769 int rc;
770
771 cq->ibcq = ibv_create_cq(backend_dev->context, cqe + 1, NULL,
772 backend_dev->channel, 0);
773 if (!cq->ibcq) {
774 rdma_error_report("ibv_create_cq fail, errno=%d", errno);
775 return -EIO;
776 }
777
778 rc = ibv_req_notify_cq(cq->ibcq, 0);
779 if (rc) {
780 rdma_warn_report("ibv_req_notify_cq fail, rc=%d, errno=%d", rc, errno);
781 }
782
783 cq->backend_dev = backend_dev;
784
785 return 0;
786 }
787
788 void rdma_backend_destroy_cq(RdmaBackendCQ *cq)
789 {
790 if (cq->ibcq) {
791 ibv_destroy_cq(cq->ibcq);
792 }
793 }
794
795 int rdma_backend_create_qp(RdmaBackendQP *qp, uint8_t qp_type,
796 RdmaBackendPD *pd, RdmaBackendCQ *scq,
797 RdmaBackendCQ *rcq, uint32_t max_send_wr,
798 uint32_t max_recv_wr, uint32_t max_send_sge,
799 uint32_t max_recv_sge)
800 {
801 struct ibv_qp_init_attr attr = {};
802
803 qp->ibqp = 0;
804
805 switch (qp_type) {
806 case IBV_QPT_GSI:
807 return 0;
808
809 case IBV_QPT_RC:
810 /* fall through */
811 case IBV_QPT_UD:
812 /* do nothing */
813 break;
814
815 default:
816 rdma_error_report("Unsupported QP type %d", qp_type);
817 return -EIO;
818 }
819
820 attr.qp_type = qp_type;
821 attr.send_cq = scq->ibcq;
822 attr.recv_cq = rcq->ibcq;
823 attr.cap.max_send_wr = max_send_wr;
824 attr.cap.max_recv_wr = max_recv_wr;
825 attr.cap.max_send_sge = max_send_sge;
826 attr.cap.max_recv_sge = max_recv_sge;
827
828 qp->ibqp = ibv_create_qp(pd->ibpd, &attr);
829 if (!qp->ibqp) {
830 rdma_error_report("ibv_create_qp fail, errno=%d", errno);
831 return -EIO;
832 }
833
834 rdma_protected_gslist_init(&qp->cqe_ctx_list);
835
836 qp->ibpd = pd->ibpd;
837
838 /* TODO: Query QP to get max_inline_data and save it to be used in send */
839
840 return 0;
841 }
842
843 int rdma_backend_qp_state_init(RdmaBackendDev *backend_dev, RdmaBackendQP *qp,
844 uint8_t qp_type, uint32_t qkey)
845 {
846 struct ibv_qp_attr attr = {};
847 int rc, attr_mask;
848
849 attr_mask = IBV_QP_STATE | IBV_QP_PKEY_INDEX | IBV_QP_PORT;
850 attr.qp_state = IBV_QPS_INIT;
851 attr.pkey_index = 0;
852 attr.port_num = backend_dev->port_num;
853
854 switch (qp_type) {
855 case IBV_QPT_RC:
856 attr_mask |= IBV_QP_ACCESS_FLAGS;
857 trace_rdma_backend_rc_qp_state_init(qp->ibqp->qp_num);
858 break;
859
860 case IBV_QPT_UD:
861 attr.qkey = qkey;
862 attr_mask |= IBV_QP_QKEY;
863 trace_rdma_backend_ud_qp_state_init(qp->ibqp->qp_num, qkey);
864 break;
865
866 default:
867 rdma_error_report("Unsupported QP type %d", qp_type);
868 return -EIO;
869 }
870
871 rc = ibv_modify_qp(qp->ibqp, &attr, attr_mask);
872 if (rc) {
873 rdma_error_report("ibv_modify_qp fail, rc=%d, errno=%d", rc, errno);
874 return -EIO;
875 }
876
877 return 0;
878 }
879
880 int rdma_backend_qp_state_rtr(RdmaBackendDev *backend_dev, RdmaBackendQP *qp,
881 uint8_t qp_type, uint8_t sgid_idx,
882 union ibv_gid *dgid, uint32_t dqpn,
883 uint32_t rq_psn, uint32_t qkey, bool use_qkey)
884 {
885 struct ibv_qp_attr attr = {};
886 union ibv_gid ibv_gid = {
887 .global.interface_id = dgid->global.interface_id,
888 .global.subnet_prefix = dgid->global.subnet_prefix
889 };
890 int rc, attr_mask;
891
892 attr.qp_state = IBV_QPS_RTR;
893 attr_mask = IBV_QP_STATE;
894
895 qp->sgid_idx = sgid_idx;
896
897 switch (qp_type) {
898 case IBV_QPT_RC:
899 attr.path_mtu = IBV_MTU_1024;
900 attr.dest_qp_num = dqpn;
901 attr.max_dest_rd_atomic = 1;
902 attr.min_rnr_timer = 12;
903 attr.ah_attr.port_num = backend_dev->port_num;
904 attr.ah_attr.is_global = 1;
905 attr.ah_attr.grh.hop_limit = 1;
906 attr.ah_attr.grh.dgid = ibv_gid;
907 attr.ah_attr.grh.sgid_index = qp->sgid_idx;
908 attr.rq_psn = rq_psn;
909
910 attr_mask |= IBV_QP_AV | IBV_QP_PATH_MTU | IBV_QP_DEST_QPN |
911 IBV_QP_RQ_PSN | IBV_QP_MAX_DEST_RD_ATOMIC |
912 IBV_QP_MIN_RNR_TIMER;
913
914 trace_rdma_backend_rc_qp_state_rtr(qp->ibqp->qp_num,
915 be64_to_cpu(ibv_gid.global.
916 subnet_prefix),
917 be64_to_cpu(ibv_gid.global.
918 interface_id),
919 qp->sgid_idx, dqpn, rq_psn);
920 break;
921
922 case IBV_QPT_UD:
923 if (use_qkey) {
924 attr.qkey = qkey;
925 attr_mask |= IBV_QP_QKEY;
926 }
927 trace_rdma_backend_ud_qp_state_rtr(qp->ibqp->qp_num, use_qkey ? qkey :
928 0);
929 break;
930 }
931
932 rc = ibv_modify_qp(qp->ibqp, &attr, attr_mask);
933 if (rc) {
934 rdma_error_report("ibv_modify_qp fail, rc=%d, errno=%d", rc, errno);
935 return -EIO;
936 }
937
938 return 0;
939 }
940
941 int rdma_backend_qp_state_rts(RdmaBackendQP *qp, uint8_t qp_type,
942 uint32_t sq_psn, uint32_t qkey, bool use_qkey)
943 {
944 struct ibv_qp_attr attr = {};
945 int rc, attr_mask;
946
947 attr.qp_state = IBV_QPS_RTS;
948 attr.sq_psn = sq_psn;
949 attr_mask = IBV_QP_STATE | IBV_QP_SQ_PSN;
950
951 switch (qp_type) {
952 case IBV_QPT_RC:
953 attr.timeout = 14;
954 attr.retry_cnt = 7;
955 attr.rnr_retry = 7;
956 attr.max_rd_atomic = 1;
957
958 attr_mask |= IBV_QP_TIMEOUT | IBV_QP_RETRY_CNT | IBV_QP_RNR_RETRY |
959 IBV_QP_MAX_QP_RD_ATOMIC;
960 trace_rdma_backend_rc_qp_state_rts(qp->ibqp->qp_num, sq_psn);
961 break;
962
963 case IBV_QPT_UD:
964 if (use_qkey) {
965 attr.qkey = qkey;
966 attr_mask |= IBV_QP_QKEY;
967 }
968 trace_rdma_backend_ud_qp_state_rts(qp->ibqp->qp_num, sq_psn,
969 use_qkey ? qkey : 0);
970 break;
971 }
972
973 rc = ibv_modify_qp(qp->ibqp, &attr, attr_mask);
974 if (rc) {
975 rdma_error_report("ibv_modify_qp fail, rc=%d, errno=%d", rc, errno);
976 return -EIO;
977 }
978
979 return 0;
980 }
981
982 int rdma_backend_query_qp(RdmaBackendQP *qp, struct ibv_qp_attr *attr,
983 int attr_mask, struct ibv_qp_init_attr *init_attr)
984 {
985 if (!qp->ibqp) {
986 attr->qp_state = IBV_QPS_RTS;
987 return 0;
988 }
989
990 return ibv_query_qp(qp->ibqp, attr, attr_mask, init_attr);
991 }
992
993 void rdma_backend_destroy_qp(RdmaBackendQP *qp, RdmaDeviceResources *dev_res)
994 {
995 if (qp->ibqp) {
996 ibv_destroy_qp(qp->ibqp);
997 }
998 g_slist_foreach(qp->cqe_ctx_list.list, free_cqe_ctx, dev_res);
999 rdma_protected_gslist_destroy(&qp->cqe_ctx_list);
1000 }
1001
1002 int rdma_backend_create_srq(RdmaBackendSRQ *srq, RdmaBackendPD *pd,
1003 uint32_t max_wr, uint32_t max_sge,
1004 uint32_t srq_limit)
1005 {
1006 struct ibv_srq_init_attr srq_init_attr = {};
1007
1008 srq_init_attr.attr.max_wr = max_wr;
1009 srq_init_attr.attr.max_sge = max_sge;
1010 srq_init_attr.attr.srq_limit = srq_limit;
1011
1012 srq->ibsrq = ibv_create_srq(pd->ibpd, &srq_init_attr);
1013 if (!srq->ibsrq) {
1014 rdma_error_report("ibv_create_srq failed, errno=%d", errno);
1015 return -EIO;
1016 }
1017
1018 rdma_protected_gslist_init(&srq->cqe_ctx_list);
1019
1020 return 0;
1021 }
1022
1023 int rdma_backend_query_srq(RdmaBackendSRQ *srq, struct ibv_srq_attr *srq_attr)
1024 {
1025 if (!srq->ibsrq) {
1026 return -EINVAL;
1027 }
1028
1029 return ibv_query_srq(srq->ibsrq, srq_attr);
1030 }
1031
1032 int rdma_backend_modify_srq(RdmaBackendSRQ *srq, struct ibv_srq_attr *srq_attr,
1033 int srq_attr_mask)
1034 {
1035 if (!srq->ibsrq) {
1036 return -EINVAL;
1037 }
1038
1039 return ibv_modify_srq(srq->ibsrq, srq_attr, srq_attr_mask);
1040 }
1041
1042 void rdma_backend_destroy_srq(RdmaBackendSRQ *srq, RdmaDeviceResources *dev_res)
1043 {
1044 if (srq->ibsrq) {
1045 ibv_destroy_srq(srq->ibsrq);
1046 }
1047 g_slist_foreach(srq->cqe_ctx_list.list, free_cqe_ctx, dev_res);
1048 rdma_protected_gslist_destroy(&srq->cqe_ctx_list);
1049 }
1050
1051 #define CHK_ATTR(req, dev, member, fmt) ({ \
1052 trace_rdma_check_dev_attr(#member, dev.member, req->member); \
1053 if (req->member > dev.member) { \
1054 rdma_warn_report("%s = "fmt" is higher than host device capability "fmt, \
1055 #member, req->member, dev.member); \
1056 req->member = dev.member; \
1057 } \
1058 })
1059
1060 static int init_device_caps(RdmaBackendDev *backend_dev,
1061 struct ibv_device_attr *dev_attr)
1062 {
1063 struct ibv_device_attr bk_dev_attr;
1064 int rc;
1065
1066 rc = ibv_query_device(backend_dev->context, &bk_dev_attr);
1067 if (rc) {
1068 rdma_error_report("ibv_query_device fail, rc=%d, errno=%d", rc, errno);
1069 return -EIO;
1070 }
1071
1072 dev_attr->max_sge = MAX_SGE;
1073 dev_attr->max_srq_sge = MAX_SGE;
1074
1075 CHK_ATTR(dev_attr, bk_dev_attr, max_mr_size, "%" PRId64);
1076 CHK_ATTR(dev_attr, bk_dev_attr, max_qp, "%d");
1077 CHK_ATTR(dev_attr, bk_dev_attr, max_sge, "%d");
1078 CHK_ATTR(dev_attr, bk_dev_attr, max_cq, "%d");
1079 CHK_ATTR(dev_attr, bk_dev_attr, max_mr, "%d");
1080 CHK_ATTR(dev_attr, bk_dev_attr, max_pd, "%d");
1081 CHK_ATTR(dev_attr, bk_dev_attr, max_qp_rd_atom, "%d");
1082 CHK_ATTR(dev_attr, bk_dev_attr, max_qp_init_rd_atom, "%d");
1083 CHK_ATTR(dev_attr, bk_dev_attr, max_ah, "%d");
1084 CHK_ATTR(dev_attr, bk_dev_attr, max_srq, "%d");
1085
1086 return 0;
1087 }
1088
1089 static inline void build_mad_hdr(struct ibv_grh *grh, union ibv_gid *sgid,
1090 union ibv_gid *my_gid, int paylen)
1091 {
1092 grh->paylen = htons(paylen);
1093 grh->sgid = *sgid;
1094 grh->dgid = *my_gid;
1095 }
1096
1097 static void process_incoming_mad_req(RdmaBackendDev *backend_dev,
1098 RdmaCmMuxMsg *msg)
1099 {
1100 unsigned long cqe_ctx_id;
1101 BackendCtx *bctx;
1102 char *mad;
1103
1104 trace_mad_message("recv", msg->umad.mad, msg->umad_len);
1105
1106 cqe_ctx_id = rdma_protected_qlist_pop_int64(&backend_dev->recv_mads_list);
1107 if (cqe_ctx_id == -ENOENT) {
1108 rdma_warn_report("No more free MADs buffers, waiting for a while");
1109 sleep(THR_POLL_TO);
1110 return;
1111 }
1112
1113 bctx = rdma_rm_get_cqe_ctx(backend_dev->rdma_dev_res, cqe_ctx_id);
1114 if (unlikely(!bctx)) {
1115 rdma_error_report("No matching ctx for req %ld", cqe_ctx_id);
1116 backend_dev->rdma_dev_res->stats.mad_rx_err++;
1117 return;
1118 }
1119
1120 mad = rdma_pci_dma_map(backend_dev->dev, bctx->sge.addr,
1121 bctx->sge.length);
1122 if (!mad || bctx->sge.length < msg->umad_len + MAD_HDR_SIZE) {
1123 backend_dev->rdma_dev_res->stats.mad_rx_err++;
1124 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_INV_MAD_BUFF,
1125 bctx->up_ctx);
1126 } else {
1127 struct ibv_wc wc = {};
1128 memset(mad, 0, bctx->sge.length);
1129 build_mad_hdr((struct ibv_grh *)mad,
1130 (union ibv_gid *)&msg->umad.hdr.addr.gid, &msg->hdr.sgid,
1131 msg->umad_len);
1132 memcpy(&mad[MAD_HDR_SIZE], msg->umad.mad, msg->umad_len);
1133 rdma_pci_dma_unmap(backend_dev->dev, mad, bctx->sge.length);
1134
1135 wc.byte_len = msg->umad_len;
1136 wc.status = IBV_WC_SUCCESS;
1137 wc.wc_flags = IBV_WC_GRH;
1138 backend_dev->rdma_dev_res->stats.mad_rx++;
1139 comp_handler(bctx->up_ctx, &wc);
1140 }
1141
1142 g_free(bctx);
1143 rdma_rm_dealloc_cqe_ctx(backend_dev->rdma_dev_res, cqe_ctx_id);
1144 }
1145
1146 static inline int rdmacm_mux_can_receive(void *opaque)
1147 {
1148 RdmaBackendDev *backend_dev = (RdmaBackendDev *)opaque;
1149
1150 return rdmacm_mux_can_process_async(backend_dev);
1151 }
1152
1153 static void rdmacm_mux_read(void *opaque, const uint8_t *buf, int size)
1154 {
1155 RdmaBackendDev *backend_dev = (RdmaBackendDev *)opaque;
1156 RdmaCmMuxMsg *msg = (RdmaCmMuxMsg *)buf;
1157
1158 trace_rdmacm_mux("read", msg->hdr.msg_type, msg->hdr.op_code);
1159
1160 if (msg->hdr.msg_type != RDMACM_MUX_MSG_TYPE_REQ &&
1161 msg->hdr.op_code != RDMACM_MUX_OP_CODE_MAD) {
1162 rdma_error_report("Error: Not a MAD request, skipping");
1163 return;
1164 }
1165 process_incoming_mad_req(backend_dev, msg);
1166 }
1167
1168 static int mad_init(RdmaBackendDev *backend_dev, CharBackend *mad_chr_be)
1169 {
1170 int ret;
1171
1172 backend_dev->rdmacm_mux.chr_be = mad_chr_be;
1173
1174 ret = qemu_chr_fe_backend_connected(backend_dev->rdmacm_mux.chr_be);
1175 if (!ret) {
1176 rdma_error_report("Missing chardev for MAD multiplexer");
1177 return -EIO;
1178 }
1179
1180 rdma_protected_qlist_init(&backend_dev->recv_mads_list);
1181
1182 enable_rdmacm_mux_async(backend_dev);
1183
1184 qemu_chr_fe_set_handlers(backend_dev->rdmacm_mux.chr_be,
1185 rdmacm_mux_can_receive, rdmacm_mux_read, NULL,
1186 NULL, backend_dev, NULL, true);
1187
1188 return 0;
1189 }
1190
1191 static void mad_stop(RdmaBackendDev *backend_dev)
1192 {
1193 clean_recv_mads(backend_dev);
1194 }
1195
1196 static void mad_fini(RdmaBackendDev *backend_dev)
1197 {
1198 disable_rdmacm_mux_async(backend_dev);
1199 qemu_chr_fe_disconnect(backend_dev->rdmacm_mux.chr_be);
1200 rdma_protected_qlist_destroy(&backend_dev->recv_mads_list);
1201 }
1202
1203 int rdma_backend_get_gid_index(RdmaBackendDev *backend_dev,
1204 union ibv_gid *gid)
1205 {
1206 union ibv_gid sgid;
1207 int ret;
1208 int i = 0;
1209
1210 do {
1211 ret = ibv_query_gid(backend_dev->context, backend_dev->port_num, i,
1212 &sgid);
1213 i++;
1214 } while (!ret && (memcmp(&sgid, gid, sizeof(*gid))));
1215
1216 trace_rdma_backend_get_gid_index(be64_to_cpu(gid->global.subnet_prefix),
1217 be64_to_cpu(gid->global.interface_id),
1218 i - 1);
1219
1220 return ret ? ret : i - 1;
1221 }
1222
1223 int rdma_backend_add_gid(RdmaBackendDev *backend_dev, const char *ifname,
1224 union ibv_gid *gid)
1225 {
1226 RdmaCmMuxMsg msg = {};
1227 int ret;
1228
1229 trace_rdma_backend_gid_change("add", be64_to_cpu(gid->global.subnet_prefix),
1230 be64_to_cpu(gid->global.interface_id));
1231
1232 msg.hdr.op_code = RDMACM_MUX_OP_CODE_REG;
1233 memcpy(msg.hdr.sgid.raw, gid->raw, sizeof(msg.hdr.sgid));
1234
1235 ret = rdmacm_mux_send(backend_dev, &msg);
1236 if (ret) {
1237 rdma_error_report("Failed to register GID to rdma_umadmux (%d)", ret);
1238 return -EIO;
1239 }
1240
1241 qapi_event_send_rdma_gid_status_changed(ifname, true,
1242 gid->global.subnet_prefix,
1243 gid->global.interface_id);
1244
1245 return ret;
1246 }
1247
1248 int rdma_backend_del_gid(RdmaBackendDev *backend_dev, const char *ifname,
1249 union ibv_gid *gid)
1250 {
1251 RdmaCmMuxMsg msg = {};
1252 int ret;
1253
1254 trace_rdma_backend_gid_change("del", be64_to_cpu(gid->global.subnet_prefix),
1255 be64_to_cpu(gid->global.interface_id));
1256
1257 msg.hdr.op_code = RDMACM_MUX_OP_CODE_UNREG;
1258 memcpy(msg.hdr.sgid.raw, gid->raw, sizeof(msg.hdr.sgid));
1259
1260 ret = rdmacm_mux_send(backend_dev, &msg);
1261 if (ret) {
1262 rdma_error_report("Failed to unregister GID from rdma_umadmux (%d)",
1263 ret);
1264 return -EIO;
1265 }
1266
1267 qapi_event_send_rdma_gid_status_changed(ifname, false,
1268 gid->global.subnet_prefix,
1269 gid->global.interface_id);
1270
1271 return 0;
1272 }
1273
1274 int rdma_backend_init(RdmaBackendDev *backend_dev, PCIDevice *pdev,
1275 RdmaDeviceResources *rdma_dev_res,
1276 const char *backend_device_name, uint8_t port_num,
1277 struct ibv_device_attr *dev_attr, CharBackend *mad_chr_be)
1278 {
1279 int i;
1280 int ret = 0;
1281 int num_ibv_devices;
1282 struct ibv_device **dev_list;
1283
1284 memset(backend_dev, 0, sizeof(*backend_dev));
1285
1286 backend_dev->dev = pdev;
1287 backend_dev->port_num = port_num;
1288 backend_dev->rdma_dev_res = rdma_dev_res;
1289
1290 rdma_backend_register_comp_handler(dummy_comp_handler);
1291
1292 dev_list = ibv_get_device_list(&num_ibv_devices);
1293 if (!dev_list) {
1294 rdma_error_report("Failed to get IB devices list");
1295 return -EIO;
1296 }
1297
1298 if (num_ibv_devices == 0) {
1299 rdma_error_report("No IB devices were found");
1300 ret = -ENXIO;
1301 goto out_free_dev_list;
1302 }
1303
1304 if (backend_device_name) {
1305 for (i = 0; dev_list[i]; ++i) {
1306 if (!strcmp(ibv_get_device_name(dev_list[i]),
1307 backend_device_name)) {
1308 break;
1309 }
1310 }
1311
1312 backend_dev->ib_dev = dev_list[i];
1313 if (!backend_dev->ib_dev) {
1314 rdma_error_report("Failed to find IB device %s",
1315 backend_device_name);
1316 ret = -EIO;
1317 goto out_free_dev_list;
1318 }
1319 } else {
1320 backend_dev->ib_dev = *dev_list;
1321 }
1322
1323 rdma_info_report("uverb device %s", backend_dev->ib_dev->dev_name);
1324
1325 backend_dev->context = ibv_open_device(backend_dev->ib_dev);
1326 if (!backend_dev->context) {
1327 rdma_error_report("Failed to open IB device %s",
1328 ibv_get_device_name(backend_dev->ib_dev));
1329 ret = -EIO;
1330 goto out;
1331 }
1332
1333 backend_dev->channel = ibv_create_comp_channel(backend_dev->context);
1334 if (!backend_dev->channel) {
1335 rdma_error_report("Failed to create IB communication channel");
1336 ret = -EIO;
1337 goto out_close_device;
1338 }
1339
1340 ret = init_device_caps(backend_dev, dev_attr);
1341 if (ret) {
1342 rdma_error_report("Failed to initialize device capabilities");
1343 ret = -EIO;
1344 goto out_destroy_comm_channel;
1345 }
1346
1347
1348 ret = mad_init(backend_dev, mad_chr_be);
1349 if (ret) {
1350 rdma_error_report("Failed to initialize mad");
1351 ret = -EIO;
1352 goto out_destroy_comm_channel;
1353 }
1354
1355 backend_dev->comp_thread.run = false;
1356 backend_dev->comp_thread.is_running = false;
1357
1358 ah_cache_init();
1359
1360 goto out_free_dev_list;
1361
1362 out_destroy_comm_channel:
1363 ibv_destroy_comp_channel(backend_dev->channel);
1364
1365 out_close_device:
1366 ibv_close_device(backend_dev->context);
1367
1368 out_free_dev_list:
1369 ibv_free_device_list(dev_list);
1370
1371 out:
1372 return ret;
1373 }
1374
1375
1376 void rdma_backend_start(RdmaBackendDev *backend_dev)
1377 {
1378 start_comp_thread(backend_dev);
1379 }
1380
1381 void rdma_backend_stop(RdmaBackendDev *backend_dev)
1382 {
1383 mad_stop(backend_dev);
1384 stop_backend_thread(&backend_dev->comp_thread);
1385 }
1386
1387 void rdma_backend_fini(RdmaBackendDev *backend_dev)
1388 {
1389 mad_fini(backend_dev);
1390 g_hash_table_destroy(ah_hash);
1391 ibv_destroy_comp_channel(backend_dev->channel);
1392 ibv_close_device(backend_dev->context);
1393 }