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Change MMIO callbacks to use offsets, not absolute addresses.
[mirror_qemu.git] / hw / realview_gic.c
1 /*
2 * ARM RealView Emulation Baseboard Interrupt Controller
3 *
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licenced under the GPL.
8 */
9
10 #include "hw.h"
11 #include "primecell.h"
12
13 #define GIC_NIRQ 96
14 #define NCPU 1
15
16 /* Only a single "CPU" interface is present. */
17 static inline int
18 gic_get_current_cpu(void)
19 {
20 return 0;
21 }
22
23 #include "arm_gic.c"
24
25 static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset)
26 {
27 gic_state *s = (gic_state *)opaque;
28 return gic_cpu_read(s, gic_get_current_cpu(), offset);
29 }
30
31 static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset,
32 uint32_t value)
33 {
34 gic_state *s = (gic_state *)opaque;
35 gic_cpu_write(s, gic_get_current_cpu(), offset, value);
36 }
37
38 static CPUReadMemoryFunc *realview_gic_cpu_readfn[] = {
39 realview_gic_cpu_read,
40 realview_gic_cpu_read,
41 realview_gic_cpu_read
42 };
43
44 static CPUWriteMemoryFunc *realview_gic_cpu_writefn[] = {
45 realview_gic_cpu_write,
46 realview_gic_cpu_write,
47 realview_gic_cpu_write
48 };
49
50 qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq)
51 {
52 gic_state *s;
53 int iomemtype;
54
55 s = gic_init(base + 0x1000, &parent_irq);
56 if (!s)
57 return NULL;
58 iomemtype = cpu_register_io_memory(0, realview_gic_cpu_readfn,
59 realview_gic_cpu_writefn, s);
60 cpu_register_physical_memory(base, 0x00001000, iomemtype);
61 return s->in;
62 }