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Merge tag 'pull-tcg-20240130' of https://gitlab.com/rth7680/qemu into staging
[mirror_qemu.git] / hw / riscv / Kconfig
1 config RISCV_NUMA
2 bool
3
4 config IBEX
5 bool
6
7 # RISC-V machines in alphabetical order
8
9 config MICROCHIP_PFSOC
10 bool
11 select CADENCE_SDHCI
12 select MCHP_PFSOC_DMC
13 select MCHP_PFSOC_IOSCB
14 select MCHP_PFSOC_MMUART
15 select MCHP_PFSOC_SYSREG
16 select RISCV_ACLINT
17 select SIFIVE_PDMA
18 select SIFIVE_PLIC
19 select UNIMP
20
21 config OPENTITAN
22 bool
23 select IBEX
24 select SIFIVE_PLIC
25 select UNIMP
26
27 config RISCV_VIRT
28 bool
29 imply PCI_DEVICES
30 imply VIRTIO_VGA
31 imply TEST_DEVICES
32 imply TPM_TIS_SYSBUS
33 select RISCV_NUMA
34 select GOLDFISH_RTC
35 select PCI
36 select PCI_EXPRESS_GENERIC_BRIDGE
37 select PFLASH_CFI01
38 select SERIAL
39 select RISCV_ACLINT
40 select RISCV_APLIC
41 select RISCV_IMSIC
42 select SIFIVE_PLIC
43 select SIFIVE_TEST
44 select VIRTIO_MMIO
45 select FW_CFG_DMA
46 select PLATFORM_BUS
47 select ACPI
48 select ACPI_PCI
49
50 config SHAKTI_C
51 bool
52 select RISCV_ACLINT
53 select SHAKTI_UART
54 select SIFIVE_PLIC
55 select UNIMP
56
57 config SIFIVE_E
58 bool
59 select RISCV_ACLINT
60 select SIFIVE_GPIO
61 select SIFIVE_PLIC
62 select SIFIVE_UART
63 select SIFIVE_E_PRCI
64 select SIFIVE_E_AON
65 select UNIMP
66
67 config SIFIVE_U
68 bool
69 select CADENCE
70 select RISCV_ACLINT
71 select SIFIVE_GPIO
72 select SIFIVE_PDMA
73 select SIFIVE_PLIC
74 select SIFIVE_SPI
75 select SIFIVE_UART
76 select SIFIVE_U_OTP
77 select SIFIVE_U_PRCI
78 select SIFIVE_PWM
79 select SSI_M25P80
80 select SSI_SD
81 select UNIMP
82
83 config SPIKE
84 bool
85 select RISCV_NUMA
86 select HTIF
87 select RISCV_ACLINT
88 select SIFIVE_PLIC