2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
4 * Copyright (c) 2020 Western Digital
6 * Provides a board compatible with the OpenTitan FPGA platform:
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "hw/riscv/opentitan.h"
23 #include "qapi/error.h"
24 #include "hw/boards.h"
25 #include "hw/misc/unimp.h"
26 #include "hw/riscv/boot.h"
27 #include "exec/address-spaces.h"
28 #include "qemu/units.h"
29 #include "sysemu/sysemu.h"
31 static const struct MemmapEntry
{
35 [IBEX_ROM
] = { 0x00008000, 16 * KiB
},
36 [IBEX_RAM
] = { 0x10000000, 0x10000 },
37 [IBEX_FLASH
] = { 0x20000000, 0x80000 },
38 [IBEX_UART
] = { 0x40000000, 0x10000 },
39 [IBEX_GPIO
] = { 0x40010000, 0x10000 },
40 [IBEX_SPI
] = { 0x40020000, 0x10000 },
41 [IBEX_FLASH_CTRL
] = { 0x40030000, 0x10000 },
42 [IBEX_PINMUX
] = { 0x40070000, 0x10000 },
43 [IBEX_RV_TIMER
] = { 0x40080000, 0x10000 },
44 [IBEX_PLIC
] = { 0x40090000, 0x10000 },
45 [IBEX_PWRMGR
] = { 0x400A0000, 0x10000 },
46 [IBEX_RSTMGR
] = { 0x400B0000, 0x10000 },
47 [IBEX_CLKMGR
] = { 0x400C0000, 0x10000 },
48 [IBEX_AES
] = { 0x40110000, 0x10000 },
49 [IBEX_HMAC
] = { 0x40120000, 0x10000 },
50 [IBEX_ALERT_HANDLER
] = { 0x40130000, 0x10000 },
51 [IBEX_NMI_GEN
] = { 0x40140000, 0x10000 },
52 [IBEX_USBDEV
] = { 0x40150000, 0x10000 },
53 [IBEX_PADCTRL
] = { 0x40160000, 0x10000 }
56 static void riscv_opentitan_init(MachineState
*machine
)
58 const struct MemmapEntry
*memmap
= ibex_memmap
;
59 OpenTitanState
*s
= g_new0(OpenTitanState
, 1);
60 MemoryRegion
*sys_mem
= get_system_memory();
61 MemoryRegion
*main_mem
= g_new(MemoryRegion
, 1);
64 object_initialize_child(OBJECT(machine
), "soc", &s
->soc
,
66 qdev_realize(DEVICE(&s
->soc
), NULL
, &error_abort
);
68 memory_region_init_ram(main_mem
, NULL
, "riscv.lowrisc.ibex.ram",
69 memmap
[IBEX_RAM
].size
, &error_fatal
);
70 memory_region_add_subregion(sys_mem
,
71 memmap
[IBEX_RAM
].base
, main_mem
);
74 if (machine
->firmware
) {
75 riscv_load_firmware(machine
->firmware
, memmap
[IBEX_RAM
].base
, NULL
);
78 if (machine
->kernel_filename
) {
79 riscv_load_kernel(machine
->kernel_filename
, NULL
);
83 static void riscv_opentitan_machine_init(MachineClass
*mc
)
85 mc
->desc
= "RISC-V Board compatible with OpenTitan";
86 mc
->init
= riscv_opentitan_init
;
88 mc
->default_cpu_type
= TYPE_RISCV_CPU_IBEX
;
91 DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init
)
93 static void riscv_lowrisc_ibex_soc_init(Object
*obj
)
95 LowRISCIbexSoCState
*s
= RISCV_IBEX_SOC(obj
);
97 object_initialize_child(obj
, "cpus", &s
->cpus
, TYPE_RISCV_HART_ARRAY
);
99 object_initialize_child(obj
, "plic", &s
->plic
, TYPE_IBEX_PLIC
);
101 object_initialize_child(obj
, "uart", &s
->uart
, TYPE_IBEX_UART
);
104 static void riscv_lowrisc_ibex_soc_realize(DeviceState
*dev_soc
, Error
**errp
)
106 const struct MemmapEntry
*memmap
= ibex_memmap
;
107 MachineState
*ms
= MACHINE(qdev_get_machine());
108 LowRISCIbexSoCState
*s
= RISCV_IBEX_SOC(dev_soc
);
109 MemoryRegion
*sys_mem
= get_system_memory();
112 object_property_set_str(OBJECT(&s
->cpus
), ms
->cpu_type
, "cpu-type",
114 object_property_set_int(OBJECT(&s
->cpus
), ms
->smp
.cpus
, "num-harts",
116 sysbus_realize(SYS_BUS_DEVICE(&s
->cpus
), &error_abort
);
119 memory_region_init_rom(&s
->rom
, OBJECT(dev_soc
), "riscv.lowrisc.ibex.rom",
120 memmap
[IBEX_ROM
].size
, &error_fatal
);
121 memory_region_add_subregion(sys_mem
,
122 memmap
[IBEX_ROM
].base
, &s
->rom
);
125 memory_region_init_rom(&s
->flash_mem
, OBJECT(dev_soc
), "riscv.lowrisc.ibex.flash",
126 memmap
[IBEX_FLASH
].size
, &error_fatal
);
127 memory_region_add_subregion(sys_mem
, memmap
[IBEX_FLASH
].base
,
131 sysbus_realize(SYS_BUS_DEVICE(&s
->plic
), &err
);
133 error_propagate(errp
, err
);
136 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->plic
), 0, memmap
[IBEX_PLIC
].base
);
139 qdev_prop_set_chr(DEVICE(&(s
->uart
)), "chardev", serial_hd(0));
140 sysbus_realize(SYS_BUS_DEVICE(&s
->uart
), &err
);
142 error_propagate(errp
, err
);
145 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
), 0, memmap
[IBEX_UART
].base
);
146 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
),
147 0, qdev_get_gpio_in(DEVICE(&s
->plic
),
148 IBEX_UART_TX_WATERMARK_IRQ
));
149 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
),
150 1, qdev_get_gpio_in(DEVICE(&s
->plic
),
151 IBEX_UART_RX_WATERMARK_IRQ
));
152 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
),
153 2, qdev_get_gpio_in(DEVICE(&s
->plic
),
154 IBEX_UART_TX_EMPTY_IRQ
));
155 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
),
156 3, qdev_get_gpio_in(DEVICE(&s
->plic
),
157 IBEX_UART_RX_OVERFLOW_IRQ
));
159 create_unimplemented_device("riscv.lowrisc.ibex.gpio",
160 memmap
[IBEX_GPIO
].base
, memmap
[IBEX_GPIO
].size
);
161 create_unimplemented_device("riscv.lowrisc.ibex.spi",
162 memmap
[IBEX_SPI
].base
, memmap
[IBEX_SPI
].size
);
163 create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
164 memmap
[IBEX_FLASH_CTRL
].base
, memmap
[IBEX_FLASH_CTRL
].size
);
165 create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
166 memmap
[IBEX_RV_TIMER
].base
, memmap
[IBEX_RV_TIMER
].size
);
167 create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
168 memmap
[IBEX_PWRMGR
].base
, memmap
[IBEX_PWRMGR
].size
);
169 create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
170 memmap
[IBEX_RSTMGR
].base
, memmap
[IBEX_RSTMGR
].size
);
171 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
172 memmap
[IBEX_CLKMGR
].base
, memmap
[IBEX_CLKMGR
].size
);
173 create_unimplemented_device("riscv.lowrisc.ibex.aes",
174 memmap
[IBEX_AES
].base
, memmap
[IBEX_AES
].size
);
175 create_unimplemented_device("riscv.lowrisc.ibex.hmac",
176 memmap
[IBEX_HMAC
].base
, memmap
[IBEX_HMAC
].size
);
177 create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
178 memmap
[IBEX_PINMUX
].base
, memmap
[IBEX_PINMUX
].size
);
179 create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
180 memmap
[IBEX_ALERT_HANDLER
].base
, memmap
[IBEX_ALERT_HANDLER
].size
);
181 create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
182 memmap
[IBEX_NMI_GEN
].base
, memmap
[IBEX_NMI_GEN
].size
);
183 create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
184 memmap
[IBEX_USBDEV
].base
, memmap
[IBEX_USBDEV
].size
);
185 create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
186 memmap
[IBEX_PADCTRL
].base
, memmap
[IBEX_PADCTRL
].size
);
189 static void riscv_lowrisc_ibex_soc_class_init(ObjectClass
*oc
, void *data
)
191 DeviceClass
*dc
= DEVICE_CLASS(oc
);
193 dc
->realize
= riscv_lowrisc_ibex_soc_realize
;
194 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
195 dc
->user_creatable
= false;
198 static const TypeInfo riscv_lowrisc_ibex_soc_type_info
= {
199 .name
= TYPE_RISCV_IBEX_SOC
,
200 .parent
= TYPE_DEVICE
,
201 .instance_size
= sizeof(LowRISCIbexSoCState
),
202 .instance_init
= riscv_lowrisc_ibex_soc_init
,
203 .class_init
= riscv_lowrisc_ibex_soc_class_init
,
206 static void riscv_lowrisc_ibex_soc_register_types(void)
208 type_register_static(&riscv_lowrisc_ibex_soc_type_info
);
211 type_init(riscv_lowrisc_ibex_soc_register_types
)