hw/riscv/riscv_htif.c

   1 /*
   2  * QEMU RISC-V Host Target Interface (HTIF) Emulation
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This provides HTIF device emulation for QEMU. At the moment this allows
   8  * for identical copies of bbl/linux to run on both spike and QEMU.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms and conditions of the GNU General Public License,
  12  * version 2 or later, as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "qapi/error.h"
  25 #include "qemu/log.h"
  26 #include "hw/sysbus.h"
  27 #include "hw/char/serial.h"
  28 #include "chardev/char.h"
  29 #include "chardev/char-fe.h"
  30 #include "hw/riscv/riscv_htif.h"
  31 #include "qemu/timer.h"
  32 #include "exec/address-spaces.h"
  33 #include "qemu/error-report.h"
  34
  35 #define RISCV_DEBUG_HTIF 0
  36 #define HTIF_DEBUG(fmt, ...)                                                   \
  37     do {                                                                       \
  38         if (RISCV_DEBUG_HTIF) {                                                \
  39             qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\
  40         }                                                                      \
  41     } while (0)
  42
  43 static uint64_t fromhost_addr, tohost_addr;
  44 static int address_symbol_set;
  45
  46 void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
  47                           uint64_t st_size)
  48 {
  49     if (strcmp("fromhost", st_name) == 0) {
  50         address_symbol_set |= 1;
  51         fromhost_addr = st_value;
  52         if (st_size != 8) {
  53             error_report("HTIF fromhost must be 8 bytes");
  54             exit(1);
  55         }
  56     } else if (strcmp("tohost", st_name) == 0) {
  57         address_symbol_set |= 2;
  58         tohost_addr = st_value;
  59         if (st_size != 8) {
  60             error_report("HTIF tohost must be 8 bytes");
  61             exit(1);
  62         }
  63     }
  64 }
  65
  66 /*
  67  * Called by the char dev to see if HTIF is ready to accept input.
  68  */
  69 static int htif_can_recv(void *opaque)
  70 {
  71     return 1;
  72 }
  73
  74 /*
  75  * Called by the char dev to supply input to HTIF console.
  76  * We assume that we will receive one character at a time.
  77  */
  78 static void htif_recv(void *opaque, const uint8_t *buf, int size)
  79 {
  80     HTIFState *htifstate = opaque;
  81
  82     if (size != 1) {
  83         return;
  84     }
  85
  86     /* TODO - we need to check whether mfromhost is zero which indicates
  87               the device is ready to receive. The current implementation
  88               will drop characters */
  89
  90     uint64_t val_written = htifstate->pending_read;
  91     uint64_t resp = 0x100 | *buf;
  92
  93     htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
  94 }
  95
  96 /*
  97  * Called by the char dev to supply special events to the HTIF console.
  98  * Not used for HTIF.
  99  */
 100 static void htif_event(void *opaque, int event)
 101 {
 102
 103 }
 104
 105 static int htif_be_change(void *opaque)
 106 {
 107     HTIFState *s = opaque;
 108
 109     qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
 110         htif_be_change, s, NULL, true);
 111
 112     return 0;
 113 }
 114
 115 static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
 116 {
 117     uint8_t device = val_written >> 56;
 118     uint8_t cmd = val_written >> 48;
 119     uint64_t payload = val_written & 0xFFFFFFFFFFFFULL;
 120     int resp = 0;
 121
 122     HTIF_DEBUG("mtohost write: device: %d cmd: %d what: %02" PRIx64
 123         " -payload: %016" PRIx64 "\n", device, cmd, payload & 0xFF, payload);
 124
 125     /*
 126      * Currently, there is a fixed mapping of devices:
 127      * 0: riscv-tests Pass/Fail Reporting Only (no syscall proxy)
 128      * 1: Console
 129      */
 130     if (unlikely(device == 0x0)) {
 131         /* frontend syscall handler, shutdown and exit code support */
 132         if (cmd == 0x0) {
 133             if (payload & 0x1) {
 134                 /* exit code */
 135                 int exit_code = payload >> 1;
 136                 exit(exit_code);
 137             } else {
 138                 qemu_log_mask(LOG_UNIMP, "pk syscall proxy not supported\n");
 139             }
 140         } else {
 141             qemu_log("HTIF device %d: unknown command\n", device);
 142         }
 143     } else if (likely(device == 0x1)) {
 144         /* HTIF Console */
 145         if (cmd == 0x0) {
 146             /* this should be a queue, but not yet implemented as such */
 147             htifstate->pending_read = val_written;
 148             htifstate->env->mtohost = 0; /* clear to indicate we read */
 149             return;
 150         } else if (cmd == 0x1) {
 151             qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1);
 152             resp = 0x100 | (uint8_t)payload;
 153         } else {
 154             qemu_log("HTIF device %d: unknown command\n", device);
 155         }
 156     } else {
 157         qemu_log("HTIF unknown device or command\n");
 158         HTIF_DEBUG("device: %d cmd: %d what: %02" PRIx64
 159             " payload: %016" PRIx64, device, cmd, payload & 0xFF, payload);
 160     }
 161     /*
 162      * - latest bbl does not set fromhost to 0 if there is a value in tohost
 163      * - with this code enabled, qemu hangs waiting for fromhost to go to 0
 164      * - with this code disabled, qemu works with bbl priv v1.9.1 and v1.10
 165      * - HTIF needs protocol documentation and a more complete state machine
 166
 167         while (!htifstate->fromhost_inprogress &&
 168             htifstate->env->mfromhost != 0x0) {
 169         }
 170     */
 171     htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
 172     htifstate->env->mtohost = 0; /* clear to indicate we read */
 173 }
 174
 175 #define TOHOST_OFFSET1 (htifstate->tohost_offset)
 176 #define TOHOST_OFFSET2 (htifstate->tohost_offset + 4)
 177 #define FROMHOST_OFFSET1 (htifstate->fromhost_offset)
 178 #define FROMHOST_OFFSET2 (htifstate->fromhost_offset + 4)
 179
 180 /* CPU wants to read an HTIF register */
 181 static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
 182 {
 183     HTIFState *htifstate = opaque;
 184     if (addr == TOHOST_OFFSET1) {
 185         return htifstate->env->mtohost & 0xFFFFFFFF;
 186     } else if (addr == TOHOST_OFFSET2) {
 187         return (htifstate->env->mtohost >> 32) & 0xFFFFFFFF;
 188     } else if (addr == FROMHOST_OFFSET1) {
 189         return htifstate->env->mfromhost & 0xFFFFFFFF;
 190     } else if (addr == FROMHOST_OFFSET2) {
 191         return (htifstate->env->mfromhost >> 32) & 0xFFFFFFFF;
 192     } else {
 193         qemu_log("Invalid htif read: address %016" PRIx64 "\n",
 194             (uint64_t)addr);
 195         return 0;
 196     }
 197 }
 198
 199 /* CPU wrote to an HTIF register */
 200 static void htif_mm_write(void *opaque, hwaddr addr,
 201                             uint64_t value, unsigned size)
 202 {
 203     HTIFState *htifstate = opaque;
 204     if (addr == TOHOST_OFFSET1) {
 205         if (htifstate->env->mtohost == 0x0) {
 206             htifstate->allow_tohost = 1;
 207             htifstate->env->mtohost = value & 0xFFFFFFFF;
 208         } else {
 209             htifstate->allow_tohost = 0;
 210         }
 211     } else if (addr == TOHOST_OFFSET2) {
 212         if (htifstate->allow_tohost) {
 213             htifstate->env->mtohost |= value << 32;
 214             htif_handle_tohost_write(htifstate, htifstate->env->mtohost);
 215         }
 216     } else if (addr == FROMHOST_OFFSET1) {
 217         htifstate->fromhost_inprogress = 1;
 218         htifstate->env->mfromhost = value & 0xFFFFFFFF;
 219     } else if (addr == FROMHOST_OFFSET2) {
 220         htifstate->env->mfromhost |= value << 32;
 221         htifstate->fromhost_inprogress = 0;
 222     } else {
 223         qemu_log("Invalid htif write: address %016" PRIx64 "\n",
 224             (uint64_t)addr);
 225     }
 226 }
 227
 228 static const MemoryRegionOps htif_mm_ops = {
 229     .read = htif_mm_read,
 230     .write = htif_mm_write,
 231 };
 232
 233 HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
 234     CPURISCVState *env, Chardev *chr)
 235 {
 236     uint64_t base = MIN(tohost_addr, fromhost_addr);
 237     uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
 238     uint64_t tohost_offset = tohost_addr - base;
 239     uint64_t fromhost_offset = fromhost_addr - base;
 240
 241     HTIFState *s = g_malloc0(sizeof(HTIFState));
 242     s->address_space = address_space;
 243     s->main_mem = main_mem;
 244     s->main_mem_ram_ptr = memory_region_get_ram_ptr(main_mem);
 245     s->env = env;
 246     s->tohost_offset = tohost_offset;
 247     s->fromhost_offset = fromhost_offset;
 248     s->pending_read = 0;
 249     s->allow_tohost = 0;
 250     s->fromhost_inprogress = 0;
 251     qemu_chr_fe_init(&s->chr, chr, &error_abort);
 252     qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
 253         htif_be_change, s, NULL, true);
 254     if (address_symbol_set == 3) {
 255         memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
 256                               TYPE_HTIF_UART, size);
 257         memory_region_add_subregion_overlap(address_space, base,
 258                                             &s->mmio, 1);
 259     }
 260
 261     return s;
 262 }