hw/riscv/riscv_htif.c

   1 /*
   2  * QEMU RISC-V Host Target Interface (HTIF) Emulation
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This provides HTIF device emulation for QEMU. At the moment this allows
   8  * for identical copies of bbl/linux to run on both spike and QEMU.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms and conditions of the GNU General Public License,
  12  * version 2 or later, as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "qapi/error.h"
  25 #include "qemu/log.h"
  26 #include "hw/sysbus.h"
  27 #include "hw/char/serial.h"
  28 #include "chardev/char.h"
  29 #include "chardev/char-fe.h"
  30 #include "hw/riscv/riscv_htif.h"
  31 #include "qemu/timer.h"
  32 #include "exec/address-spaces.h"
  33 #include "qemu/error-report.h"
  34
  35 #define RISCV_DEBUG_HTIF 0
  36 #define HTIF_DEBUG(fmt, ...)                                                   \
  37     do {                                                                       \
  38         if (RISCV_DEBUG_HTIF) {                                                \
  39             qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\
  40         }                                                                      \
  41     } while (0)
  42
  43 static uint64_t fromhost_addr, tohost_addr;
  44
  45 void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
  46     uint64_t st_size)
  47 {
  48     if (strcmp("fromhost", st_name) == 0) {
  49         fromhost_addr = st_value;
  50         if (st_size != 8) {
  51             error_report("HTIF fromhost must be 8 bytes");
  52             exit(1);
  53         }
  54     } else if (strcmp("tohost", st_name) == 0) {
  55         tohost_addr = st_value;
  56         if (st_size != 8) {
  57             error_report("HTIF tohost must be 8 bytes");
  58             exit(1);
  59         }
  60     }
  61 }
  62
  63 /*
  64  * Called by the char dev to see if HTIF is ready to accept input.
  65  */
  66 static int htif_can_recv(void *opaque)
  67 {
  68     return 1;
  69 }
  70
  71 /*
  72  * Called by the char dev to supply input to HTIF console.
  73  * We assume that we will receive one character at a time.
  74  */
  75 static void htif_recv(void *opaque, const uint8_t *buf, int size)
  76 {
  77     HTIFState *htifstate = opaque;
  78
  79     if (size != 1) {
  80         return;
  81     }
  82
  83     /* TODO - we need to check whether mfromhost is zero which indicates
  84               the device is ready to receive. The current implementation
  85               will drop characters */
  86
  87     uint64_t val_written = htifstate->pending_read;
  88     uint64_t resp = 0x100 | *buf;
  89
  90     htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
  91 }
  92
  93 /*
  94  * Called by the char dev to supply special events to the HTIF console.
  95  * Not used for HTIF.
  96  */
  97 static void htif_event(void *opaque, int event)
  98 {
  99
 100 }
 101
 102 static int htif_be_change(void *opaque)
 103 {
 104     HTIFState *s = opaque;
 105
 106     qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
 107         htif_be_change, s, NULL, true);
 108
 109     return 0;
 110 }
 111
 112 static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
 113 {
 114     uint8_t device = val_written >> 56;
 115     uint8_t cmd = val_written >> 48;
 116     uint64_t payload = val_written & 0xFFFFFFFFFFFFULL;
 117     int resp = 0;
 118
 119     HTIF_DEBUG("mtohost write: device: %d cmd: %d what: %02" PRIx64
 120         " -payload: %016" PRIx64 "\n", device, cmd, payload & 0xFF, payload);
 121
 122     /*
 123      * Currently, there is a fixed mapping of devices:
 124      * 0: riscv-tests Pass/Fail Reporting Only (no syscall proxy)
 125      * 1: Console
 126      */
 127     if (unlikely(device == 0x0)) {
 128         /* frontend syscall handler, shutdown and exit code support */
 129         if (cmd == 0x0) {
 130             if (payload & 0x1) {
 131                 /* exit code */
 132                 int exit_code = payload >> 1;
 133                 exit(exit_code);
 134             } else {
 135                 qemu_log_mask(LOG_UNIMP, "pk syscall proxy not supported\n");
 136             }
 137         } else {
 138             qemu_log("HTIF device %d: unknown command\n", device);
 139         }
 140     } else if (likely(device == 0x1)) {
 141         /* HTIF Console */
 142         if (cmd == 0x0) {
 143             /* this should be a queue, but not yet implemented as such */
 144             htifstate->pending_read = val_written;
 145             htifstate->env->mtohost = 0; /* clear to indicate we read */
 146             return;
 147         } else if (cmd == 0x1) {
 148             qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1);
 149             resp = 0x100 | (uint8_t)payload;
 150         } else {
 151             qemu_log("HTIF device %d: unknown command\n", device);
 152         }
 153     } else {
 154         qemu_log("HTIF unknown device or command\n");
 155         HTIF_DEBUG("device: %d cmd: %d what: %02" PRIx64
 156             " payload: %016" PRIx64, device, cmd, payload & 0xFF, payload);
 157     }
 158     /*
 159      * - latest bbl does not set fromhost to 0 if there is a value in tohost
 160      * - with this code enabled, qemu hangs waiting for fromhost to go to 0
 161      * - with this code disabled, qemu works with bbl priv v1.9.1 and v1.10
 162      * - HTIF needs protocol documentation and a more complete state machine
 163
 164         while (!htifstate->fromhost_inprogress &&
 165             htifstate->env->mfromhost != 0x0) {
 166         }
 167     */
 168     htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
 169     htifstate->env->mtohost = 0; /* clear to indicate we read */
 170 }
 171
 172 #define TOHOST_OFFSET1 (htifstate->tohost_offset)
 173 #define TOHOST_OFFSET2 (htifstate->tohost_offset + 4)
 174 #define FROMHOST_OFFSET1 (htifstate->fromhost_offset)
 175 #define FROMHOST_OFFSET2 (htifstate->fromhost_offset + 4)
 176
 177 /* CPU wants to read an HTIF register */
 178 static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
 179 {
 180     HTIFState *htifstate = opaque;
 181     if (addr == TOHOST_OFFSET1) {
 182         return htifstate->env->mtohost & 0xFFFFFFFF;
 183     } else if (addr == TOHOST_OFFSET2) {
 184         return (htifstate->env->mtohost >> 32) & 0xFFFFFFFF;
 185     } else if (addr == FROMHOST_OFFSET1) {
 186         return htifstate->env->mfromhost & 0xFFFFFFFF;
 187     } else if (addr == FROMHOST_OFFSET2) {
 188         return (htifstate->env->mfromhost >> 32) & 0xFFFFFFFF;
 189     } else {
 190         qemu_log("Invalid htif read: address %016" PRIx64 "\n",
 191             (uint64_t)addr);
 192         return 0;
 193     }
 194 }
 195
 196 /* CPU wrote to an HTIF register */
 197 static void htif_mm_write(void *opaque, hwaddr addr,
 198                             uint64_t value, unsigned size)
 199 {
 200     HTIFState *htifstate = opaque;
 201     if (addr == TOHOST_OFFSET1) {
 202         if (htifstate->env->mtohost == 0x0) {
 203             htifstate->allow_tohost = 1;
 204             htifstate->env->mtohost = value & 0xFFFFFFFF;
 205         } else {
 206             htifstate->allow_tohost = 0;
 207         }
 208     } else if (addr == TOHOST_OFFSET2) {
 209         if (htifstate->allow_tohost) {
 210             htifstate->env->mtohost |= value << 32;
 211             htif_handle_tohost_write(htifstate, htifstate->env->mtohost);
 212         }
 213     } else if (addr == FROMHOST_OFFSET1) {
 214         htifstate->fromhost_inprogress = 1;
 215         htifstate->env->mfromhost = value & 0xFFFFFFFF;
 216     } else if (addr == FROMHOST_OFFSET2) {
 217         htifstate->env->mfromhost |= value << 32;
 218         htifstate->fromhost_inprogress = 0;
 219     } else {
 220         qemu_log("Invalid htif write: address %016" PRIx64 "\n",
 221             (uint64_t)addr);
 222     }
 223 }
 224
 225 static const MemoryRegionOps htif_mm_ops = {
 226     .read = htif_mm_read,
 227     .write = htif_mm_write,
 228 };
 229
 230 HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
 231     CPURISCVState *env, Chardev *chr)
 232 {
 233     uint64_t base = MIN(tohost_addr, fromhost_addr);
 234     uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
 235     uint64_t tohost_offset = tohost_addr - base;
 236     uint64_t fromhost_offset = fromhost_addr - base;
 237
 238     HTIFState *s = g_malloc0(sizeof(HTIFState));
 239     s->address_space = address_space;
 240     s->main_mem = main_mem;
 241     s->main_mem_ram_ptr = memory_region_get_ram_ptr(main_mem);
 242     s->env = env;
 243     s->tohost_offset = tohost_offset;
 244     s->fromhost_offset = fromhost_offset;
 245     s->pending_read = 0;
 246     s->allow_tohost = 0;
 247     s->fromhost_inprogress = 0;
 248     qemu_chr_fe_init(&s->chr, chr, &error_abort);
 249     qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
 250         htif_be_change, s, NULL, true);
 251     if (base) {
 252         memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
 253                             TYPE_HTIF_UART, size);
 254         memory_region_add_subregion(address_space, base, &s->mmio);
 255     }
 256
 257     return s;
 258 }