2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
4 * Copyright (c) 2017 SiFive, Inc.
6 * Provides a board compatible with the SiFive Freedom E SDK:
9 * 1) CLINT (Core Level Interruptor)
10 * 2) PLIC (Platform Level Interrupt Controller)
11 * 3) PRCI (Power, Reset, Clock, Interrupt)
12 * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
13 * 5) Flash memory emulated as RAM
15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
16 * The OTP ROM and Flash boot code will be emulated in a future version.
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2 or later, as published by the Free Software Foundation.
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
31 #include "qemu/osdep.h"
33 #include "qemu/error-report.h"
34 #include "qapi/error.h"
35 #include "hw/boards.h"
36 #include "hw/loader.h"
37 #include "hw/sysbus.h"
38 #include "hw/char/serial.h"
39 #include "hw/misc/unimp.h"
40 #include "target/riscv/cpu.h"
41 #include "hw/riscv/riscv_hart.h"
42 #include "hw/riscv/sifive_plic.h"
43 #include "hw/riscv/sifive_clint.h"
44 #include "hw/riscv/sifive_uart.h"
45 #include "hw/riscv/sifive_e.h"
46 #include "hw/riscv/sifive_e_prci.h"
47 #include "hw/riscv/boot.h"
48 #include "chardev/char.h"
49 #include "sysemu/arch_init.h"
50 #include "sysemu/sysemu.h"
51 #include "exec/address-spaces.h"
53 static const struct MemmapEntry
{
56 } sifive_e_memmap
[] = {
57 [SIFIVE_E_DEBUG
] = { 0x0, 0x100 },
58 [SIFIVE_E_MROM
] = { 0x1000, 0x2000 },
59 [SIFIVE_E_OTP
] = { 0x20000, 0x2000 },
60 [SIFIVE_E_CLINT
] = { 0x2000000, 0x10000 },
61 [SIFIVE_E_PLIC
] = { 0xc000000, 0x4000000 },
62 [SIFIVE_E_AON
] = { 0x10000000, 0x8000 },
63 [SIFIVE_E_PRCI
] = { 0x10008000, 0x8000 },
64 [SIFIVE_E_OTP_CTRL
] = { 0x10010000, 0x1000 },
65 [SIFIVE_E_GPIO0
] = { 0x10012000, 0x1000 },
66 [SIFIVE_E_UART0
] = { 0x10013000, 0x1000 },
67 [SIFIVE_E_QSPI0
] = { 0x10014000, 0x1000 },
68 [SIFIVE_E_PWM0
] = { 0x10015000, 0x1000 },
69 [SIFIVE_E_UART1
] = { 0x10023000, 0x1000 },
70 [SIFIVE_E_QSPI1
] = { 0x10024000, 0x1000 },
71 [SIFIVE_E_PWM1
] = { 0x10025000, 0x1000 },
72 [SIFIVE_E_QSPI2
] = { 0x10034000, 0x1000 },
73 [SIFIVE_E_PWM2
] = { 0x10035000, 0x1000 },
74 [SIFIVE_E_XIP
] = { 0x20000000, 0x20000000 },
75 [SIFIVE_E_DTIM
] = { 0x80000000, 0x4000 }
78 static void riscv_sifive_e_init(MachineState
*machine
)
80 const struct MemmapEntry
*memmap
= sifive_e_memmap
;
82 SiFiveEState
*s
= RISCV_E_MACHINE(machine
);
83 MemoryRegion
*sys_mem
= get_system_memory();
84 MemoryRegion
*main_mem
= g_new(MemoryRegion
, 1);
88 object_initialize_child(OBJECT(machine
), "soc", &s
->soc
, TYPE_RISCV_E_SOC
);
89 object_property_set_bool(OBJECT(&s
->soc
), true, "realized",
92 /* Data Tightly Integrated Memory */
93 memory_region_init_ram(main_mem
, NULL
, "riscv.sifive.e.ram",
94 memmap
[SIFIVE_E_DTIM
].size
, &error_fatal
);
95 memory_region_add_subregion(sys_mem
,
96 memmap
[SIFIVE_E_DTIM
].base
, main_mem
);
98 /* Mask ROM reset vector */
99 uint32_t reset_vec
[2] = {
100 0x204002b7, /* 0x1000: lui t0,0x20400 */
101 0x00028067, /* 0x1004: jr t0 */
104 /* copy in the reset vector in little_endian byte order */
105 for (i
= 0; i
< sizeof(reset_vec
) >> 2; i
++) {
106 reset_vec
[i
] = cpu_to_le32(reset_vec
[i
]);
108 rom_add_blob_fixed_as("mrom.reset", reset_vec
, sizeof(reset_vec
),
109 memmap
[SIFIVE_E_MROM
].base
, &address_space_memory
);
111 if (machine
->kernel_filename
) {
112 riscv_load_kernel(machine
->kernel_filename
, NULL
);
116 static void sifive_e_machine_instance_init(Object
*obj
)
120 static void sifive_e_machine_class_init(ObjectClass
*oc
, void *data
)
122 MachineClass
*mc
= MACHINE_CLASS(oc
);
124 mc
->desc
= "RISC-V Board compatible with SiFive E SDK";
125 mc
->init
= riscv_sifive_e_init
;
127 mc
->default_cpu_type
= SIFIVE_E_CPU
;
130 static const TypeInfo sifive_e_machine_typeinfo
= {
131 .name
= MACHINE_TYPE_NAME("sifive_e"),
132 .parent
= TYPE_MACHINE
,
133 .class_init
= sifive_e_machine_class_init
,
134 .instance_init
= sifive_e_machine_instance_init
,
135 .instance_size
= sizeof(SiFiveEState
),
138 static void sifive_e_machine_init_register_types(void)
140 type_register_static(&sifive_e_machine_typeinfo
);
143 type_init(sifive_e_machine_init_register_types
)
145 static void riscv_sifive_e_soc_init(Object
*obj
)
147 MachineState
*ms
= MACHINE(qdev_get_machine());
148 SiFiveESoCState
*s
= RISCV_E_SOC(obj
);
150 object_initialize_child(obj
, "cpus", &s
->cpus
, TYPE_RISCV_HART_ARRAY
);
151 object_property_set_int(OBJECT(&s
->cpus
), ms
->smp
.cpus
, "num-harts",
153 object_initialize_child(obj
, "riscv.sifive.e.gpio0", &s
->gpio
,
157 static void riscv_sifive_e_soc_realize(DeviceState
*dev
, Error
**errp
)
159 MachineState
*ms
= MACHINE(qdev_get_machine());
160 const struct MemmapEntry
*memmap
= sifive_e_memmap
;
163 SiFiveESoCState
*s
= RISCV_E_SOC(dev
);
164 MemoryRegion
*sys_mem
= get_system_memory();
166 object_property_set_str(OBJECT(&s
->cpus
), ms
->cpu_type
, "cpu-type",
168 sysbus_realize(SYS_BUS_DEVICE(&s
->cpus
), &error_abort
);
171 memory_region_init_rom(&s
->mask_rom
, OBJECT(dev
), "riscv.sifive.e.mrom",
172 memmap
[SIFIVE_E_MROM
].size
, &error_fatal
);
173 memory_region_add_subregion(sys_mem
,
174 memmap
[SIFIVE_E_MROM
].base
, &s
->mask_rom
);
177 s
->plic
= sifive_plic_create(memmap
[SIFIVE_E_PLIC
].base
,
178 (char *)SIFIVE_E_PLIC_HART_CONFIG
,
179 SIFIVE_E_PLIC_NUM_SOURCES
,
180 SIFIVE_E_PLIC_NUM_PRIORITIES
,
181 SIFIVE_E_PLIC_PRIORITY_BASE
,
182 SIFIVE_E_PLIC_PENDING_BASE
,
183 SIFIVE_E_PLIC_ENABLE_BASE
,
184 SIFIVE_E_PLIC_ENABLE_STRIDE
,
185 SIFIVE_E_PLIC_CONTEXT_BASE
,
186 SIFIVE_E_PLIC_CONTEXT_STRIDE
,
187 memmap
[SIFIVE_E_PLIC
].size
);
188 sifive_clint_create(memmap
[SIFIVE_E_CLINT
].base
,
189 memmap
[SIFIVE_E_CLINT
].size
, ms
->smp
.cpus
,
190 SIFIVE_SIP_BASE
, SIFIVE_TIMECMP_BASE
, SIFIVE_TIME_BASE
, false);
191 create_unimplemented_device("riscv.sifive.e.aon",
192 memmap
[SIFIVE_E_AON
].base
, memmap
[SIFIVE_E_AON
].size
);
193 sifive_e_prci_create(memmap
[SIFIVE_E_PRCI
].base
);
197 sysbus_realize(SYS_BUS_DEVICE(&s
->gpio
), &err
);
199 error_propagate(errp
, err
);
203 /* Map GPIO registers */
204 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
), 0, memmap
[SIFIVE_E_GPIO0
].base
);
206 /* Pass all GPIOs to the SOC layer so they are available to the board */
207 qdev_pass_gpios(DEVICE(&s
->gpio
), dev
, NULL
);
209 /* Connect GPIO interrupts to the PLIC */
210 for (int i
= 0; i
< 32; i
++) {
211 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
), i
,
212 qdev_get_gpio_in(DEVICE(s
->plic
),
213 SIFIVE_E_GPIO0_IRQ0
+ i
));
216 sifive_uart_create(sys_mem
, memmap
[SIFIVE_E_UART0
].base
,
217 serial_hd(0), qdev_get_gpio_in(DEVICE(s
->plic
), SIFIVE_E_UART0_IRQ
));
218 create_unimplemented_device("riscv.sifive.e.qspi0",
219 memmap
[SIFIVE_E_QSPI0
].base
, memmap
[SIFIVE_E_QSPI0
].size
);
220 create_unimplemented_device("riscv.sifive.e.pwm0",
221 memmap
[SIFIVE_E_PWM0
].base
, memmap
[SIFIVE_E_PWM0
].size
);
222 sifive_uart_create(sys_mem
, memmap
[SIFIVE_E_UART1
].base
,
223 serial_hd(1), qdev_get_gpio_in(DEVICE(s
->plic
), SIFIVE_E_UART1_IRQ
));
224 create_unimplemented_device("riscv.sifive.e.qspi1",
225 memmap
[SIFIVE_E_QSPI1
].base
, memmap
[SIFIVE_E_QSPI1
].size
);
226 create_unimplemented_device("riscv.sifive.e.pwm1",
227 memmap
[SIFIVE_E_PWM1
].base
, memmap
[SIFIVE_E_PWM1
].size
);
228 create_unimplemented_device("riscv.sifive.e.qspi2",
229 memmap
[SIFIVE_E_QSPI2
].base
, memmap
[SIFIVE_E_QSPI2
].size
);
230 create_unimplemented_device("riscv.sifive.e.pwm2",
231 memmap
[SIFIVE_E_PWM2
].base
, memmap
[SIFIVE_E_PWM2
].size
);
234 memory_region_init_rom(&s
->xip_mem
, OBJECT(dev
), "riscv.sifive.e.xip",
235 memmap
[SIFIVE_E_XIP
].size
, &error_fatal
);
236 memory_region_add_subregion(sys_mem
, memmap
[SIFIVE_E_XIP
].base
,
240 static void riscv_sifive_e_soc_class_init(ObjectClass
*oc
, void *data
)
242 DeviceClass
*dc
= DEVICE_CLASS(oc
);
244 dc
->realize
= riscv_sifive_e_soc_realize
;
245 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
246 dc
->user_creatable
= false;
249 static const TypeInfo riscv_sifive_e_soc_type_info
= {
250 .name
= TYPE_RISCV_E_SOC
,
251 .parent
= TYPE_DEVICE
,
252 .instance_size
= sizeof(SiFiveESoCState
),
253 .instance_init
= riscv_sifive_e_soc_init
,
254 .class_init
= riscv_sifive_e_soc_class_init
,
257 static void riscv_sifive_e_soc_register_types(void)
259 type_register_static(&riscv_sifive_e_soc_type_info
);
262 type_init(riscv_sifive_e_soc_register_types
)