hw/riscv/sifive_plic.c

   1 /*
   2  * SiFive PLIC (Platform Level Interrupt Controller)
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * This provides a parameterizable interrupt controller based on SiFive's PLIC.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/log.h"
  23 #include "qemu/error-report.h"
  24 #include "hw/sysbus.h"
  25 #include "hw/pci/msi.h"
  26 #include "target/riscv/cpu.h"
  27 #include "sysemu/sysemu.h"
  28 #include "hw/riscv/sifive_plic.h"
  29
  30 #define RISCV_DEBUG_PLIC 0
  31
  32 static PLICMode char_to_mode(char c)
  33 {
  34     switch (c) {
  35     case 'U': return PLICMode_U;
  36     case 'S': return PLICMode_S;
  37     case 'H': return PLICMode_H;
  38     case 'M': return PLICMode_M;
  39     default:
  40         error_report("plic: invalid mode '%c'", c);
  41         exit(1);
  42     }
  43 }
  44
  45 static char mode_to_char(PLICMode m)
  46 {
  47     switch (m) {
  48     case PLICMode_U: return 'U';
  49     case PLICMode_S: return 'S';
  50     case PLICMode_H: return 'H';
  51     case PLICMode_M: return 'M';
  52     default: return '?';
  53     }
  54 }
  55
  56 static void sifive_plic_print_state(SiFivePLICState *plic)
  57 {
  58     int i;
  59     int addrid;
  60
  61     /* pending */
  62     qemu_log("pending       : ");
  63     for (i = plic->bitfield_words - 1; i >= 0; i--) {
  64         qemu_log("%08x", plic->pending[i]);
  65     }
  66     qemu_log("\n");
  67
  68     /* pending */
  69     qemu_log("claimed       : ");
  70     for (i = plic->bitfield_words - 1; i >= 0; i--) {
  71         qemu_log("%08x", plic->claimed[i]);
  72     }
  73     qemu_log("\n");
  74
  75     for (addrid = 0; addrid < plic->num_addrs; addrid++) {
  76         qemu_log("hart%d-%c enable: ",
  77             plic->addr_config[addrid].hartid,
  78             mode_to_char(plic->addr_config[addrid].mode));
  79         for (i = plic->bitfield_words - 1; i >= 0; i--) {
  80             qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + i]);
  81         }
  82         qemu_log("\n");
  83     }
  84 }
  85
  86 static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
  87 {
  88     uint32_t old, new, cmp = atomic_read(a);
  89
  90     do {
  91         old = cmp;
  92         new = (old & ~mask) | (value & mask);
  93         cmp = atomic_cmpxchg(a, old, new);
  94     } while (old != cmp);
  95
  96     return old;
  97 }
  98
  99 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level)
 100 {
 101     atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level);
 102 }
 103
 104 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
 105 {
 106     atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
 107 }
 108
 109 static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid)
 110 {
 111     int i, j;
 112     for (i = 0; i < plic->bitfield_words; i++) {
 113         uint32_t pending_enabled_not_claimed =
 114             (plic->pending[i] & ~plic->claimed[i]) &
 115             plic->enable[addrid * plic->bitfield_words + i];
 116         if (!pending_enabled_not_claimed) {
 117             continue;
 118         }
 119         for (j = 0; j < 32; j++) {
 120             int irq = (i << 5) + j;
 121             uint32_t prio = plic->source_priority[irq];
 122             int enabled = pending_enabled_not_claimed & (1 << j);
 123             if (enabled && prio > plic->target_priority[addrid]) {
 124                 return 1;
 125             }
 126         }
 127     }
 128     return 0;
 129 }
 130
 131 static void sifive_plic_update(SiFivePLICState *plic)
 132 {
 133     int addrid;
 134
 135     /* raise irq on harts where this irq is enabled */
 136     for (addrid = 0; addrid < plic->num_addrs; addrid++) {
 137         uint32_t hartid = plic->addr_config[addrid].hartid;
 138         PLICMode mode = plic->addr_config[addrid].mode;
 139         CPUState *cpu = qemu_get_cpu(hartid);
 140         CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
 141         if (!env) {
 142             continue;
 143         }
 144         int level = sifive_plic_irqs_pending(plic, addrid);
 145         switch (mode) {
 146         case PLICMode_M:
 147             riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
 148             break;
 149         case PLICMode_S:
 150             riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
 151             break;
 152         default:
 153             break;
 154         }
 155     }
 156
 157     if (RISCV_DEBUG_PLIC) {
 158         sifive_plic_print_state(plic);
 159     }
 160 }
 161
 162 void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq)
 163 {
 164     sifive_plic_set_pending(plic, irq, true);
 165     sifive_plic_update(plic);
 166 }
 167
 168 void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq)
 169 {
 170     sifive_plic_set_pending(plic, irq, false);
 171     sifive_plic_update(plic);
 172 }
 173
 174 static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
 175 {
 176     int i, j;
 177     for (i = 0; i < plic->bitfield_words; i++) {
 178         uint32_t pending_enabled_not_claimed =
 179             (plic->pending[i] & ~plic->claimed[i]) &
 180             plic->enable[addrid * plic->bitfield_words + i];
 181         if (!pending_enabled_not_claimed) {
 182             continue;
 183         }
 184         for (j = 0; j < 32; j++) {
 185             int irq = (i << 5) + j;
 186             uint32_t prio = plic->source_priority[irq];
 187             int enabled = pending_enabled_not_claimed & (1 << j);
 188             if (enabled && prio > plic->target_priority[addrid]) {
 189                 sifive_plic_set_pending(plic, irq, false);
 190                 sifive_plic_set_claimed(plic, irq, true);
 191                 return irq;
 192             }
 193         }
 194     }
 195     return 0;
 196 }
 197
 198 static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
 199 {
 200     SiFivePLICState *plic = opaque;
 201
 202     /* writes must be 4 byte words */
 203     if ((addr & 0x3) != 0) {
 204         goto err;
 205     }
 206
 207     if (addr >= plic->priority_base && /* 4 bytes per source */
 208         addr < plic->priority_base + (plic->num_sources << 2))
 209     {
 210         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 211         if (RISCV_DEBUG_PLIC) {
 212             qemu_log("plic: read priority: irq=%d priority=%d\n",
 213                 irq, plic->source_priority[irq]);
 214         }
 215         return plic->source_priority[irq];
 216     } else if (addr >= plic->pending_base && /* 1 bit per source */
 217                addr < plic->pending_base + (plic->num_sources >> 3))
 218     {
 219         uint32_t word = (addr - plic->pending_base) >> 2;
 220         if (RISCV_DEBUG_PLIC) {
 221             qemu_log("plic: read pending: word=%d value=%d\n",
 222                 word, plic->pending[word]);
 223         }
 224         return plic->pending[word];
 225     } else if (addr >= plic->enable_base && /* 1 bit per source */
 226              addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
 227     {
 228         uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
 229         uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
 230         if (wordid < plic->bitfield_words) {
 231             if (RISCV_DEBUG_PLIC) {
 232                 qemu_log("plic: read enable: hart%d-%c word=%d value=%x\n",
 233                     plic->addr_config[addrid].hartid,
 234                     mode_to_char(plic->addr_config[addrid].mode), wordid,
 235                     plic->enable[addrid * plic->bitfield_words + wordid]);
 236             }
 237             return plic->enable[addrid * plic->bitfield_words + wordid];
 238         }
 239     } else if (addr >= plic->context_base && /* 1 bit per source */
 240              addr < plic->context_base + plic->num_addrs * plic->context_stride)
 241     {
 242         uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
 243         uint32_t contextid = (addr & (plic->context_stride - 1));
 244         if (contextid == 0) {
 245             if (RISCV_DEBUG_PLIC) {
 246                 qemu_log("plic: read priority: hart%d-%c priority=%x\n",
 247                     plic->addr_config[addrid].hartid,
 248                     mode_to_char(plic->addr_config[addrid].mode),
 249                     plic->target_priority[addrid]);
 250             }
 251             return plic->target_priority[addrid];
 252         } else if (contextid == 4) {
 253             uint32_t value = sifive_plic_claim(plic, addrid);
 254             if (RISCV_DEBUG_PLIC) {
 255                 qemu_log("plic: read claim: hart%d-%c irq=%x\n",
 256                     plic->addr_config[addrid].hartid,
 257                     mode_to_char(plic->addr_config[addrid].mode),
 258                     value);
 259                 sifive_plic_print_state(plic);
 260             }
 261             return value;
 262         }
 263     }
 264
 265 err:
 266     qemu_log_mask(LOG_GUEST_ERROR,
 267                   "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
 268                   __func__, addr);
 269     return 0;
 270 }
 271
 272 static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
 273         unsigned size)
 274 {
 275     SiFivePLICState *plic = opaque;
 276
 277     /* writes must be 4 byte words */
 278     if ((addr & 0x3) != 0) {
 279         goto err;
 280     }
 281
 282     if (addr >= plic->priority_base && /* 4 bytes per source */
 283         addr < plic->priority_base + (plic->num_sources << 2))
 284     {
 285         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 286         plic->source_priority[irq] = value & 7;
 287         if (RISCV_DEBUG_PLIC) {
 288             qemu_log("plic: write priority: irq=%d priority=%d\n",
 289                 irq, plic->source_priority[irq]);
 290         }
 291         return;
 292     } else if (addr >= plic->pending_base && /* 1 bit per source */
 293                addr < plic->pending_base + (plic->num_sources >> 3))
 294     {
 295         qemu_log_mask(LOG_GUEST_ERROR,
 296                       "%s: invalid pending write: 0x%" HWADDR_PRIx "",
 297                       __func__, addr);
 298         return;
 299     } else if (addr >= plic->enable_base && /* 1 bit per source */
 300         addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
 301     {
 302         uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
 303         uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
 304         if (wordid < plic->bitfield_words) {
 305             plic->enable[addrid * plic->bitfield_words + wordid] = value;
 306             if (RISCV_DEBUG_PLIC) {
 307                 qemu_log("plic: write enable: hart%d-%c word=%d value=%x\n",
 308                     plic->addr_config[addrid].hartid,
 309                     mode_to_char(plic->addr_config[addrid].mode), wordid,
 310                     plic->enable[addrid * plic->bitfield_words + wordid]);
 311             }
 312             return;
 313         }
 314     } else if (addr >= plic->context_base && /* 4 bytes per reg */
 315         addr < plic->context_base + plic->num_addrs * plic->context_stride)
 316     {
 317         uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
 318         uint32_t contextid = (addr & (plic->context_stride - 1));
 319         if (contextid == 0) {
 320             if (RISCV_DEBUG_PLIC) {
 321                 qemu_log("plic: write priority: hart%d-%c priority=%x\n",
 322                     plic->addr_config[addrid].hartid,
 323                     mode_to_char(plic->addr_config[addrid].mode),
 324                     plic->target_priority[addrid]);
 325             }
 326             if (value <= plic->num_priorities) {
 327                 plic->target_priority[addrid] = value;
 328                 sifive_plic_update(plic);
 329             }
 330             return;
 331         } else if (contextid == 4) {
 332             if (RISCV_DEBUG_PLIC) {
 333                 qemu_log("plic: write claim: hart%d-%c irq=%x\n",
 334                     plic->addr_config[addrid].hartid,
 335                     mode_to_char(plic->addr_config[addrid].mode),
 336                     (uint32_t)value);
 337             }
 338             if (value < plic->num_sources) {
 339                 sifive_plic_set_claimed(plic, value, false);
 340                 sifive_plic_update(plic);
 341             }
 342             return;
 343         }
 344     }
 345
 346 err:
 347     qemu_log_mask(LOG_GUEST_ERROR,
 348                   "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
 349                   __func__, addr);
 350 }
 351
 352 static const MemoryRegionOps sifive_plic_ops = {
 353     .read = sifive_plic_read,
 354     .write = sifive_plic_write,
 355     .endianness = DEVICE_LITTLE_ENDIAN,
 356     .valid = {
 357         .min_access_size = 4,
 358         .max_access_size = 4
 359     }
 360 };
 361
 362 static Property sifive_plic_properties[] = {
 363     DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
 364     DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
 365     DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
 366     DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
 367     DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
 368     DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
 369     DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
 370     DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
 371     DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
 372     DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
 373     DEFINE_PROP_END_OF_LIST(),
 374 };
 375
 376 /*
 377  * parse PLIC hart/mode address offset config
 378  *
 379  * "M"              1 hart with M mode
 380  * "MS,MS"          2 harts, 0-1 with M and S mode
 381  * "M,MS,MS,MS,MS"  5 harts, 0 with M mode, 1-5 with M and S mode
 382  */
 383 static void parse_hart_config(SiFivePLICState *plic)
 384 {
 385     int addrid, hartid, modes;
 386     const char *p;
 387     char c;
 388
 389     /* count and validate hart/mode combinations */
 390     addrid = 0, hartid = 0, modes = 0;
 391     p = plic->hart_config;
 392     while ((c = *p++)) {
 393         if (c == ',') {
 394             addrid += ctpop8(modes);
 395             modes = 0;
 396             hartid++;
 397         } else {
 398             int m = 1 << char_to_mode(c);
 399             if (modes == (modes | m)) {
 400                 error_report("plic: duplicate mode '%c' in config: %s",
 401                              c, plic->hart_config);
 402                 exit(1);
 403             }
 404             modes |= m;
 405         }
 406     }
 407     if (modes) {
 408         addrid += ctpop8(modes);
 409     }
 410     hartid++;
 411
 412     /* store hart/mode combinations */
 413     plic->num_addrs = addrid;
 414     plic->addr_config = g_new(PLICAddr, plic->num_addrs);
 415     addrid = 0, hartid = 0;
 416     p = plic->hart_config;
 417     while ((c = *p++)) {
 418         if (c == ',') {
 419             hartid++;
 420         } else {
 421             plic->addr_config[addrid].addrid = addrid;
 422             plic->addr_config[addrid].hartid = hartid;
 423             plic->addr_config[addrid].mode = char_to_mode(c);
 424             addrid++;
 425         }
 426     }
 427 }
 428
 429 static void sifive_plic_irq_request(void *opaque, int irq, int level)
 430 {
 431     SiFivePLICState *plic = opaque;
 432     if (RISCV_DEBUG_PLIC) {
 433         qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
 434     }
 435     sifive_plic_set_pending(plic, irq, level > 0);
 436     sifive_plic_update(plic);
 437 }
 438
 439 static void sifive_plic_realize(DeviceState *dev, Error **errp)
 440 {
 441     SiFivePLICState *plic = SIFIVE_PLIC(dev);
 442     int i;
 443
 444     memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
 445                           TYPE_SIFIVE_PLIC, plic->aperture_size);
 446     parse_hart_config(plic);
 447     plic->bitfield_words = (plic->num_sources + 31) >> 5;
 448     plic->source_priority = g_new0(uint32_t, plic->num_sources);
 449     plic->target_priority = g_new(uint32_t, plic->num_addrs);
 450     plic->pending = g_new0(uint32_t, plic->bitfield_words);
 451     plic->claimed = g_new0(uint32_t, plic->bitfield_words);
 452     plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
 453     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
 454     qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
 455
 456     /* We can't allow the supervisor to control SEIP as this would allow the
 457      * supervisor to clear a pending external interrupt which will result in
 458      * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
 459      * hardware controlled when a PLIC is attached.
 460      */
 461     for (i = 0; i < smp_cpus; i++) {
 462         RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
 463         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
 464             error_report("SEIP already claimed");
 465             exit(1);
 466         }
 467     }
 468
 469     msi_nonbroken = true;
 470 }
 471
 472 static void sifive_plic_class_init(ObjectClass *klass, void *data)
 473 {
 474     DeviceClass *dc = DEVICE_CLASS(klass);
 475
 476     dc->props = sifive_plic_properties;
 477     dc->realize = sifive_plic_realize;
 478 }
 479
 480 static const TypeInfo sifive_plic_info = {
 481     .name          = TYPE_SIFIVE_PLIC,
 482     .parent        = TYPE_SYS_BUS_DEVICE,
 483     .instance_size = sizeof(SiFivePLICState),
 484     .class_init    = sifive_plic_class_init,
 485 };
 486
 487 static void sifive_plic_register_types(void)
 488 {
 489     type_register_static(&sifive_plic_info);
 490 }
 491
 492 type_init(sifive_plic_register_types)
 493
 494 /*
 495  * Create PLIC device.
 496  */
 497 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
 498     uint32_t num_sources, uint32_t num_priorities,
 499     uint32_t priority_base, uint32_t pending_base,
 500     uint32_t enable_base, uint32_t enable_stride,
 501     uint32_t context_base, uint32_t context_stride,
 502     uint32_t aperture_size)
 503 {
 504     DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PLIC);
 505     assert(enable_stride == (enable_stride & -enable_stride));
 506     assert(context_stride == (context_stride & -context_stride));
 507     qdev_prop_set_string(dev, "hart-config", hart_config);
 508     qdev_prop_set_uint32(dev, "num-sources", num_sources);
 509     qdev_prop_set_uint32(dev, "num-priorities", num_priorities);
 510     qdev_prop_set_uint32(dev, "priority-base", priority_base);
 511     qdev_prop_set_uint32(dev, "pending-base", pending_base);
 512     qdev_prop_set_uint32(dev, "enable-base", enable_base);
 513     qdev_prop_set_uint32(dev, "enable-stride", enable_stride);
 514     qdev_prop_set_uint32(dev, "context-base", context_base);
 515     qdev_prop_set_uint32(dev, "context-stride", context_stride);
 516     qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
 517     qdev_init_nofail(dev);
 518     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 519     return dev;
 520 }