2 * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt)
4 * Copyright (c) 2017 SiFive, Inc.
6 * Simple model of the PRCI to emulate register reads made by the SDK BSP
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "qemu/module.h"
24 #include "target/riscv/cpu.h"
25 #include "hw/riscv/sifive_prci.h"
27 static uint64_t sifive_prci_read(void *opaque
, hwaddr addr
, unsigned int size
)
29 SiFivePRCIState
*s
= opaque
;
31 case SIFIVE_PRCI_HFROSCCFG
:
33 case SIFIVE_PRCI_HFXOSCCFG
:
35 case SIFIVE_PRCI_PLLCFG
:
37 case SIFIVE_PRCI_PLLOUTDIV
:
40 hw_error("%s: read: addr=0x%x\n", __func__
, (int)addr
);
44 static void sifive_prci_write(void *opaque
, hwaddr addr
,
45 uint64_t val64
, unsigned int size
)
47 SiFivePRCIState
*s
= opaque
;
49 case SIFIVE_PRCI_HFROSCCFG
:
50 s
->hfrosccfg
= (uint32_t) val64
;
52 s
->hfrosccfg
|= SIFIVE_PRCI_HFROSCCFG_RDY
;
54 case SIFIVE_PRCI_HFXOSCCFG
:
55 s
->hfxosccfg
= (uint32_t) val64
;
57 s
->hfxosccfg
|= SIFIVE_PRCI_HFXOSCCFG_RDY
;
59 case SIFIVE_PRCI_PLLCFG
:
60 s
->pllcfg
= (uint32_t) val64
;
61 /* PLL stays locked */
62 s
->pllcfg
|= SIFIVE_PRCI_PLLCFG_LOCK
;
64 case SIFIVE_PRCI_PLLOUTDIV
:
65 s
->plloutdiv
= (uint32_t) val64
;
68 hw_error("%s: bad write: addr=0x%x v=0x%x\n",
69 __func__
, (int)addr
, (int)val64
);
73 static const MemoryRegionOps sifive_prci_ops
= {
74 .read
= sifive_prci_read
,
75 .write
= sifive_prci_write
,
76 .endianness
= DEVICE_NATIVE_ENDIAN
,
83 static void sifive_prci_init(Object
*obj
)
85 SiFivePRCIState
*s
= SIFIVE_PRCI(obj
);
87 memory_region_init_io(&s
->mmio
, obj
, &sifive_prci_ops
, s
,
88 TYPE_SIFIVE_PRCI
, 0x8000);
89 sysbus_init_mmio(SYS_BUS_DEVICE(obj
), &s
->mmio
);
91 s
->hfrosccfg
= (SIFIVE_PRCI_HFROSCCFG_RDY
| SIFIVE_PRCI_HFROSCCFG_EN
);
92 s
->hfxosccfg
= (SIFIVE_PRCI_HFROSCCFG_RDY
| SIFIVE_PRCI_HFROSCCFG_EN
);
93 s
->pllcfg
= (SIFIVE_PRCI_PLLCFG_REFSEL
| SIFIVE_PRCI_PLLCFG_BYPASS
|
94 SIFIVE_PRCI_PLLCFG_LOCK
);
95 s
->plloutdiv
= SIFIVE_PRCI_PLLOUTDIV_DIV1
;
99 static const TypeInfo sifive_prci_info
= {
100 .name
= TYPE_SIFIVE_PRCI
,
101 .parent
= TYPE_SYS_BUS_DEVICE
,
102 .instance_size
= sizeof(SiFivePRCIState
),
103 .instance_init
= sifive_prci_init
,
106 static void sifive_prci_register_types(void)
108 type_register_static(&sifive_prci_info
);
111 type_init(sifive_prci_register_types
)
115 * Create PRCI device.
117 DeviceState
*sifive_prci_create(hwaddr addr
)
119 DeviceState
*dev
= qdev_create(NULL
, TYPE_SIFIVE_PRCI
);
120 qdev_init_nofail(dev
);
121 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, addr
);