hw/riscv/sifive_u.c

   1 /*
   2  * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017 SiFive, Inc.
   6  * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
   7  *
   8  * Provides a board compatible with the SiFive Freedom U SDK:
   9  *
  10  * 0) UART
  11  * 1) CLINT (Core Level Interruptor)
  12  * 2) PLIC (Platform Level Interrupt Controller)
  13  * 3) PRCI (Power, Reset, Clock, Interrupt)
  14  * 4) OTP (One-Time Programmable) memory with stored serial number
  15  * 5) GEM (Gigabit Ethernet Controller) and management block
  16  *
  17  * This board currently generates devicetree dynamically that indicates at least
  18  * two harts and up to five harts.
  19  *
  20  * This program is free software; you can redistribute it and/or modify it
  21  * under the terms and conditions of the GNU General Public License,
  22  * version 2 or later, as published by the Free Software Foundation.
  23  *
  24  * This program is distributed in the hope it will be useful, but WITHOUT
  25  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  26  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  27  * more details.
  28  *
  29  * You should have received a copy of the GNU General Public License along with
  30  * this program.  If not, see <http://www.gnu.org/licenses/>.
  31  */
  32
  33 #include "qemu/osdep.h"
  34 #include "qemu/log.h"
  35 #include "qemu/error-report.h"
  36 #include "qapi/error.h"
  37 #include "hw/boards.h"
  38 #include "hw/loader.h"
  39 #include "hw/sysbus.h"
  40 #include "hw/char/serial.h"
  41 #include "hw/cpu/cluster.h"
  42 #include "hw/misc/unimp.h"
  43 #include "target/riscv/cpu.h"
  44 #include "hw/riscv/riscv_hart.h"
  45 #include "hw/riscv/sifive_plic.h"
  46 #include "hw/riscv/sifive_clint.h"
  47 #include "hw/riscv/sifive_uart.h"
  48 #include "hw/riscv/sifive_u.h"
  49 #include "hw/riscv/boot.h"
  50 #include "chardev/char.h"
  51 #include "net/eth.h"
  52 #include "sysemu/arch_init.h"
  53 #include "sysemu/device_tree.h"
  54 #include "sysemu/sysemu.h"
  55 #include "exec/address-spaces.h"
  56
  57 #include <libfdt.h>
  58
  59 #define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin"
  60
  61 static const struct MemmapEntry {
  62     hwaddr base;
  63     hwaddr size;
  64 } sifive_u_memmap[] = {
  65     [SIFIVE_U_DEBUG] =    {        0x0,      0x100 },
  66     [SIFIVE_U_MROM] =     {     0x1000,    0x11000 },
  67     [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
  68     [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
  69     [SIFIVE_U_PRCI] =     { 0x10000000,     0x1000 },
  70     [SIFIVE_U_UART0] =    { 0x10010000,     0x1000 },
  71     [SIFIVE_U_UART1] =    { 0x10011000,     0x1000 },
  72     [SIFIVE_U_OTP] =      { 0x10070000,     0x1000 },
  73     [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
  74     [SIFIVE_U_GEM] =      { 0x10090000,     0x2000 },
  75     [SIFIVE_U_GEM_MGMT] = { 0x100a0000,     0x1000 },
  76 };
  77
  78 #define OTP_SERIAL          1
  79 #define GEM_REVISION        0x10070109
  80
  81 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
  82     uint64_t mem_size, const char *cmdline)
  83 {
  84     MachineState *ms = MACHINE(qdev_get_machine());
  85     void *fdt;
  86     int cpu;
  87     uint32_t *cells;
  88     char *nodename;
  89     char ethclk_names[] = "pclk\0hclk";
  90     uint32_t plic_phandle, prci_phandle, phandle = 1;
  91     uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
  92
  93     fdt = s->fdt = create_device_tree(&s->fdt_size);
  94     if (!fdt) {
  95         error_report("create_device_tree() failed");
  96         exit(1);
  97     }
  98
  99     qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
 100     qemu_fdt_setprop_string(fdt, "/", "compatible",
 101                             "sifive,hifive-unleashed-a00");
 102     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 103     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 104
 105     qemu_fdt_add_subnode(fdt, "/soc");
 106     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 107     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
 108     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 109     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 110
 111     hfclk_phandle = phandle++;
 112     nodename = g_strdup_printf("/hfclk");
 113     qemu_fdt_add_subnode(fdt, nodename);
 114     qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
 115     qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
 116     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 117         SIFIVE_U_HFCLK_FREQ);
 118     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
 119     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
 120     g_free(nodename);
 121
 122     rtcclk_phandle = phandle++;
 123     nodename = g_strdup_printf("/rtcclk");
 124     qemu_fdt_add_subnode(fdt, nodename);
 125     qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
 126     qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
 127     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 128         SIFIVE_U_RTCCLK_FREQ);
 129     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
 130     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
 131     g_free(nodename);
 132
 133     nodename = g_strdup_printf("/memory@%lx",
 134         (long)memmap[SIFIVE_U_DRAM].base);
 135     qemu_fdt_add_subnode(fdt, nodename);
 136     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 137         memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
 138         mem_size >> 32, mem_size);
 139     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 140     g_free(nodename);
 141
 142     qemu_fdt_add_subnode(fdt, "/cpus");
 143     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 144         SIFIVE_CLINT_TIMEBASE_FREQ);
 145     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 146     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 147
 148     for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
 149         int cpu_phandle = phandle++;
 150         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 151         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 152         char *isa;
 153         qemu_fdt_add_subnode(fdt, nodename);
 154         /* cpu 0 is the management hart that does not have mmu */
 155         if (cpu != 0) {
 156             qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 157             isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
 158         } else {
 159             isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
 160         }
 161         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 162         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 163         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 164         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 165         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 166         qemu_fdt_add_subnode(fdt, intc);
 167         qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
 168         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 169         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 170         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 171         g_free(isa);
 172         g_free(intc);
 173         g_free(nodename);
 174     }
 175
 176     cells =  g_new0(uint32_t, ms->smp.cpus * 4);
 177     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 178         nodename =
 179             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 180         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 181         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 182         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 183         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 184         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 185         g_free(nodename);
 186     }
 187     nodename = g_strdup_printf("/soc/clint@%lx",
 188         (long)memmap[SIFIVE_U_CLINT].base);
 189     qemu_fdt_add_subnode(fdt, nodename);
 190     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 191     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 192         0x0, memmap[SIFIVE_U_CLINT].base,
 193         0x0, memmap[SIFIVE_U_CLINT].size);
 194     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 195         cells, ms->smp.cpus * sizeof(uint32_t) * 4);
 196     g_free(cells);
 197     g_free(nodename);
 198
 199     prci_phandle = phandle++;
 200     nodename = g_strdup_printf("/soc/clock-controller@%lx",
 201         (long)memmap[SIFIVE_U_PRCI].base);
 202     qemu_fdt_add_subnode(fdt, nodename);
 203     qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
 204     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
 205     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 206         hfclk_phandle, rtcclk_phandle);
 207     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 208         0x0, memmap[SIFIVE_U_PRCI].base,
 209         0x0, memmap[SIFIVE_U_PRCI].size);
 210     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 211         "sifive,fu540-c000-prci");
 212     g_free(nodename);
 213
 214     plic_phandle = phandle++;
 215     cells =  g_new0(uint32_t, ms->smp.cpus * 4 - 2);
 216     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 217         nodename =
 218             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 219         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 220         /* cpu 0 is the management hart that does not have S-mode */
 221         if (cpu == 0) {
 222             cells[0] = cpu_to_be32(intc_phandle);
 223             cells[1] = cpu_to_be32(IRQ_M_EXT);
 224         } else {
 225             cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
 226             cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
 227             cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 228             cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
 229         }
 230         g_free(nodename);
 231     }
 232     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 233         (long)memmap[SIFIVE_U_PLIC].base);
 234     qemu_fdt_add_subnode(fdt, nodename);
 235     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
 236     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
 237     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 238     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 239         cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
 240     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 241         0x0, memmap[SIFIVE_U_PLIC].base,
 242         0x0, memmap[SIFIVE_U_PLIC].size);
 243     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
 244     qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 245     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 246     g_free(cells);
 247     g_free(nodename);
 248
 249     phy_phandle = phandle++;
 250     nodename = g_strdup_printf("/soc/ethernet@%lx",
 251         (long)memmap[SIFIVE_U_GEM].base);
 252     qemu_fdt_add_subnode(fdt, nodename);
 253     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 254         "sifive,fu540-c000-gem");
 255     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 256         0x0, memmap[SIFIVE_U_GEM].base,
 257         0x0, memmap[SIFIVE_U_GEM].size,
 258         0x0, memmap[SIFIVE_U_GEM_MGMT].base,
 259         0x0, memmap[SIFIVE_U_GEM_MGMT].size);
 260     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 261     qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
 262     qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
 263     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 264     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
 265     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 266         prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
 267     qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
 268         sizeof(ethclk_names));
 269     qemu_fdt_setprop(fdt, nodename, "local-mac-address",
 270         s->soc.gem.conf.macaddr.a, ETH_ALEN);
 271     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
 272     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
 273     g_free(nodename);
 274
 275     nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
 276         (long)memmap[SIFIVE_U_GEM].base);
 277     qemu_fdt_add_subnode(fdt, nodename);
 278     qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
 279     qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
 280     g_free(nodename);
 281
 282     nodename = g_strdup_printf("/soc/serial@%lx",
 283         (long)memmap[SIFIVE_U_UART0].base);
 284     qemu_fdt_add_subnode(fdt, nodename);
 285     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
 286     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 287         0x0, memmap[SIFIVE_U_UART0].base,
 288         0x0, memmap[SIFIVE_U_UART0].size);
 289     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 290         prci_phandle, PRCI_CLK_TLCLK);
 291     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 292     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
 293
 294     qemu_fdt_add_subnode(fdt, "/chosen");
 295     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 296     if (cmdline) {
 297         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 298     }
 299
 300     qemu_fdt_add_subnode(fdt, "/aliases");
 301     qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
 302
 303     g_free(nodename);
 304 }
 305
 306 static void riscv_sifive_u_init(MachineState *machine)
 307 {
 308     const struct MemmapEntry *memmap = sifive_u_memmap;
 309
 310     SiFiveUState *s = g_new0(SiFiveUState, 1);
 311     MemoryRegion *system_memory = get_system_memory();
 312     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 313     int i;
 314
 315     /* Initialize SoC */
 316     object_initialize_child(OBJECT(machine), "soc", &s->soc,
 317                             sizeof(s->soc), TYPE_RISCV_U_SOC,
 318                             &error_abort, NULL);
 319     object_property_set_bool(OBJECT(&s->soc), true, "realized",
 320                             &error_abort);
 321
 322     /* register RAM */
 323     memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
 324                            machine->ram_size, &error_fatal);
 325     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
 326                                 main_mem);
 327
 328     /* create device tree */
 329     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 330
 331     riscv_find_and_load_firmware(machine, BIOS_FILENAME,
 332                                  memmap[SIFIVE_U_DRAM].base);
 333
 334     if (machine->kernel_filename) {
 335         uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
 336
 337         if (machine->initrd_filename) {
 338             hwaddr start;
 339             hwaddr end = riscv_load_initrd(machine->initrd_filename,
 340                                            machine->ram_size, kernel_entry,
 341                                            &start);
 342             qemu_fdt_setprop_cell(s->fdt, "/chosen",
 343                                   "linux,initrd-start", start);
 344             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 345                                   end);
 346         }
 347     }
 348
 349     /* reset vector */
 350     uint32_t reset_vec[8] = {
 351         0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */
 352         0x02028593,                    /*     addi   a1, t0, %pcrel_lo(1b) */
 353         0xf1402573,                    /*     csrr   a0, mhartid  */
 354 #if defined(TARGET_RISCV32)
 355         0x0182a283,                    /*     lw     t0, 24(t0) */
 356 #elif defined(TARGET_RISCV64)
 357         0x0182b283,                    /*     ld     t0, 24(t0) */
 358 #endif
 359         0x00028067,                    /*     jr     t0 */
 360         0x00000000,
 361         memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
 362         0x00000000,
 363                                        /* dtb: */
 364     };
 365
 366     /* copy in the reset vector in little_endian byte order */
 367     for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 368         reset_vec[i] = cpu_to_le32(reset_vec[i]);
 369     }
 370     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 371                           memmap[SIFIVE_U_MROM].base, &address_space_memory);
 372
 373     /* copy in the device tree */
 374     if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
 375             memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
 376         error_report("not enough space to store device-tree");
 377         exit(1);
 378     }
 379     qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
 380     rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
 381                           memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
 382                           &address_space_memory);
 383 }
 384
 385 static void riscv_sifive_u_soc_init(Object *obj)
 386 {
 387     MachineState *ms = MACHINE(qdev_get_machine());
 388     SiFiveUSoCState *s = RISCV_U_SOC(obj);
 389
 390     object_initialize_child(obj, "e-cluster", &s->e_cluster,
 391                             sizeof(s->e_cluster), TYPE_CPU_CLUSTER,
 392                             &error_abort, NULL);
 393     qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
 394
 395     object_initialize_child(OBJECT(&s->e_cluster), "e-cpus",
 396                             &s->e_cpus, sizeof(s->e_cpus),
 397                             TYPE_RISCV_HART_ARRAY, &error_abort,
 398                             NULL);
 399     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
 400     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
 401     qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
 402
 403     object_initialize_child(obj, "u-cluster", &s->u_cluster,
 404                             sizeof(s->u_cluster), TYPE_CPU_CLUSTER,
 405                             &error_abort, NULL);
 406     qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
 407
 408     object_initialize_child(OBJECT(&s->u_cluster), "u-cpus",
 409                             &s->u_cpus, sizeof(s->u_cpus),
 410                             TYPE_RISCV_HART_ARRAY, &error_abort,
 411                             NULL);
 412     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
 413     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
 414     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
 415
 416     sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
 417                           TYPE_SIFIVE_U_PRCI);
 418     sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
 419                           TYPE_SIFIVE_U_OTP);
 420     qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
 421     sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
 422                           TYPE_CADENCE_GEM);
 423 }
 424
 425 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
 426 {
 427     MachineState *ms = MACHINE(qdev_get_machine());
 428     SiFiveUSoCState *s = RISCV_U_SOC(dev);
 429     const struct MemmapEntry *memmap = sifive_u_memmap;
 430     MemoryRegion *system_memory = get_system_memory();
 431     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 432     qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
 433     char *plic_hart_config;
 434     size_t plic_hart_config_len;
 435     int i;
 436     Error *err = NULL;
 437     NICInfo *nd = &nd_table[0];
 438
 439     object_property_set_bool(OBJECT(&s->e_cpus), true, "realized",
 440                              &error_abort);
 441     object_property_set_bool(OBJECT(&s->u_cpus), true, "realized",
 442                              &error_abort);
 443     /*
 444      * The cluster must be realized after the RISC-V hart array container,
 445      * as the container's CPU object is only created on realize, and the
 446      * CPU must exist and have been parented into the cluster before the
 447      * cluster is realized.
 448      */
 449     object_property_set_bool(OBJECT(&s->e_cluster), true, "realized",
 450                              &error_abort);
 451     object_property_set_bool(OBJECT(&s->u_cluster), true, "realized",
 452                              &error_abort);
 453
 454     /* boot rom */
 455     memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
 456                            memmap[SIFIVE_U_MROM].size, &error_fatal);
 457     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
 458                                 mask_rom);
 459
 460     /* create PLIC hart topology configuration string */
 461     plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
 462                            ms->smp.cpus;
 463     plic_hart_config = g_malloc0(plic_hart_config_len);
 464     for (i = 0; i < ms->smp.cpus; i++) {
 465         if (i != 0) {
 466             strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
 467                     plic_hart_config_len);
 468         } else {
 469             strncat(plic_hart_config, "M", plic_hart_config_len);
 470         }
 471         plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
 472     }
 473
 474     /* MMIO */
 475     s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
 476         plic_hart_config,
 477         SIFIVE_U_PLIC_NUM_SOURCES,
 478         SIFIVE_U_PLIC_NUM_PRIORITIES,
 479         SIFIVE_U_PLIC_PRIORITY_BASE,
 480         SIFIVE_U_PLIC_PENDING_BASE,
 481         SIFIVE_U_PLIC_ENABLE_BASE,
 482         SIFIVE_U_PLIC_ENABLE_STRIDE,
 483         SIFIVE_U_PLIC_CONTEXT_BASE,
 484         SIFIVE_U_PLIC_CONTEXT_STRIDE,
 485         memmap[SIFIVE_U_PLIC].size);
 486     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
 487         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
 488     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
 489         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
 490     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
 491         memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
 492         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 493
 494     object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
 495     sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
 496
 497     object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
 498     sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
 499
 500     for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
 501         plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
 502     }
 503
 504     if (nd->used) {
 505         qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 506         qdev_set_nic_properties(DEVICE(&s->gem), nd);
 507     }
 508     object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
 509                             &error_abort);
 510     object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
 511     if (err) {
 512         error_propagate(errp, err);
 513         return;
 514     }
 515     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
 516     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
 517                        plic_gpios[SIFIVE_U_GEM_IRQ]);
 518
 519     create_unimplemented_device("riscv.sifive.u.gem-mgmt",
 520         memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
 521 }
 522
 523 static void riscv_sifive_u_machine_init(MachineClass *mc)
 524 {
 525     mc->desc = "RISC-V Board compatible with SiFive U SDK";
 526     mc->init = riscv_sifive_u_init;
 527     mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
 528     mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
 529     mc->default_cpus = mc->min_cpus;
 530 }
 531
 532 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
 533
 534 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
 535 {
 536     DeviceClass *dc = DEVICE_CLASS(oc);
 537
 538     dc->realize = riscv_sifive_u_soc_realize;
 539     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 540     dc->user_creatable = false;
 541 }
 542
 543 static const TypeInfo riscv_sifive_u_soc_type_info = {
 544     .name = TYPE_RISCV_U_SOC,
 545     .parent = TYPE_DEVICE,
 546     .instance_size = sizeof(SiFiveUSoCState),
 547     .instance_init = riscv_sifive_u_soc_init,
 548     .class_init = riscv_sifive_u_soc_class_init,
 549 };
 550
 551 static void riscv_sifive_u_soc_register_types(void)
 552 {
 553     type_register_static(&riscv_sifive_u_soc_type_info);
 554 }
 555
 556 type_init(riscv_sifive_u_soc_register_types)