2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
7 * Provides a board compatible with the SiFive Freedom U SDK:
10 * 1) CLINT (Core Level Interruptor)
11 * 2) PLIC (Platform Level Interrupt Controller)
12 * 3) PRCI (Power, Reset, Clock, Interrupt)
14 * This board currently generates devicetree dynamically that indicates at least
15 * two harts and up to five harts.
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms and conditions of the GNU General Public License,
19 * version 2 or later, as published by the Free Software Foundation.
21 * This program is distributed in the hope it will be useful, but WITHOUT
22 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
26 * You should have received a copy of the GNU General Public License along with
27 * this program. If not, see <http://www.gnu.org/licenses/>.
30 #include "qemu/osdep.h"
32 #include "qemu/error-report.h"
33 #include "qapi/error.h"
34 #include "hw/boards.h"
35 #include "hw/loader.h"
36 #include "hw/sysbus.h"
37 #include "hw/char/serial.h"
38 #include "hw/cpu/cluster.h"
39 #include "target/riscv/cpu.h"
40 #include "hw/riscv/riscv_hart.h"
41 #include "hw/riscv/sifive_plic.h"
42 #include "hw/riscv/sifive_clint.h"
43 #include "hw/riscv/sifive_uart.h"
44 #include "hw/riscv/sifive_u.h"
45 #include "hw/riscv/boot.h"
46 #include "chardev/char.h"
47 #include "sysemu/arch_init.h"
48 #include "sysemu/device_tree.h"
49 #include "sysemu/sysemu.h"
50 #include "exec/address-spaces.h"
54 #define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin"
56 static const struct MemmapEntry
{
59 } sifive_u_memmap
[] = {
60 [SIFIVE_U_DEBUG
] = { 0x0, 0x100 },
61 [SIFIVE_U_MROM
] = { 0x1000, 0x11000 },
62 [SIFIVE_U_CLINT
] = { 0x2000000, 0x10000 },
63 [SIFIVE_U_PLIC
] = { 0xc000000, 0x4000000 },
64 [SIFIVE_U_PRCI
] = { 0x10000000, 0x1000 },
65 [SIFIVE_U_UART0
] = { 0x10010000, 0x1000 },
66 [SIFIVE_U_UART1
] = { 0x10011000, 0x1000 },
67 [SIFIVE_U_DRAM
] = { 0x80000000, 0x0 },
68 [SIFIVE_U_GEM
] = { 0x100900FC, 0x2000 },
71 #define GEM_REVISION 0x10070109
73 static void create_fdt(SiFiveUState
*s
, const struct MemmapEntry
*memmap
,
74 uint64_t mem_size
, const char *cmdline
)
76 MachineState
*ms
= MACHINE(qdev_get_machine());
81 char ethclk_names
[] = "pclk\0hclk";
82 uint32_t plic_phandle
, prci_phandle
, ethclk_phandle
, phandle
= 1;
83 uint32_t uartclk_phandle
;
84 uint32_t hfclk_phandle
, rtcclk_phandle
;
86 fdt
= s
->fdt
= create_device_tree(&s
->fdt_size
);
88 error_report("create_device_tree() failed");
92 qemu_fdt_setprop_string(fdt
, "/", "model", "ucbbar,spike-bare,qemu");
93 qemu_fdt_setprop_string(fdt
, "/", "compatible", "ucbbar,spike-bare-dev");
94 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
95 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
97 qemu_fdt_add_subnode(fdt
, "/soc");
98 qemu_fdt_setprop(fdt
, "/soc", "ranges", NULL
, 0);
99 qemu_fdt_setprop_string(fdt
, "/soc", "compatible", "simple-bus");
100 qemu_fdt_setprop_cell(fdt
, "/soc", "#size-cells", 0x2);
101 qemu_fdt_setprop_cell(fdt
, "/soc", "#address-cells", 0x2);
103 hfclk_phandle
= phandle
++;
104 nodename
= g_strdup_printf("/hfclk");
105 qemu_fdt_add_subnode(fdt
, nodename
);
106 qemu_fdt_setprop_cell(fdt
, nodename
, "phandle", hfclk_phandle
);
107 qemu_fdt_setprop_string(fdt
, nodename
, "clock-output-names", "hfclk");
108 qemu_fdt_setprop_cell(fdt
, nodename
, "clock-frequency",
109 SIFIVE_U_HFCLK_FREQ
);
110 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "fixed-clock");
111 qemu_fdt_setprop_cell(fdt
, nodename
, "#clock-cells", 0x0);
114 rtcclk_phandle
= phandle
++;
115 nodename
= g_strdup_printf("/rtcclk");
116 qemu_fdt_add_subnode(fdt
, nodename
);
117 qemu_fdt_setprop_cell(fdt
, nodename
, "phandle", rtcclk_phandle
);
118 qemu_fdt_setprop_string(fdt
, nodename
, "clock-output-names", "rtcclk");
119 qemu_fdt_setprop_cell(fdt
, nodename
, "clock-frequency",
120 SIFIVE_U_RTCCLK_FREQ
);
121 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "fixed-clock");
122 qemu_fdt_setprop_cell(fdt
, nodename
, "#clock-cells", 0x0);
125 nodename
= g_strdup_printf("/memory@%lx",
126 (long)memmap
[SIFIVE_U_DRAM
].base
);
127 qemu_fdt_add_subnode(fdt
, nodename
);
128 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
129 memmap
[SIFIVE_U_DRAM
].base
>> 32, memmap
[SIFIVE_U_DRAM
].base
,
130 mem_size
>> 32, mem_size
);
131 qemu_fdt_setprop_string(fdt
, nodename
, "device_type", "memory");
134 qemu_fdt_add_subnode(fdt
, "/cpus");
135 qemu_fdt_setprop_cell(fdt
, "/cpus", "timebase-frequency",
136 SIFIVE_CLINT_TIMEBASE_FREQ
);
137 qemu_fdt_setprop_cell(fdt
, "/cpus", "#size-cells", 0x0);
138 qemu_fdt_setprop_cell(fdt
, "/cpus", "#address-cells", 0x1);
140 for (cpu
= ms
->smp
.cpus
- 1; cpu
>= 0; cpu
--) {
141 int cpu_phandle
= phandle
++;
142 nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
143 char *intc
= g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu
);
145 qemu_fdt_add_subnode(fdt
, nodename
);
146 qemu_fdt_setprop_cell(fdt
, nodename
, "clock-frequency",
147 SIFIVE_U_CLOCK_FREQ
);
148 /* cpu 0 is the management hart that does not have mmu */
150 qemu_fdt_setprop_string(fdt
, nodename
, "mmu-type", "riscv,sv48");
151 isa
= riscv_isa_string(&s
->soc
.u_cpus
.harts
[cpu
- 1]);
153 isa
= riscv_isa_string(&s
->soc
.e_cpus
.harts
[0]);
155 qemu_fdt_setprop_string(fdt
, nodename
, "riscv,isa", isa
);
156 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "riscv");
157 qemu_fdt_setprop_string(fdt
, nodename
, "status", "okay");
158 qemu_fdt_setprop_cell(fdt
, nodename
, "reg", cpu
);
159 qemu_fdt_setprop_string(fdt
, nodename
, "device_type", "cpu");
160 qemu_fdt_add_subnode(fdt
, intc
);
161 qemu_fdt_setprop_cell(fdt
, intc
, "phandle", cpu_phandle
);
162 qemu_fdt_setprop_string(fdt
, intc
, "compatible", "riscv,cpu-intc");
163 qemu_fdt_setprop(fdt
, intc
, "interrupt-controller", NULL
, 0);
164 qemu_fdt_setprop_cell(fdt
, intc
, "#interrupt-cells", 1);
170 cells
= g_new0(uint32_t, ms
->smp
.cpus
* 4);
171 for (cpu
= 0; cpu
< ms
->smp
.cpus
; cpu
++) {
173 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu
);
174 uint32_t intc_phandle
= qemu_fdt_get_phandle(fdt
, nodename
);
175 cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandle
);
176 cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_SOFT
);
177 cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandle
);
178 cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_M_TIMER
);
181 nodename
= g_strdup_printf("/soc/clint@%lx",
182 (long)memmap
[SIFIVE_U_CLINT
].base
);
183 qemu_fdt_add_subnode(fdt
, nodename
);
184 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "riscv,clint0");
185 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
186 0x0, memmap
[SIFIVE_U_CLINT
].base
,
187 0x0, memmap
[SIFIVE_U_CLINT
].size
);
188 qemu_fdt_setprop(fdt
, nodename
, "interrupts-extended",
189 cells
, ms
->smp
.cpus
* sizeof(uint32_t) * 4);
193 prci_phandle
= phandle
++;
194 nodename
= g_strdup_printf("/soc/clock-controller@%lx",
195 (long)memmap
[SIFIVE_U_PRCI
].base
);
196 qemu_fdt_add_subnode(fdt
, nodename
);
197 qemu_fdt_setprop_cell(fdt
, nodename
, "phandle", prci_phandle
);
198 qemu_fdt_setprop_cell(fdt
, nodename
, "#clock-cells", 0x1);
199 qemu_fdt_setprop_cells(fdt
, nodename
, "clocks",
200 hfclk_phandle
, rtcclk_phandle
);
201 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
202 0x0, memmap
[SIFIVE_U_PRCI
].base
,
203 0x0, memmap
[SIFIVE_U_PRCI
].size
);
204 qemu_fdt_setprop_string(fdt
, nodename
, "compatible",
205 "sifive,fu540-c000-prci");
208 plic_phandle
= phandle
++;
209 cells
= g_new0(uint32_t, ms
->smp
.cpus
* 4 - 2);
210 for (cpu
= 0; cpu
< ms
->smp
.cpus
; cpu
++) {
212 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu
);
213 uint32_t intc_phandle
= qemu_fdt_get_phandle(fdt
, nodename
);
214 /* cpu 0 is the management hart that does not have S-mode */
216 cells
[0] = cpu_to_be32(intc_phandle
);
217 cells
[1] = cpu_to_be32(IRQ_M_EXT
);
219 cells
[cpu
* 4 - 2] = cpu_to_be32(intc_phandle
);
220 cells
[cpu
* 4 - 1] = cpu_to_be32(IRQ_M_EXT
);
221 cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandle
);
222 cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_S_EXT
);
226 nodename
= g_strdup_printf("/soc/interrupt-controller@%lx",
227 (long)memmap
[SIFIVE_U_PLIC
].base
);
228 qemu_fdt_add_subnode(fdt
, nodename
);
229 qemu_fdt_setprop_cell(fdt
, nodename
, "#interrupt-cells", 1);
230 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "riscv,plic0");
231 qemu_fdt_setprop(fdt
, nodename
, "interrupt-controller", NULL
, 0);
232 qemu_fdt_setprop(fdt
, nodename
, "interrupts-extended",
233 cells
, (ms
->smp
.cpus
* 4 - 2) * sizeof(uint32_t));
234 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
235 0x0, memmap
[SIFIVE_U_PLIC
].base
,
236 0x0, memmap
[SIFIVE_U_PLIC
].size
);
237 qemu_fdt_setprop_cell(fdt
, nodename
, "riscv,ndev", 0x35);
238 qemu_fdt_setprop_cell(fdt
, nodename
, "phandle", plic_phandle
);
239 plic_phandle
= qemu_fdt_get_phandle(fdt
, nodename
);
243 ethclk_phandle
= phandle
++;
244 nodename
= g_strdup_printf("/soc/ethclk");
245 qemu_fdt_add_subnode(fdt
, nodename
);
246 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "fixed-clock");
247 qemu_fdt_setprop_cell(fdt
, nodename
, "#clock-cells", 0x0);
248 qemu_fdt_setprop_cell(fdt
, nodename
, "clock-frequency",
249 SIFIVE_U_GEM_CLOCK_FREQ
);
250 qemu_fdt_setprop_cell(fdt
, nodename
, "phandle", ethclk_phandle
);
251 ethclk_phandle
= qemu_fdt_get_phandle(fdt
, nodename
);
254 nodename
= g_strdup_printf("/soc/ethernet@%lx",
255 (long)memmap
[SIFIVE_U_GEM
].base
);
256 qemu_fdt_add_subnode(fdt
, nodename
);
257 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "cdns,macb");
258 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
259 0x0, memmap
[SIFIVE_U_GEM
].base
,
260 0x0, memmap
[SIFIVE_U_GEM
].size
);
261 qemu_fdt_setprop_string(fdt
, nodename
, "reg-names", "control");
262 qemu_fdt_setprop_string(fdt
, nodename
, "phy-mode", "gmii");
263 qemu_fdt_setprop_cell(fdt
, nodename
, "interrupt-parent", plic_phandle
);
264 qemu_fdt_setprop_cell(fdt
, nodename
, "interrupts", SIFIVE_U_GEM_IRQ
);
265 qemu_fdt_setprop_cells(fdt
, nodename
, "clocks",
266 prci_phandle
, PRCI_CLK_GEMGXLPLL
, prci_phandle
, PRCI_CLK_GEMGXLPLL
);
267 qemu_fdt_setprop(fdt
, nodename
, "clock-names", ethclk_names
,
268 sizeof(ethclk_names
));
269 qemu_fdt_setprop_cell(fdt
, nodename
, "#address-cells", 1);
270 qemu_fdt_setprop_cell(fdt
, nodename
, "#size-cells", 0);
273 nodename
= g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
274 (long)memmap
[SIFIVE_U_GEM
].base
);
275 qemu_fdt_add_subnode(fdt
, nodename
);
276 qemu_fdt_setprop_cell(fdt
, nodename
, "reg", 0x0);
279 uartclk_phandle
= phandle
++;
280 nodename
= g_strdup_printf("/soc/uartclk");
281 qemu_fdt_add_subnode(fdt
, nodename
);
282 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "fixed-clock");
283 qemu_fdt_setprop_cell(fdt
, nodename
, "#clock-cells", 0x0);
284 qemu_fdt_setprop_cell(fdt
, nodename
, "clock-frequency", 3686400);
285 qemu_fdt_setprop_cell(fdt
, nodename
, "phandle", uartclk_phandle
);
286 uartclk_phandle
= qemu_fdt_get_phandle(fdt
, nodename
);
289 nodename
= g_strdup_printf("/soc/serial@%lx",
290 (long)memmap
[SIFIVE_U_UART0
].base
);
291 qemu_fdt_add_subnode(fdt
, nodename
);
292 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "sifive,uart0");
293 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
294 0x0, memmap
[SIFIVE_U_UART0
].base
,
295 0x0, memmap
[SIFIVE_U_UART0
].size
);
296 qemu_fdt_setprop_cells(fdt
, nodename
, "clocks",
297 prci_phandle
, PRCI_CLK_TLCLK
);
298 qemu_fdt_setprop_cell(fdt
, nodename
, "interrupt-parent", plic_phandle
);
299 qemu_fdt_setprop_cell(fdt
, nodename
, "interrupts", SIFIVE_U_UART0_IRQ
);
301 qemu_fdt_add_subnode(fdt
, "/chosen");
302 qemu_fdt_setprop_string(fdt
, "/chosen", "stdout-path", nodename
);
304 qemu_fdt_setprop_string(fdt
, "/chosen", "bootargs", cmdline
);
307 qemu_fdt_add_subnode(fdt
, "/aliases");
308 qemu_fdt_setprop_string(fdt
, "/aliases", "serial0", nodename
);
313 static void riscv_sifive_u_init(MachineState
*machine
)
315 const struct MemmapEntry
*memmap
= sifive_u_memmap
;
317 SiFiveUState
*s
= g_new0(SiFiveUState
, 1);
318 MemoryRegion
*system_memory
= get_system_memory();
319 MemoryRegion
*main_mem
= g_new(MemoryRegion
, 1);
323 object_initialize_child(OBJECT(machine
), "soc", &s
->soc
,
324 sizeof(s
->soc
), TYPE_RISCV_U_SOC
,
326 object_property_set_bool(OBJECT(&s
->soc
), true, "realized",
330 memory_region_init_ram(main_mem
, NULL
, "riscv.sifive.u.ram",
331 machine
->ram_size
, &error_fatal
);
332 memory_region_add_subregion(system_memory
, memmap
[SIFIVE_U_DRAM
].base
,
335 /* create device tree */
336 create_fdt(s
, memmap
, machine
->ram_size
, machine
->kernel_cmdline
);
338 riscv_find_and_load_firmware(machine
, BIOS_FILENAME
,
339 memmap
[SIFIVE_U_DRAM
].base
);
341 if (machine
->kernel_filename
) {
342 uint64_t kernel_entry
= riscv_load_kernel(machine
->kernel_filename
);
344 if (machine
->initrd_filename
) {
346 hwaddr end
= riscv_load_initrd(machine
->initrd_filename
,
347 machine
->ram_size
, kernel_entry
,
349 qemu_fdt_setprop_cell(s
->fdt
, "/chosen",
350 "linux,initrd-start", start
);
351 qemu_fdt_setprop_cell(s
->fdt
, "/chosen", "linux,initrd-end",
357 uint32_t reset_vec
[8] = {
358 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
359 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
360 0xf1402573, /* csrr a0, mhartid */
361 #if defined(TARGET_RISCV32)
362 0x0182a283, /* lw t0, 24(t0) */
363 #elif defined(TARGET_RISCV64)
364 0x0182b283, /* ld t0, 24(t0) */
366 0x00028067, /* jr t0 */
368 memmap
[SIFIVE_U_DRAM
].base
, /* start: .dword DRAM_BASE */
373 /* copy in the reset vector in little_endian byte order */
374 for (i
= 0; i
< sizeof(reset_vec
) >> 2; i
++) {
375 reset_vec
[i
] = cpu_to_le32(reset_vec
[i
]);
377 rom_add_blob_fixed_as("mrom.reset", reset_vec
, sizeof(reset_vec
),
378 memmap
[SIFIVE_U_MROM
].base
, &address_space_memory
);
380 /* copy in the device tree */
381 if (fdt_pack(s
->fdt
) || fdt_totalsize(s
->fdt
) >
382 memmap
[SIFIVE_U_MROM
].size
- sizeof(reset_vec
)) {
383 error_report("not enough space to store device-tree");
386 qemu_fdt_dumpdtb(s
->fdt
, fdt_totalsize(s
->fdt
));
387 rom_add_blob_fixed_as("mrom.fdt", s
->fdt
, fdt_totalsize(s
->fdt
),
388 memmap
[SIFIVE_U_MROM
].base
+ sizeof(reset_vec
),
389 &address_space_memory
);
392 static void riscv_sifive_u_soc_init(Object
*obj
)
394 MachineState
*ms
= MACHINE(qdev_get_machine());
395 SiFiveUSoCState
*s
= RISCV_U_SOC(obj
);
397 object_initialize_child(obj
, "e-cluster", &s
->e_cluster
,
398 sizeof(s
->e_cluster
), TYPE_CPU_CLUSTER
,
400 qdev_prop_set_uint32(DEVICE(&s
->e_cluster
), "cluster-id", 0);
402 object_initialize_child(OBJECT(&s
->e_cluster
), "e-cpus",
403 &s
->e_cpus
, sizeof(s
->e_cpus
),
404 TYPE_RISCV_HART_ARRAY
, &error_abort
,
406 qdev_prop_set_uint32(DEVICE(&s
->e_cpus
), "num-harts", 1);
407 qdev_prop_set_uint32(DEVICE(&s
->e_cpus
), "hartid-base", 0);
408 qdev_prop_set_string(DEVICE(&s
->e_cpus
), "cpu-type", SIFIVE_E_CPU
);
410 object_initialize_child(obj
, "u-cluster", &s
->u_cluster
,
411 sizeof(s
->u_cluster
), TYPE_CPU_CLUSTER
,
413 qdev_prop_set_uint32(DEVICE(&s
->u_cluster
), "cluster-id", 1);
415 object_initialize_child(OBJECT(&s
->u_cluster
), "u-cpus",
416 &s
->u_cpus
, sizeof(s
->u_cpus
),
417 TYPE_RISCV_HART_ARRAY
, &error_abort
,
419 qdev_prop_set_uint32(DEVICE(&s
->u_cpus
), "num-harts", ms
->smp
.cpus
- 1);
420 qdev_prop_set_uint32(DEVICE(&s
->u_cpus
), "hartid-base", 1);
421 qdev_prop_set_string(DEVICE(&s
->u_cpus
), "cpu-type", SIFIVE_U_CPU
);
423 sysbus_init_child_obj(obj
, "prci", &s
->prci
, sizeof(s
->prci
),
425 sysbus_init_child_obj(obj
, "gem", &s
->gem
, sizeof(s
->gem
),
429 static void riscv_sifive_u_soc_realize(DeviceState
*dev
, Error
**errp
)
431 MachineState
*ms
= MACHINE(qdev_get_machine());
432 SiFiveUSoCState
*s
= RISCV_U_SOC(dev
);
433 const struct MemmapEntry
*memmap
= sifive_u_memmap
;
434 MemoryRegion
*system_memory
= get_system_memory();
435 MemoryRegion
*mask_rom
= g_new(MemoryRegion
, 1);
436 qemu_irq plic_gpios
[SIFIVE_U_PLIC_NUM_SOURCES
];
437 char *plic_hart_config
;
438 size_t plic_hart_config_len
;
441 NICInfo
*nd
= &nd_table
[0];
443 object_property_set_bool(OBJECT(&s
->e_cpus
), true, "realized",
445 object_property_set_bool(OBJECT(&s
->u_cpus
), true, "realized",
448 * The cluster must be realized after the RISC-V hart array container,
449 * as the container's CPU object is only created on realize, and the
450 * CPU must exist and have been parented into the cluster before the
451 * cluster is realized.
453 object_property_set_bool(OBJECT(&s
->e_cluster
), true, "realized",
455 object_property_set_bool(OBJECT(&s
->u_cluster
), true, "realized",
459 memory_region_init_rom(mask_rom
, NULL
, "riscv.sifive.u.mrom",
460 memmap
[SIFIVE_U_MROM
].size
, &error_fatal
);
461 memory_region_add_subregion(system_memory
, memmap
[SIFIVE_U_MROM
].base
,
464 /* create PLIC hart topology configuration string */
465 plic_hart_config_len
= (strlen(SIFIVE_U_PLIC_HART_CONFIG
) + 1) *
467 plic_hart_config
= g_malloc0(plic_hart_config_len
);
468 for (i
= 0; i
< ms
->smp
.cpus
; i
++) {
470 strncat(plic_hart_config
, "," SIFIVE_U_PLIC_HART_CONFIG
,
471 plic_hart_config_len
);
473 strncat(plic_hart_config
, "M", plic_hart_config_len
);
475 plic_hart_config_len
-= (strlen(SIFIVE_U_PLIC_HART_CONFIG
) + 1);
479 s
->plic
= sifive_plic_create(memmap
[SIFIVE_U_PLIC
].base
,
481 SIFIVE_U_PLIC_NUM_SOURCES
,
482 SIFIVE_U_PLIC_NUM_PRIORITIES
,
483 SIFIVE_U_PLIC_PRIORITY_BASE
,
484 SIFIVE_U_PLIC_PENDING_BASE
,
485 SIFIVE_U_PLIC_ENABLE_BASE
,
486 SIFIVE_U_PLIC_ENABLE_STRIDE
,
487 SIFIVE_U_PLIC_CONTEXT_BASE
,
488 SIFIVE_U_PLIC_CONTEXT_STRIDE
,
489 memmap
[SIFIVE_U_PLIC
].size
);
490 sifive_uart_create(system_memory
, memmap
[SIFIVE_U_UART0
].base
,
491 serial_hd(0), qdev_get_gpio_in(DEVICE(s
->plic
), SIFIVE_U_UART0_IRQ
));
492 sifive_uart_create(system_memory
, memmap
[SIFIVE_U_UART1
].base
,
493 serial_hd(1), qdev_get_gpio_in(DEVICE(s
->plic
), SIFIVE_U_UART1_IRQ
));
494 sifive_clint_create(memmap
[SIFIVE_U_CLINT
].base
,
495 memmap
[SIFIVE_U_CLINT
].size
, ms
->smp
.cpus
,
496 SIFIVE_SIP_BASE
, SIFIVE_TIMECMP_BASE
, SIFIVE_TIME_BASE
);
498 object_property_set_bool(OBJECT(&s
->prci
), true, "realized", &err
);
499 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->prci
), 0, memmap
[SIFIVE_U_PRCI
].base
);
501 for (i
= 0; i
< SIFIVE_U_PLIC_NUM_SOURCES
; i
++) {
502 plic_gpios
[i
] = qdev_get_gpio_in(DEVICE(s
->plic
), i
);
506 qemu_check_nic_model(nd
, TYPE_CADENCE_GEM
);
507 qdev_set_nic_properties(DEVICE(&s
->gem
), nd
);
509 object_property_set_int(OBJECT(&s
->gem
), GEM_REVISION
, "revision",
511 object_property_set_bool(OBJECT(&s
->gem
), true, "realized", &err
);
513 error_propagate(errp
, err
);
516 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gem
), 0, memmap
[SIFIVE_U_GEM
].base
);
517 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gem
), 0,
518 plic_gpios
[SIFIVE_U_GEM_IRQ
]);
521 static void riscv_sifive_u_machine_init(MachineClass
*mc
)
523 mc
->desc
= "RISC-V Board compatible with SiFive U SDK";
524 mc
->init
= riscv_sifive_u_init
;
525 mc
->max_cpus
= SIFIVE_U_MANAGEMENT_CPU_COUNT
+ SIFIVE_U_COMPUTE_CPU_COUNT
;
526 mc
->min_cpus
= SIFIVE_U_MANAGEMENT_CPU_COUNT
+ 1;
527 mc
->default_cpus
= mc
->min_cpus
;
530 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init
)
532 static void riscv_sifive_u_soc_class_init(ObjectClass
*oc
, void *data
)
534 DeviceClass
*dc
= DEVICE_CLASS(oc
);
536 dc
->realize
= riscv_sifive_u_soc_realize
;
537 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
538 dc
->user_creatable
= false;
541 static const TypeInfo riscv_sifive_u_soc_type_info
= {
542 .name
= TYPE_RISCV_U_SOC
,
543 .parent
= TYPE_DEVICE
,
544 .instance_size
= sizeof(SiFiveUSoCState
),
545 .instance_init
= riscv_sifive_u_soc_init
,
546 .class_init
= riscv_sifive_u_soc_class_init
,
549 static void riscv_sifive_u_soc_register_types(void)
551 type_register_static(&riscv_sifive_u_soc_type_info
);
554 type_init(riscv_sifive_u_soc_register_types
)