hw/riscv/sifive_u.c

   1 /*
   2  * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017 SiFive, Inc.
   6  *
   7  * Provides a board compatible with the SiFive Freedom U SDK:
   8  *
   9  * 0) UART
  10  * 1) CLINT (Core Level Interruptor)
  11  * 2) PLIC (Platform Level Interrupt Controller)
  12  *
  13  * This board currently generates devicetree dynamically that indicates at least
  14  * two harts and up to five harts.
  15  *
  16  * This program is free software; you can redistribute it and/or modify it
  17  * under the terms and conditions of the GNU General Public License,
  18  * version 2 or later, as published by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope it will be useful, but WITHOUT
  21  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  23  * more details.
  24  *
  25  * You should have received a copy of the GNU General Public License along with
  26  * this program.  If not, see <http://www.gnu.org/licenses/>.
  27  */
  28
  29 #include "qemu/osdep.h"
  30 #include "qemu/log.h"
  31 #include "qemu/error-report.h"
  32 #include "qapi/error.h"
  33 #include "hw/boards.h"
  34 #include "hw/loader.h"
  35 #include "hw/sysbus.h"
  36 #include "hw/char/serial.h"
  37 #include "hw/cpu/cluster.h"
  38 #include "target/riscv/cpu.h"
  39 #include "hw/riscv/riscv_hart.h"
  40 #include "hw/riscv/sifive_plic.h"
  41 #include "hw/riscv/sifive_clint.h"
  42 #include "hw/riscv/sifive_uart.h"
  43 #include "hw/riscv/sifive_u.h"
  44 #include "hw/riscv/boot.h"
  45 #include "chardev/char.h"
  46 #include "sysemu/arch_init.h"
  47 #include "sysemu/device_tree.h"
  48 #include "sysemu/sysemu.h"
  49 #include "exec/address-spaces.h"
  50
  51 #include <libfdt.h>
  52
  53 #define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin"
  54
  55 static const struct MemmapEntry {
  56     hwaddr base;
  57     hwaddr size;
  58 } sifive_u_memmap[] = {
  59     [SIFIVE_U_DEBUG] =    {        0x0,      0x100 },
  60     [SIFIVE_U_MROM] =     {     0x1000,    0x11000 },
  61     [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
  62     [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
  63     [SIFIVE_U_UART0] =    { 0x10013000,     0x1000 },
  64     [SIFIVE_U_UART1] =    { 0x10023000,     0x1000 },
  65     [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
  66     [SIFIVE_U_GEM] =      { 0x100900FC,     0x2000 },
  67 };
  68
  69 #define GEM_REVISION        0x10070109
  70
  71 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
  72     uint64_t mem_size, const char *cmdline)
  73 {
  74     MachineState *ms = MACHINE(qdev_get_machine());
  75     void *fdt;
  76     int cpu;
  77     uint32_t *cells;
  78     char *nodename;
  79     char ethclk_names[] = "pclk\0hclk\0tx_clk";
  80     uint32_t plic_phandle, ethclk_phandle, phandle = 1;
  81     uint32_t uartclk_phandle;
  82     uint32_t hfclk_phandle, rtcclk_phandle;
  83
  84     fdt = s->fdt = create_device_tree(&s->fdt_size);
  85     if (!fdt) {
  86         error_report("create_device_tree() failed");
  87         exit(1);
  88     }
  89
  90     qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
  91     qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
  92     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
  93     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
  94
  95     qemu_fdt_add_subnode(fdt, "/soc");
  96     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
  97     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
  98     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
  99     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 100
 101     hfclk_phandle = phandle++;
 102     nodename = g_strdup_printf("/hfclk");
 103     qemu_fdt_add_subnode(fdt, nodename);
 104     qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
 105     qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
 106     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 107         SIFIVE_U_HFCLK_FREQ);
 108     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
 109     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
 110     g_free(nodename);
 111
 112     rtcclk_phandle = phandle++;
 113     nodename = g_strdup_printf("/rtcclk");
 114     qemu_fdt_add_subnode(fdt, nodename);
 115     qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
 116     qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
 117     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 118         SIFIVE_U_RTCCLK_FREQ);
 119     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
 120     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
 121     g_free(nodename);
 122
 123     nodename = g_strdup_printf("/memory@%lx",
 124         (long)memmap[SIFIVE_U_DRAM].base);
 125     qemu_fdt_add_subnode(fdt, nodename);
 126     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 127         memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
 128         mem_size >> 32, mem_size);
 129     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 130     g_free(nodename);
 131
 132     qemu_fdt_add_subnode(fdt, "/cpus");
 133     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 134         SIFIVE_CLINT_TIMEBASE_FREQ);
 135     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 136     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 137
 138     for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
 139         int cpu_phandle = phandle++;
 140         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 141         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 142         char *isa;
 143         qemu_fdt_add_subnode(fdt, nodename);
 144         qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 145                               SIFIVE_U_CLOCK_FREQ);
 146         /* cpu 0 is the management hart that does not have mmu */
 147         if (cpu != 0) {
 148             qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 149             isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
 150         } else {
 151             isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
 152         }
 153         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 154         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 155         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 156         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 157         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 158         qemu_fdt_add_subnode(fdt, intc);
 159         qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
 160         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 161         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 162         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 163         g_free(isa);
 164         g_free(intc);
 165         g_free(nodename);
 166     }
 167
 168     cells =  g_new0(uint32_t, ms->smp.cpus * 4);
 169     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 170         nodename =
 171             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 172         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 173         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 174         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 175         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 176         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 177         g_free(nodename);
 178     }
 179     nodename = g_strdup_printf("/soc/clint@%lx",
 180         (long)memmap[SIFIVE_U_CLINT].base);
 181     qemu_fdt_add_subnode(fdt, nodename);
 182     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 183     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 184         0x0, memmap[SIFIVE_U_CLINT].base,
 185         0x0, memmap[SIFIVE_U_CLINT].size);
 186     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 187         cells, ms->smp.cpus * sizeof(uint32_t) * 4);
 188     g_free(cells);
 189     g_free(nodename);
 190
 191     plic_phandle = phandle++;
 192     cells =  g_new0(uint32_t, ms->smp.cpus * 4 - 2);
 193     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 194         nodename =
 195             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 196         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 197         /* cpu 0 is the management hart that does not have S-mode */
 198         if (cpu == 0) {
 199             cells[0] = cpu_to_be32(intc_phandle);
 200             cells[1] = cpu_to_be32(IRQ_M_EXT);
 201         } else {
 202             cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
 203             cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
 204             cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 205             cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
 206         }
 207         g_free(nodename);
 208     }
 209     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 210         (long)memmap[SIFIVE_U_PLIC].base);
 211     qemu_fdt_add_subnode(fdt, nodename);
 212     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
 213     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
 214     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 215     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 216         cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
 217     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 218         0x0, memmap[SIFIVE_U_PLIC].base,
 219         0x0, memmap[SIFIVE_U_PLIC].size);
 220     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
 221     qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 222     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 223     g_free(cells);
 224     g_free(nodename);
 225
 226     ethclk_phandle = phandle++;
 227     nodename = g_strdup_printf("/soc/ethclk");
 228     qemu_fdt_add_subnode(fdt, nodename);
 229     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
 230     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
 231     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 232         SIFIVE_U_GEM_CLOCK_FREQ);
 233     qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle);
 234     ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
 235     g_free(nodename);
 236
 237     nodename = g_strdup_printf("/soc/ethernet@%lx",
 238         (long)memmap[SIFIVE_U_GEM].base);
 239     qemu_fdt_add_subnode(fdt, nodename);
 240     qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
 241     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 242         0x0, memmap[SIFIVE_U_GEM].base,
 243         0x0, memmap[SIFIVE_U_GEM].size);
 244     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 245     qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
 246     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 247     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
 248     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 249         ethclk_phandle, ethclk_phandle, ethclk_phandle);
 250     qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
 251         sizeof(ethclk_names));
 252     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
 253     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
 254     g_free(nodename);
 255
 256     nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
 257         (long)memmap[SIFIVE_U_GEM].base);
 258     qemu_fdt_add_subnode(fdt, nodename);
 259     qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
 260     g_free(nodename);
 261
 262     uartclk_phandle = phandle++;
 263     nodename = g_strdup_printf("/soc/uartclk");
 264     qemu_fdt_add_subnode(fdt, nodename);
 265     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
 266     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
 267     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
 268     qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle);
 269     uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
 270     g_free(nodename);
 271
 272     nodename = g_strdup_printf("/soc/uart@%lx",
 273         (long)memmap[SIFIVE_U_UART0].base);
 274     qemu_fdt_add_subnode(fdt, nodename);
 275     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
 276     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 277         0x0, memmap[SIFIVE_U_UART0].base,
 278         0x0, memmap[SIFIVE_U_UART0].size);
 279     qemu_fdt_setprop_cell(fdt, nodename, "clocks", uartclk_phandle);
 280     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 281     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
 282
 283     qemu_fdt_add_subnode(fdt, "/chosen");
 284     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 285     if (cmdline) {
 286         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 287     }
 288
 289     qemu_fdt_add_subnode(fdt, "/aliases");
 290     qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
 291
 292     g_free(nodename);
 293 }
 294
 295 static void riscv_sifive_u_init(MachineState *machine)
 296 {
 297     const struct MemmapEntry *memmap = sifive_u_memmap;
 298
 299     SiFiveUState *s = g_new0(SiFiveUState, 1);
 300     MemoryRegion *system_memory = get_system_memory();
 301     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 302     int i;
 303
 304     /* Initialize SoC */
 305     object_initialize_child(OBJECT(machine), "soc", &s->soc,
 306                             sizeof(s->soc), TYPE_RISCV_U_SOC,
 307                             &error_abort, NULL);
 308     object_property_set_bool(OBJECT(&s->soc), true, "realized",
 309                             &error_abort);
 310
 311     /* register RAM */
 312     memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
 313                            machine->ram_size, &error_fatal);
 314     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
 315                                 main_mem);
 316
 317     /* create device tree */
 318     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 319
 320     riscv_find_and_load_firmware(machine, BIOS_FILENAME,
 321                                  memmap[SIFIVE_U_DRAM].base);
 322
 323     if (machine->kernel_filename) {
 324         uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
 325
 326         if (machine->initrd_filename) {
 327             hwaddr start;
 328             hwaddr end = riscv_load_initrd(machine->initrd_filename,
 329                                            machine->ram_size, kernel_entry,
 330                                            &start);
 331             qemu_fdt_setprop_cell(s->fdt, "/chosen",
 332                                   "linux,initrd-start", start);
 333             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 334                                   end);
 335         }
 336     }
 337
 338     /* reset vector */
 339     uint32_t reset_vec[8] = {
 340         0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */
 341         0x02028593,                    /*     addi   a1, t0, %pcrel_lo(1b) */
 342         0xf1402573,                    /*     csrr   a0, mhartid  */
 343 #if defined(TARGET_RISCV32)
 344         0x0182a283,                    /*     lw     t0, 24(t0) */
 345 #elif defined(TARGET_RISCV64)
 346         0x0182b283,                    /*     ld     t0, 24(t0) */
 347 #endif
 348         0x00028067,                    /*     jr     t0 */
 349         0x00000000,
 350         memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
 351         0x00000000,
 352                                        /* dtb: */
 353     };
 354
 355     /* copy in the reset vector in little_endian byte order */
 356     for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 357         reset_vec[i] = cpu_to_le32(reset_vec[i]);
 358     }
 359     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 360                           memmap[SIFIVE_U_MROM].base, &address_space_memory);
 361
 362     /* copy in the device tree */
 363     if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
 364             memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
 365         error_report("not enough space to store device-tree");
 366         exit(1);
 367     }
 368     qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
 369     rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
 370                           memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
 371                           &address_space_memory);
 372 }
 373
 374 static void riscv_sifive_u_soc_init(Object *obj)
 375 {
 376     MachineState *ms = MACHINE(qdev_get_machine());
 377     SiFiveUSoCState *s = RISCV_U_SOC(obj);
 378
 379     object_initialize_child(obj, "e-cluster", &s->e_cluster,
 380                             sizeof(s->e_cluster), TYPE_CPU_CLUSTER,
 381                             &error_abort, NULL);
 382     qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
 383
 384     object_initialize_child(OBJECT(&s->e_cluster), "e-cpus",
 385                             &s->e_cpus, sizeof(s->e_cpus),
 386                             TYPE_RISCV_HART_ARRAY, &error_abort,
 387                             NULL);
 388     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
 389     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
 390     qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
 391
 392     object_initialize_child(obj, "u-cluster", &s->u_cluster,
 393                             sizeof(s->u_cluster), TYPE_CPU_CLUSTER,
 394                             &error_abort, NULL);
 395     qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
 396
 397     object_initialize_child(OBJECT(&s->u_cluster), "u-cpus",
 398                             &s->u_cpus, sizeof(s->u_cpus),
 399                             TYPE_RISCV_HART_ARRAY, &error_abort,
 400                             NULL);
 401     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
 402     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
 403     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
 404
 405     sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
 406                           TYPE_CADENCE_GEM);
 407 }
 408
 409 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
 410 {
 411     MachineState *ms = MACHINE(qdev_get_machine());
 412     SiFiveUSoCState *s = RISCV_U_SOC(dev);
 413     const struct MemmapEntry *memmap = sifive_u_memmap;
 414     MemoryRegion *system_memory = get_system_memory();
 415     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 416     qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
 417     char *plic_hart_config;
 418     size_t plic_hart_config_len;
 419     int i;
 420     Error *err = NULL;
 421     NICInfo *nd = &nd_table[0];
 422
 423     object_property_set_bool(OBJECT(&s->e_cpus), true, "realized",
 424                              &error_abort);
 425     object_property_set_bool(OBJECT(&s->u_cpus), true, "realized",
 426                              &error_abort);
 427     /*
 428      * The cluster must be realized after the RISC-V hart array container,
 429      * as the container's CPU object is only created on realize, and the
 430      * CPU must exist and have been parented into the cluster before the
 431      * cluster is realized.
 432      */
 433     object_property_set_bool(OBJECT(&s->e_cluster), true, "realized",
 434                              &error_abort);
 435     object_property_set_bool(OBJECT(&s->u_cluster), true, "realized",
 436                              &error_abort);
 437
 438     /* boot rom */
 439     memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
 440                            memmap[SIFIVE_U_MROM].size, &error_fatal);
 441     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
 442                                 mask_rom);
 443
 444     /* create PLIC hart topology configuration string */
 445     plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
 446                            ms->smp.cpus;
 447     plic_hart_config = g_malloc0(plic_hart_config_len);
 448     for (i = 0; i < ms->smp.cpus; i++) {
 449         if (i != 0) {
 450             strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
 451                     plic_hart_config_len);
 452         } else {
 453             strncat(plic_hart_config, "M", plic_hart_config_len);
 454         }
 455         plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
 456     }
 457
 458     /* MMIO */
 459     s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
 460         plic_hart_config,
 461         SIFIVE_U_PLIC_NUM_SOURCES,
 462         SIFIVE_U_PLIC_NUM_PRIORITIES,
 463         SIFIVE_U_PLIC_PRIORITY_BASE,
 464         SIFIVE_U_PLIC_PENDING_BASE,
 465         SIFIVE_U_PLIC_ENABLE_BASE,
 466         SIFIVE_U_PLIC_ENABLE_STRIDE,
 467         SIFIVE_U_PLIC_CONTEXT_BASE,
 468         SIFIVE_U_PLIC_CONTEXT_STRIDE,
 469         memmap[SIFIVE_U_PLIC].size);
 470     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
 471         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
 472     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
 473         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
 474     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
 475         memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
 476         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 477
 478     for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
 479         plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
 480     }
 481
 482     if (nd->used) {
 483         qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 484         qdev_set_nic_properties(DEVICE(&s->gem), nd);
 485     }
 486     object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
 487                             &error_abort);
 488     object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
 489     if (err) {
 490         error_propagate(errp, err);
 491         return;
 492     }
 493     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
 494     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
 495                        plic_gpios[SIFIVE_U_GEM_IRQ]);
 496 }
 497
 498 static void riscv_sifive_u_machine_init(MachineClass *mc)
 499 {
 500     mc->desc = "RISC-V Board compatible with SiFive U SDK";
 501     mc->init = riscv_sifive_u_init;
 502     mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
 503     mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
 504     mc->default_cpus = mc->min_cpus;
 505 }
 506
 507 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
 508
 509 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
 510 {
 511     DeviceClass *dc = DEVICE_CLASS(oc);
 512
 513     dc->realize = riscv_sifive_u_soc_realize;
 514     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 515     dc->user_creatable = false;
 516 }
 517
 518 static const TypeInfo riscv_sifive_u_soc_type_info = {
 519     .name = TYPE_RISCV_U_SOC,
 520     .parent = TYPE_DEVICE,
 521     .instance_size = sizeof(SiFiveUSoCState),
 522     .instance_init = riscv_sifive_u_soc_init,
 523     .class_init = riscv_sifive_u_soc_class_init,
 524 };
 525
 526 static void riscv_sifive_u_soc_register_types(void)
 527 {
 528     type_register_static(&riscv_sifive_u_soc_type_info);
 529 }
 530
 531 type_init(riscv_sifive_u_soc_register_types)