hw/riscv/spike.c

   1 /*
   2  * QEMU RISC-V Spike Board
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This provides a RISC-V Board with the following devices:
   8  *
   9  * 0) HTIF Console and Poweroff
  10  * 1) CLINT (Timer and IPI)
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms and conditions of the GNU General Public License,
  14  * version 2 or later, as published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  *
  21  * You should have received a copy of the GNU General Public License along with
  22  * this program.  If not, see <http://www.gnu.org/licenses/>.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/error-report.h"
  27 #include "qapi/error.h"
  28 #include "hw/boards.h"
  29 #include "hw/loader.h"
  30 #include "hw/sysbus.h"
  31 #include "target/riscv/cpu.h"
  32 #include "hw/riscv/riscv_hart.h"
  33 #include "hw/riscv/spike.h"
  34 #include "hw/riscv/boot.h"
  35 #include "hw/riscv/numa.h"
  36 #include "hw/char/riscv_htif.h"
  37 #include "hw/intc/riscv_aclint.h"
  38 #include "chardev/char.h"
  39 #include "sysemu/device_tree.h"
  40 #include "sysemu/sysemu.h"
  41
  42 #include <libfdt.h>
  43
  44 static const MemMapEntry spike_memmap[] = {
  45     [SPIKE_MROM] =     {     0x1000,     0xf000 },
  46     [SPIKE_HTIF] =     {  0x1000000,     0x1000 },
  47     [SPIKE_CLINT] =    {  0x2000000,    0x10000 },
  48     [SPIKE_DRAM] =     { 0x80000000,        0x0 },
  49 };
  50
  51 static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
  52                        uint64_t mem_size, const char *cmdline, bool is_32_bit)
  53 {
  54     void *fdt;
  55     uint64_t addr, size;
  56     unsigned long clint_addr;
  57     int cpu, socket;
  58     MachineState *mc = MACHINE(s);
  59     uint32_t *clint_cells;
  60     uint32_t cpu_phandle, intc_phandle, phandle = 1;
  61     char *name, *mem_name, *clint_name, *clust_name;
  62     char *core_name, *cpu_name, *intc_name;
  63     static const char * const clint_compat[2] = {
  64         "sifive,clint0", "riscv,clint0"
  65     };
  66
  67     fdt = s->fdt = create_device_tree(&s->fdt_size);
  68     if (!fdt) {
  69         error_report("create_device_tree() failed");
  70         exit(1);
  71     }
  72
  73     qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
  74     qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
  75     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
  76     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
  77
  78     qemu_fdt_add_subnode(fdt, "/htif");
  79     qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
  80     if (!htif_uses_elf_symbols()) {
  81         qemu_fdt_setprop_cells(fdt, "/htif", "reg",
  82             0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
  83     }
  84
  85     qemu_fdt_add_subnode(fdt, "/soc");
  86     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
  87     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
  88     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
  89     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
  90
  91     qemu_fdt_add_subnode(fdt, "/cpus");
  92     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
  93         RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
  94     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
  95     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
  96     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
  97
  98     for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
  99         clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
 100         qemu_fdt_add_subnode(fdt, clust_name);
 101
 102         clint_cells =  g_new0(uint32_t, s->soc[socket].num_harts * 4);
 103
 104         for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
 105             cpu_phandle = phandle++;
 106
 107             cpu_name = g_strdup_printf("/cpus/cpu@%d",
 108                 s->soc[socket].hartid_base + cpu);
 109             qemu_fdt_add_subnode(fdt, cpu_name);
 110             if (is_32_bit) {
 111                 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
 112             } else {
 113                 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
 114             }
 115             name = riscv_isa_string(&s->soc[socket].harts[cpu]);
 116             qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
 117             g_free(name);
 118             qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
 119             qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
 120             qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
 121                 s->soc[socket].hartid_base + cpu);
 122             qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
 123             riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
 124             qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
 125
 126             intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
 127             qemu_fdt_add_subnode(fdt, intc_name);
 128             intc_phandle = phandle++;
 129             qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
 130             qemu_fdt_setprop_string(fdt, intc_name, "compatible",
 131                 "riscv,cpu-intc");
 132             qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
 133             qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
 134
 135             clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 136             clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 137             clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 138             clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 139
 140             core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
 141             qemu_fdt_add_subnode(fdt, core_name);
 142             qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
 143
 144             g_free(core_name);
 145             g_free(intc_name);
 146             g_free(cpu_name);
 147         }
 148
 149         addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
 150         size = riscv_socket_mem_size(mc, socket);
 151         mem_name = g_strdup_printf("/memory@%lx", (long)addr);
 152         qemu_fdt_add_subnode(fdt, mem_name);
 153         qemu_fdt_setprop_cells(fdt, mem_name, "reg",
 154             addr >> 32, addr, size >> 32, size);
 155         qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
 156         riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
 157         g_free(mem_name);
 158
 159         clint_addr = memmap[SPIKE_CLINT].base +
 160             (memmap[SPIKE_CLINT].size * socket);
 161         clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
 162         qemu_fdt_add_subnode(fdt, clint_name);
 163         qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
 164             (char **)&clint_compat, ARRAY_SIZE(clint_compat));
 165         qemu_fdt_setprop_cells(fdt, clint_name, "reg",
 166             0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
 167         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
 168             clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
 169         riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
 170
 171         g_free(clint_name);
 172         g_free(clint_cells);
 173         g_free(clust_name);
 174     }
 175
 176     riscv_socket_fdt_write_distance_matrix(mc, fdt);
 177
 178     qemu_fdt_add_subnode(fdt, "/chosen");
 179     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
 180
 181     if (cmdline && *cmdline) {
 182         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 183     }
 184 }
 185
 186 static void spike_board_init(MachineState *machine)
 187 {
 188     const MemMapEntry *memmap = spike_memmap;
 189     SpikeState *s = SPIKE_MACHINE(machine);
 190     MemoryRegion *system_memory = get_system_memory();
 191     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 192     target_ulong firmware_end_addr, kernel_start_addr;
 193     const char *firmware_name;
 194     uint32_t fdt_load_addr;
 195     uint64_t kernel_entry;
 196     char *soc_name;
 197     int i, base_hartid, hart_count;
 198
 199     /* Check socket count limit */
 200     if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
 201         error_report("number of sockets/nodes should be less than %d",
 202             SPIKE_SOCKETS_MAX);
 203         exit(1);
 204     }
 205
 206     /* Initialize sockets */
 207     for (i = 0; i < riscv_socket_count(machine); i++) {
 208         if (!riscv_socket_check_hartids(machine, i)) {
 209             error_report("discontinuous hartids in socket%d", i);
 210             exit(1);
 211         }
 212
 213         base_hartid = riscv_socket_first_hartid(machine, i);
 214         if (base_hartid < 0) {
 215             error_report("can't find hartid base for socket%d", i);
 216             exit(1);
 217         }
 218
 219         hart_count = riscv_socket_hart_count(machine, i);
 220         if (hart_count < 0) {
 221             error_report("can't find hart count for socket%d", i);
 222             exit(1);
 223         }
 224
 225         soc_name = g_strdup_printf("soc%d", i);
 226         object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
 227                                 TYPE_RISCV_HART_ARRAY);
 228         g_free(soc_name);
 229         object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
 230                                 machine->cpu_type, &error_abort);
 231         object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
 232                                 base_hartid, &error_abort);
 233         object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
 234                                 hart_count, &error_abort);
 235         sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
 236
 237         /* Core Local Interruptor (timer and IPI) for each socket */
 238         riscv_aclint_swi_create(
 239             memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
 240             base_hartid, hart_count, false);
 241         riscv_aclint_mtimer_create(
 242             memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size +
 243                 RISCV_ACLINT_SWI_SIZE,
 244             RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
 245             RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
 246             RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
 247     }
 248
 249     /* register system main memory (actual RAM) */
 250     memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
 251         machine->ram);
 252
 253     /* boot rom */
 254     memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
 255                            memmap[SPIKE_MROM].size, &error_fatal);
 256     memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
 257                                 mask_rom);
 258
 259     firmware_name = riscv_default_firmware_name(&s->soc[0]);
 260     firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
 261                                                      memmap[SPIKE_DRAM].base,
 262                                                      htif_symbol_callback);
 263
 264     /* Load kernel */
 265     if (machine->kernel_filename) {
 266         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
 267                                                          firmware_end_addr);
 268
 269         kernel_entry = riscv_load_kernel(machine->kernel_filename,
 270                                          kernel_start_addr,
 271                                          htif_symbol_callback);
 272     } else {
 273        /*
 274         * If dynamic firmware is used, it doesn't know where is the next mode
 275         * if kernel argument is not set.
 276         */
 277         kernel_entry = 0;
 278     }
 279
 280     /* Create device tree */
 281     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
 282                riscv_is_32bit(&s->soc[0]));
 283
 284     /* Load initrd */
 285     if (machine->kernel_filename && machine->initrd_filename) {
 286         hwaddr start;
 287         hwaddr end = riscv_load_initrd(machine->initrd_filename,
 288                                        machine->ram_size, kernel_entry,
 289                                        &start);
 290         qemu_fdt_setprop_cell(s->fdt, "/chosen",
 291                               "linux,initrd-start", start);
 292         qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 293                               end);
 294     }
 295
 296     /* Compute the fdt load address in dram */
 297     fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
 298                                    machine->ram_size, s->fdt);
 299
 300     /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
 301     machine->fdt = s->fdt;
 302
 303     /* load the reset vector */
 304     riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
 305                               memmap[SPIKE_MROM].base,
 306                               memmap[SPIKE_MROM].size, kernel_entry,
 307                               fdt_load_addr);
 308
 309     /* initialize HTIF using symbols found in load_kernel */
 310     htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base);
 311 }
 312
 313 static void spike_machine_instance_init(Object *obj)
 314 {
 315 }
 316
 317 static void spike_machine_class_init(ObjectClass *oc, void *data)
 318 {
 319     MachineClass *mc = MACHINE_CLASS(oc);
 320
 321     mc->desc = "RISC-V Spike board";
 322     mc->init = spike_board_init;
 323     mc->max_cpus = SPIKE_CPUS_MAX;
 324     mc->is_default = true;
 325     mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
 326     mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
 327     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
 328     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
 329     mc->numa_mem_supported = true;
 330     mc->default_ram_id = "riscv.spike.ram";
 331 }
 332
 333 static const TypeInfo spike_machine_typeinfo = {
 334     .name       = MACHINE_TYPE_NAME("spike"),
 335     .parent     = TYPE_MACHINE,
 336     .class_init = spike_machine_class_init,
 337     .instance_init = spike_machine_instance_init,
 338     .instance_size = sizeof(SpikeState),
 339 };
 340
 341 static void spike_machine_init_register_types(void)
 342 {
 343     type_register_static(&spike_machine_typeinfo);
 344 }
 345
 346 type_init(spike_machine_init_register_types)