hw/riscv/virt-acpi-build.c

   1 /*
   2  * Support for generating ACPI tables and passing them to Guests
   3  *
   4  * RISC-V virt ACPI generation
   5  *
   6  * Copyright (C) 2008-2010  Kevin O'Connor <kevin@koconnor.net>
   7  * Copyright (C) 2006 Fabrice Bellard
   8  * Copyright (C) 2013 Red Hat Inc
   9  * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
  10  * Copyright (C) 2021-2023 Ventana Micro Systems Inc
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21
  22  * You should have received a copy of the GNU General Public License along
  23  * with this program; if not, see <http://www.gnu.org/licenses/>.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/acpi/acpi-defs.h"
  28 #include "hw/acpi/acpi.h"
  29 #include "hw/acpi/aml-build.h"
  30 #include "hw/acpi/utils.h"
  31 #include "hw/nvram/fw_cfg_acpi.h"
  32 #include "qapi/error.h"
  33 #include "qemu/error-report.h"
  34 #include "sysemu/reset.h"
  35 #include "migration/vmstate.h"
  36 #include "hw/riscv/virt.h"
  37 #include "hw/riscv/numa.h"
  38 #include "hw/intc/riscv_aclint.h"
  39
  40 #define ACPI_BUILD_TABLE_SIZE             0x20000
  41 #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
  42
  43 typedef struct AcpiBuildState {
  44     /* Copy of table in RAM (for patching) */
  45     MemoryRegion *table_mr;
  46     MemoryRegion *rsdp_mr;
  47     MemoryRegion *linker_mr;
  48     /* Is table patched? */
  49     bool patched;
  50 } AcpiBuildState;
  51
  52 static void acpi_align_size(GArray *blob, unsigned align)
  53 {
  54     /*
  55      * Align size to multiple of given size. This reduces the chance
  56      * we need to change size in the future (breaking cross version migration).
  57      */
  58     g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
  59 }
  60
  61 static void riscv_acpi_madt_add_rintc(uint32_t uid,
  62                                       const CPUArchIdList *arch_ids,
  63                                       GArray *entry,
  64                                       RISCVVirtState *s)
  65 {
  66     uint8_t  guest_index_bits = imsic_num_bits(s->aia_guests + 1);
  67     uint64_t hart_id = arch_ids->cpus[uid].arch_id;
  68     uint32_t imsic_size, local_cpu_id, socket_id;
  69     uint64_t imsic_socket_addr, imsic_addr;
  70     MachineState *ms = MACHINE(s);
  71
  72     socket_id = arch_ids->cpus[uid].props.node_id;
  73     local_cpu_id = (arch_ids->cpus[uid].arch_id -
  74                     riscv_socket_first_hartid(ms, socket_id)) %
  75                     riscv_socket_hart_count(ms, socket_id);
  76     imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base +
  77                         (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE);
  78     imsic_size = IMSIC_HART_SIZE(guest_index_bits);
  79     imsic_addr = imsic_socket_addr + local_cpu_id * imsic_size;
  80     build_append_int_noprefix(entry, 0x18, 1);       /* Type     */
  81     build_append_int_noprefix(entry, 36, 1);         /* Length   */
  82     build_append_int_noprefix(entry, 1, 1);          /* Version  */
  83     build_append_int_noprefix(entry, 0, 1);          /* Reserved */
  84     build_append_int_noprefix(entry, 0x1, 4);        /* Flags    */
  85     build_append_int_noprefix(entry, hart_id, 8);    /* Hart ID  */
  86     build_append_int_noprefix(entry, uid, 4);        /* ACPI Processor UID */
  87     /* External Interrupt Controller ID */
  88     if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
  89         build_append_int_noprefix(entry,
  90                                   ACPI_BUILD_INTC_ID(
  91                                       arch_ids->cpus[uid].props.node_id,
  92                                       local_cpu_id),
  93                                   4);
  94     } else {
  95         build_append_int_noprefix(entry, 0, 4);
  96     }
  97
  98     if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
  99         /* IMSIC Base address */
 100         build_append_int_noprefix(entry, imsic_addr, 8);
 101         /* IMSIC Size */
 102         build_append_int_noprefix(entry, imsic_size, 4);
 103     } else {
 104         build_append_int_noprefix(entry, 0, 8);
 105         build_append_int_noprefix(entry, 0, 4);
 106     }
 107 }
 108
 109 static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
 110 {
 111     MachineClass *mc = MACHINE_GET_CLASS(s);
 112     MachineState *ms = MACHINE(s);
 113     const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
 114
 115     for (int i = 0; i < arch_ids->len; i++) {
 116             Aml *dev;
 117             GArray *madt_buf = g_array_new(0, 1, 1);
 118
 119             dev = aml_device("C%.03X", i);
 120             aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
 121             aml_append(dev, aml_name_decl("_UID",
 122                        aml_int(arch_ids->cpus[i].arch_id)));
 123
 124             /* build _MAT object */
 125             riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf, s);
 126             aml_append(dev, aml_name_decl("_MAT",
 127                                           aml_buffer(madt_buf->len,
 128                                           (uint8_t *)madt_buf->data)));
 129             g_array_free(madt_buf, true);
 130
 131             aml_append(scope, dev);
 132     }
 133 }
 134
 135 /* RHCT Node[N] starts at offset 56 */
 136 #define RHCT_NODE_ARRAY_OFFSET 56
 137
 138 /*
 139  * ACPI spec, Revision 6.5+
 140  * 5.2.36 RISC-V Hart Capabilities Table (RHCT)
 141  * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16
 142  *      https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
 143  *      https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view
 144  */
 145 static void build_rhct(GArray *table_data,
 146                        BIOSLinker *linker,
 147                        RISCVVirtState *s)
 148 {
 149     MachineClass *mc = MACHINE_GET_CLASS(s);
 150     MachineState *ms = MACHINE(s);
 151     const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
 152     size_t len, aligned_len;
 153     uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
 154     RISCVCPU *cpu = &s->soc[0].harts[0];
 155     uint32_t mmu_offset = 0;
 156     uint8_t satp_mode_max;
 157     char *isa;
 158
 159     AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
 160                         .oem_table_id = s->oem_table_id };
 161
 162     acpi_table_begin(&table, table_data);
 163
 164     build_append_int_noprefix(table_data, 0x0, 4);   /* Reserved */
 165
 166     /* Time Base Frequency */
 167     build_append_int_noprefix(table_data,
 168                               RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, 8);
 169
 170     /* ISA + N hart info */
 171     num_rhct_nodes = 1 + ms->smp.cpus;
 172     if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
 173         num_rhct_nodes++;
 174     }
 175
 176     if (cpu->cfg.satp_mode.supported != 0) {
 177         num_rhct_nodes++;
 178     }
 179
 180     /* Number of RHCT nodes*/
 181     build_append_int_noprefix(table_data, num_rhct_nodes, 4);
 182
 183     /* Offset to the RHCT node array */
 184     build_append_int_noprefix(table_data, RHCT_NODE_ARRAY_OFFSET, 4);
 185
 186     /* ISA String Node */
 187     isa_offset = table_data->len - table.table_offset;
 188     build_append_int_noprefix(table_data, 0, 2);   /* Type 0 */
 189
 190     isa = riscv_isa_string(cpu);
 191     len = 8 + strlen(isa) + 1;
 192     aligned_len = (len % 2) ? (len + 1) : len;
 193
 194     build_append_int_noprefix(table_data, aligned_len, 2);   /* Length */
 195     build_append_int_noprefix(table_data, 0x1, 2);           /* Revision */
 196
 197     /* ISA string length including NUL */
 198     build_append_int_noprefix(table_data, strlen(isa) + 1, 2);
 199     g_array_append_vals(table_data, isa, strlen(isa) + 1);   /* ISA string */
 200
 201     if (aligned_len != len) {
 202         build_append_int_noprefix(table_data, 0x0, 1);   /* Optional Padding */
 203     }
 204
 205     /* CMO node */
 206     if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
 207         cmo_offset = table_data->len - table.table_offset;
 208         build_append_int_noprefix(table_data, 1, 2);    /* Type */
 209         build_append_int_noprefix(table_data, 10, 2);   /* Length */
 210         build_append_int_noprefix(table_data, 0x1, 2);  /* Revision */
 211         build_append_int_noprefix(table_data, 0, 1);    /* Reserved */
 212
 213         /* CBOM block size */
 214         if (cpu->cfg.cbom_blocksize) {
 215             build_append_int_noprefix(table_data,
 216                                       __builtin_ctz(cpu->cfg.cbom_blocksize),
 217                                       1);
 218         } else {
 219             build_append_int_noprefix(table_data, 0, 1);
 220         }
 221
 222         /* CBOP block size */
 223         build_append_int_noprefix(table_data, 0, 1);
 224
 225         /* CBOZ block size */
 226         if (cpu->cfg.cboz_blocksize) {
 227             build_append_int_noprefix(table_data,
 228                                       __builtin_ctz(cpu->cfg.cboz_blocksize),
 229                                       1);
 230         } else {
 231             build_append_int_noprefix(table_data, 0, 1);
 232         }
 233     }
 234
 235     /* MMU node structure */
 236     if (cpu->cfg.satp_mode.supported != 0) {
 237         satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
 238         mmu_offset = table_data->len - table.table_offset;
 239         build_append_int_noprefix(table_data, 2, 2);    /* Type */
 240         build_append_int_noprefix(table_data, 8, 2);    /* Length */
 241         build_append_int_noprefix(table_data, 0x1, 2);  /* Revision */
 242         build_append_int_noprefix(table_data, 0, 1);    /* Reserved */
 243         /* MMU Type */
 244         if (satp_mode_max == VM_1_10_SV57) {
 245             build_append_int_noprefix(table_data, 2, 1);    /* Sv57 */
 246         } else if (satp_mode_max == VM_1_10_SV48) {
 247             build_append_int_noprefix(table_data, 1, 1);    /* Sv48 */
 248         } else if (satp_mode_max == VM_1_10_SV39) {
 249             build_append_int_noprefix(table_data, 0, 1);    /* Sv39 */
 250         } else {
 251             assert(1);
 252         }
 253     }
 254
 255     /* Hart Info Node */
 256     for (int i = 0; i < arch_ids->len; i++) {
 257         len = 16;
 258         int num_offsets = 1;
 259         build_append_int_noprefix(table_data, 0xFFFF, 2);  /* Type */
 260
 261         /* Length */
 262         if (cmo_offset) {
 263             len += 4;
 264             num_offsets++;
 265         }
 266
 267         if (mmu_offset) {
 268             len += 4;
 269             num_offsets++;
 270         }
 271
 272         build_append_int_noprefix(table_data, len, 2);
 273         build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
 274         /* Number of offsets */
 275         build_append_int_noprefix(table_data, num_offsets, 2);
 276         build_append_int_noprefix(table_data, i, 4);   /* ACPI Processor UID */
 277         /* Offsets */
 278         build_append_int_noprefix(table_data, isa_offset, 4);
 279         if (cmo_offset) {
 280             build_append_int_noprefix(table_data, cmo_offset, 4);
 281         }
 282
 283         if (mmu_offset) {
 284             build_append_int_noprefix(table_data, mmu_offset, 4);
 285         }
 286     }
 287
 288     acpi_table_end(linker, &table);
 289 }
 290
 291 /* FADT */
 292 static void build_fadt_rev6(GArray *table_data,
 293                             BIOSLinker *linker,
 294                             RISCVVirtState *s,
 295                             unsigned dsdt_tbl_offset)
 296 {
 297     AcpiFadtData fadt = {
 298         .rev = 6,
 299         .minor_ver = 5,
 300         .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
 301         .xdsdt_tbl_offset = &dsdt_tbl_offset,
 302     };
 303
 304     build_fadt(table_data, linker, &fadt, s->oem_id, s->oem_table_id);
 305 }
 306
 307 /* DSDT */
 308 static void build_dsdt(GArray *table_data,
 309                        BIOSLinker *linker,
 310                        RISCVVirtState *s)
 311 {
 312     Aml *scope, *dsdt;
 313     const MemMapEntry *memmap = s->memmap;
 314     AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id,
 315                         .oem_table_id = s->oem_table_id };
 316
 317
 318     acpi_table_begin(&table, table_data);
 319     dsdt = init_aml_allocator();
 320
 321     /*
 322      * When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
 323      * While UEFI can use libfdt to disable the RTC device node in the DTB that
 324      * it passes to the OS, it cannot modify AML. Therefore, we won't generate
 325      * the RTC ACPI device at all when using UEFI.
 326      */
 327     scope = aml_scope("\\_SB");
 328     acpi_dsdt_add_cpus(scope, s);
 329
 330     fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
 331
 332     aml_append(dsdt, scope);
 333
 334     /* copy AML table into ACPI tables blob and patch header there */
 335     g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
 336
 337     acpi_table_end(linker, &table);
 338     free_aml_allocator();
 339 }
 340
 341 /*
 342  * ACPI spec, Revision 6.5+
 343  * 5.2.12 Multiple APIC Description Table (MADT)
 344  * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15
 345  *      https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
 346  *      https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view
 347  */
 348 static void build_madt(GArray *table_data,
 349                        BIOSLinker *linker,
 350                        RISCVVirtState *s)
 351 {
 352     MachineClass *mc = MACHINE_GET_CLASS(s);
 353     MachineState *ms = MACHINE(s);
 354     const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
 355     uint8_t  group_index_bits = imsic_num_bits(riscv_socket_count(ms));
 356     uint8_t  guest_index_bits = imsic_num_bits(s->aia_guests + 1);
 357     uint16_t imsic_max_hart_per_socket = 0;
 358     uint8_t  hart_index_bits;
 359     uint64_t aplic_addr;
 360     uint32_t gsi_base;
 361     uint8_t  socket;
 362
 363     for (socket = 0; socket < riscv_socket_count(ms); socket++) {
 364         if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
 365             imsic_max_hart_per_socket = s->soc[socket].num_harts;
 366         }
 367     }
 368
 369     hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket);
 370
 371     AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id,
 372                         .oem_table_id = s->oem_table_id };
 373
 374     acpi_table_begin(&table, table_data);
 375     /* Local Interrupt Controller Address */
 376     build_append_int_noprefix(table_data, 0, 4);
 377     build_append_int_noprefix(table_data, 0, 4);   /* MADT Flags */
 378
 379     /* RISC-V Local INTC structures per HART */
 380     for (int i = 0; i < arch_ids->len; i++) {
 381         riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s);
 382     }
 383
 384     /* IMSIC */
 385     if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
 386         /* IMSIC */
 387         build_append_int_noprefix(table_data, 0x19, 1);     /* Type */
 388         build_append_int_noprefix(table_data, 16, 1);       /* Length */
 389         build_append_int_noprefix(table_data, 1, 1);        /* Version */
 390         build_append_int_noprefix(table_data, 0, 1);        /* Reserved */
 391         build_append_int_noprefix(table_data, 0, 4);        /* Flags */
 392         /* Number of supervisor mode Interrupt Identities */
 393         build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
 394         /* Number of guest mode Interrupt Identities */
 395         build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
 396         /* Guest Index Bits */
 397         build_append_int_noprefix(table_data, guest_index_bits, 1);
 398         /* Hart Index Bits */
 399         build_append_int_noprefix(table_data, hart_index_bits, 1);
 400         /* Group Index Bits */
 401         build_append_int_noprefix(table_data, group_index_bits, 1);
 402         /* Group Index Shift */
 403         build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1);
 404     }
 405
 406     if (s->aia_type != VIRT_AIA_TYPE_NONE) {
 407         /* APLICs */
 408         for (socket = 0; socket < riscv_socket_count(ms); socket++) {
 409             aplic_addr = s->memmap[VIRT_APLIC_S].base +
 410                              s->memmap[VIRT_APLIC_S].size * socket;
 411             gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
 412             build_append_int_noprefix(table_data, 0x1A, 1);    /* Type */
 413             build_append_int_noprefix(table_data, 36, 1);      /* Length */
 414             build_append_int_noprefix(table_data, 1, 1);       /* Version */
 415             build_append_int_noprefix(table_data, socket, 1);  /* APLIC ID */
 416             build_append_int_noprefix(table_data, 0, 4);       /* Flags */
 417             build_append_int_noprefix(table_data, 0, 8);       /* Hardware ID */
 418             /* Number of IDCs */
 419             if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
 420                 build_append_int_noprefix(table_data,
 421                                           s->soc[socket].num_harts,
 422                                           2);
 423             } else {
 424                 build_append_int_noprefix(table_data, 0, 2);
 425             }
 426             /* Total External Interrupt Sources Supported */
 427             build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_SOURCES, 2);
 428             /* Global System Interrupt Base */
 429             build_append_int_noprefix(table_data, gsi_base, 4);
 430             /* APLIC Address */
 431             build_append_int_noprefix(table_data, aplic_addr, 8);
 432             /* APLIC size */
 433             build_append_int_noprefix(table_data,
 434                                       s->memmap[VIRT_APLIC_S].size, 4);
 435         }
 436     }
 437
 438     acpi_table_end(linker, &table);
 439 }
 440
 441 static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
 442 {
 443     GArray *table_offsets;
 444     unsigned dsdt, xsdt;
 445     GArray *tables_blob = tables->table_data;
 446
 447     table_offsets = g_array_new(false, true,
 448                                 sizeof(uint32_t));
 449
 450     bios_linker_loader_alloc(tables->linker,
 451                              ACPI_BUILD_TABLE_FILE, tables_blob,
 452                              64, false);
 453
 454     /* DSDT is pointed to by FADT */
 455     dsdt = tables_blob->len;
 456     build_dsdt(tables_blob, tables->linker, s);
 457
 458     /* FADT and others pointed to by XSDT */
 459     acpi_add_table(table_offsets, tables_blob);
 460     build_fadt_rev6(tables_blob, tables->linker, s, dsdt);
 461
 462     acpi_add_table(table_offsets, tables_blob);
 463     build_madt(tables_blob, tables->linker, s);
 464
 465     acpi_add_table(table_offsets, tables_blob);
 466     build_rhct(tables_blob, tables->linker, s);
 467
 468     /* XSDT is pointed to by RSDP */
 469     xsdt = tables_blob->len;
 470     build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,
 471                 s->oem_table_id);
 472
 473     /* RSDP is in FSEG memory, so allocate it separately */
 474     {
 475         AcpiRsdpData rsdp_data = {
 476             .revision = 2,
 477             .oem_id = s->oem_id,
 478             .xsdt_tbl_offset = &xsdt,
 479             .rsdt_tbl_offset = NULL,
 480         };
 481         build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
 482     }
 483
 484     /*
 485      * The align size is 128, warn if 64k is not enough therefore
 486      * the align size could be resized.
 487      */
 488     if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
 489         warn_report("ACPI table size %u exceeds %d bytes,"
 490                     " migration may not work",
 491                     tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
 492         error_printf("Try removing some objects.");
 493     }
 494
 495     acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
 496
 497     /* Clean up memory that's no longer used */
 498     g_array_free(table_offsets, true);
 499 }
 500
 501 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
 502 {
 503     uint32_t size = acpi_data_len(data);
 504
 505     /*
 506      * Make sure RAM size is correct - in case it got changed
 507      * e.g. by migration
 508      */
 509     memory_region_ram_resize(mr, size, &error_abort);
 510
 511     memcpy(memory_region_get_ram_ptr(mr), data->data, size);
 512     memory_region_set_dirty(mr, 0, size);
 513 }
 514
 515 static void virt_acpi_build_update(void *build_opaque)
 516 {
 517     AcpiBuildState *build_state = build_opaque;
 518     AcpiBuildTables tables;
 519
 520     /* No state to update or already patched? Nothing to do. */
 521     if (!build_state || build_state->patched) {
 522         return;
 523     }
 524
 525     build_state->patched = true;
 526
 527     acpi_build_tables_init(&tables);
 528
 529     virt_acpi_build(RISCV_VIRT_MACHINE(qdev_get_machine()), &tables);
 530
 531     acpi_ram_update(build_state->table_mr, tables.table_data);
 532     acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
 533     acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
 534
 535     acpi_build_tables_cleanup(&tables, true);
 536 }
 537
 538 static void virt_acpi_build_reset(void *build_opaque)
 539 {
 540     AcpiBuildState *build_state = build_opaque;
 541     build_state->patched = false;
 542 }
 543
 544 static const VMStateDescription vmstate_virt_acpi_build = {
 545     .name = "virt_acpi_build",
 546     .version_id = 1,
 547     .minimum_version_id = 1,
 548     .fields = (const VMStateField[]) {
 549         VMSTATE_BOOL(patched, AcpiBuildState),
 550         VMSTATE_END_OF_LIST()
 551     },
 552 };
 553
 554 void virt_acpi_setup(RISCVVirtState *s)
 555 {
 556     AcpiBuildTables tables;
 557     AcpiBuildState *build_state;
 558
 559     build_state = g_malloc0(sizeof *build_state);
 560
 561     acpi_build_tables_init(&tables);
 562     virt_acpi_build(s, &tables);
 563
 564     /* Now expose it all to Guest */
 565     build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,
 566                                               build_state, tables.table_data,
 567                                               ACPI_BUILD_TABLE_FILE);
 568     assert(build_state->table_mr != NULL);
 569
 570     build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update,
 571                                                build_state,
 572                                                tables.linker->cmd_blob,
 573                                                ACPI_BUILD_LOADER_FILE);
 574
 575     build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
 576                                              build_state, tables.rsdp,
 577                                              ACPI_BUILD_RSDP_FILE);
 578
 579     qemu_register_reset(virt_acpi_build_reset, build_state);
 580     virt_acpi_build_reset(build_state);
 581     vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
 582
 583     /*
 584      * Clean up tables but don't free the memory: we track it
 585      * in build_state.
 586      */
 587     acpi_build_tables_cleanup(&tables, false);
 588 }