2 * QEMU RISC-V VirtIO Board
4 * Copyright (c) 2017 SiFive, Inc.
6 * RISC-V machine with 16550a UART and VirtIO MMIO
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
25 #include "hw/boards.h"
26 #include "hw/loader.h"
27 #include "hw/sysbus.h"
28 #include "hw/qdev-properties.h"
29 #include "hw/char/serial.h"
30 #include "target/riscv/cpu.h"
31 #include "hw/riscv/riscv_hart.h"
32 #include "hw/riscv/virt.h"
33 #include "hw/riscv/boot.h"
34 #include "hw/riscv/numa.h"
35 #include "hw/intc/riscv_aclint.h"
36 #include "hw/intc/sifive_plic.h"
37 #include "hw/misc/sifive_test.h"
38 #include "chardev/char.h"
39 #include "sysemu/device_tree.h"
40 #include "sysemu/sysemu.h"
41 #include "sysemu/kvm.h"
42 #include "hw/pci/pci.h"
43 #include "hw/pci-host/gpex.h"
44 #include "hw/display/ramfb.h"
46 static const MemMapEntry virt_memmap
[] = {
47 [VIRT_DEBUG
] = { 0x0, 0x100 },
48 [VIRT_MROM
] = { 0x1000, 0xf000 },
49 [VIRT_TEST
] = { 0x100000, 0x1000 },
50 [VIRT_RTC
] = { 0x101000, 0x1000 },
51 [VIRT_CLINT
] = { 0x2000000, 0x10000 },
52 [VIRT_ACLINT_SSWI
] = { 0x2F00000, 0x4000 },
53 [VIRT_PCIE_PIO
] = { 0x3000000, 0x10000 },
54 [VIRT_PLIC
] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX
* 2) },
55 [VIRT_UART0
] = { 0x10000000, 0x100 },
56 [VIRT_VIRTIO
] = { 0x10001000, 0x1000 },
57 [VIRT_FW_CFG
] = { 0x10100000, 0x18 },
58 [VIRT_FLASH
] = { 0x20000000, 0x4000000 },
59 [VIRT_PCIE_ECAM
] = { 0x30000000, 0x10000000 },
60 [VIRT_PCIE_MMIO
] = { 0x40000000, 0x40000000 },
61 [VIRT_DRAM
] = { 0x80000000, 0x0 },
64 /* PCIe high mmio is fixed for RV32 */
65 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
66 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
68 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
69 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
71 static MemMapEntry virt_high_pcie_memmap
;
73 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
75 static PFlashCFI01
*virt_flash_create1(RISCVVirtState
*s
,
77 const char *alias_prop_name
)
80 * Create a single flash device. We use the same parameters as
81 * the flash devices on the ARM virt board.
83 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
85 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
86 qdev_prop_set_uint8(dev
, "width", 4);
87 qdev_prop_set_uint8(dev
, "device-width", 2);
88 qdev_prop_set_bit(dev
, "big-endian", false);
89 qdev_prop_set_uint16(dev
, "id0", 0x89);
90 qdev_prop_set_uint16(dev
, "id1", 0x18);
91 qdev_prop_set_uint16(dev
, "id2", 0x00);
92 qdev_prop_set_uint16(dev
, "id3", 0x00);
93 qdev_prop_set_string(dev
, "name", name
);
95 object_property_add_child(OBJECT(s
), name
, OBJECT(dev
));
96 object_property_add_alias(OBJECT(s
), alias_prop_name
,
97 OBJECT(dev
), "drive");
99 return PFLASH_CFI01(dev
);
102 static void virt_flash_create(RISCVVirtState
*s
)
104 s
->flash
[0] = virt_flash_create1(s
, "virt.flash0", "pflash0");
105 s
->flash
[1] = virt_flash_create1(s
, "virt.flash1", "pflash1");
108 static void virt_flash_map1(PFlashCFI01
*flash
,
109 hwaddr base
, hwaddr size
,
110 MemoryRegion
*sysmem
)
112 DeviceState
*dev
= DEVICE(flash
);
114 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
115 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
116 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
117 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
119 memory_region_add_subregion(sysmem
, base
,
120 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
124 static void virt_flash_map(RISCVVirtState
*s
,
125 MemoryRegion
*sysmem
)
127 hwaddr flashsize
= virt_memmap
[VIRT_FLASH
].size
/ 2;
128 hwaddr flashbase
= virt_memmap
[VIRT_FLASH
].base
;
130 virt_flash_map1(s
->flash
[0], flashbase
, flashsize
,
132 virt_flash_map1(s
->flash
[1], flashbase
+ flashsize
, flashsize
,
136 static void create_pcie_irq_map(void *fdt
, char *nodename
,
137 uint32_t plic_phandle
)
141 full_irq_map
[GPEX_NUM_IRQS
* GPEX_NUM_IRQS
* FDT_INT_MAP_WIDTH
] = {};
142 uint32_t *irq_map
= full_irq_map
;
144 /* This code creates a standard swizzle of interrupts such that
145 * each device's first interrupt is based on it's PCI_SLOT number.
146 * (See pci_swizzle_map_irq_fn())
148 * We only need one entry per interrupt in the table (not one per
149 * possible slot) seeing the interrupt-map-mask will allow the table
150 * to wrap to any number of devices.
152 for (dev
= 0; dev
< GPEX_NUM_IRQS
; dev
++) {
153 int devfn
= dev
* 0x8;
155 for (pin
= 0; pin
< GPEX_NUM_IRQS
; pin
++) {
156 int irq_nr
= PCIE_IRQ
+ ((pin
+ PCI_SLOT(devfn
)) % GPEX_NUM_IRQS
);
159 irq_map
[i
] = cpu_to_be32(devfn
<< 8);
161 i
+= FDT_PCI_ADDR_CELLS
;
162 irq_map
[i
] = cpu_to_be32(pin
+ 1);
164 i
+= FDT_PCI_INT_CELLS
;
165 irq_map
[i
++] = cpu_to_be32(plic_phandle
);
167 i
+= FDT_PLIC_ADDR_CELLS
;
168 irq_map
[i
] = cpu_to_be32(irq_nr
);
170 irq_map
+= FDT_INT_MAP_WIDTH
;
174 qemu_fdt_setprop(fdt
, nodename
, "interrupt-map",
175 full_irq_map
, sizeof(full_irq_map
));
177 qemu_fdt_setprop_cells(fdt
, nodename
, "interrupt-map-mask",
181 static void create_fdt_socket_cpus(RISCVVirtState
*s
, int socket
,
182 char *clust_name
, uint32_t *phandle
,
183 bool is_32_bit
, uint32_t *intc_phandles
)
186 uint32_t cpu_phandle
;
187 MachineState
*mc
= MACHINE(s
);
188 char *name
, *cpu_name
, *core_name
, *intc_name
;
190 for (cpu
= s
->soc
[socket
].num_harts
- 1; cpu
>= 0; cpu
--) {
191 cpu_phandle
= (*phandle
)++;
193 cpu_name
= g_strdup_printf("/cpus/cpu@%d",
194 s
->soc
[socket
].hartid_base
+ cpu
);
195 qemu_fdt_add_subnode(mc
->fdt
, cpu_name
);
196 qemu_fdt_setprop_string(mc
->fdt
, cpu_name
, "mmu-type",
197 (is_32_bit
) ? "riscv,sv32" : "riscv,sv48");
198 name
= riscv_isa_string(&s
->soc
[socket
].harts
[cpu
]);
199 qemu_fdt_setprop_string(mc
->fdt
, cpu_name
, "riscv,isa", name
);
201 qemu_fdt_setprop_string(mc
->fdt
, cpu_name
, "compatible", "riscv");
202 qemu_fdt_setprop_string(mc
->fdt
, cpu_name
, "status", "okay");
203 qemu_fdt_setprop_cell(mc
->fdt
, cpu_name
, "reg",
204 s
->soc
[socket
].hartid_base
+ cpu
);
205 qemu_fdt_setprop_string(mc
->fdt
, cpu_name
, "device_type", "cpu");
206 riscv_socket_fdt_write_id(mc
, mc
->fdt
, cpu_name
, socket
);
207 qemu_fdt_setprop_cell(mc
->fdt
, cpu_name
, "phandle", cpu_phandle
);
209 intc_phandles
[cpu
] = (*phandle
)++;
211 intc_name
= g_strdup_printf("%s/interrupt-controller", cpu_name
);
212 qemu_fdt_add_subnode(mc
->fdt
, intc_name
);
213 qemu_fdt_setprop_cell(mc
->fdt
, intc_name
, "phandle",
215 qemu_fdt_setprop_string(mc
->fdt
, intc_name
, "compatible",
217 qemu_fdt_setprop(mc
->fdt
, intc_name
, "interrupt-controller", NULL
, 0);
218 qemu_fdt_setprop_cell(mc
->fdt
, intc_name
, "#interrupt-cells", 1);
220 core_name
= g_strdup_printf("%s/core%d", clust_name
, cpu
);
221 qemu_fdt_add_subnode(mc
->fdt
, core_name
);
222 qemu_fdt_setprop_cell(mc
->fdt
, core_name
, "cpu", cpu_phandle
);
230 static void create_fdt_socket_memory(RISCVVirtState
*s
,
231 const MemMapEntry
*memmap
, int socket
)
235 MachineState
*mc
= MACHINE(s
);
237 addr
= memmap
[VIRT_DRAM
].base
+ riscv_socket_mem_offset(mc
, socket
);
238 size
= riscv_socket_mem_size(mc
, socket
);
239 mem_name
= g_strdup_printf("/memory@%lx", (long)addr
);
240 qemu_fdt_add_subnode(mc
->fdt
, mem_name
);
241 qemu_fdt_setprop_cells(mc
->fdt
, mem_name
, "reg",
242 addr
>> 32, addr
, size
>> 32, size
);
243 qemu_fdt_setprop_string(mc
->fdt
, mem_name
, "device_type", "memory");
244 riscv_socket_fdt_write_id(mc
, mc
->fdt
, mem_name
, socket
);
248 static void create_fdt_socket_clint(RISCVVirtState
*s
,
249 const MemMapEntry
*memmap
, int socket
,
250 uint32_t *intc_phandles
)
254 uint32_t *clint_cells
;
255 unsigned long clint_addr
;
256 MachineState
*mc
= MACHINE(s
);
257 static const char * const clint_compat
[2] = {
258 "sifive,clint0", "riscv,clint0"
261 clint_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 4);
263 for (cpu
= 0; cpu
< s
->soc
[socket
].num_harts
; cpu
++) {
264 clint_cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
265 clint_cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_SOFT
);
266 clint_cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandles
[cpu
]);
267 clint_cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_M_TIMER
);
270 clint_addr
= memmap
[VIRT_CLINT
].base
+ (memmap
[VIRT_CLINT
].size
* socket
);
271 clint_name
= g_strdup_printf("/soc/clint@%lx", clint_addr
);
272 qemu_fdt_add_subnode(mc
->fdt
, clint_name
);
273 qemu_fdt_setprop_string_array(mc
->fdt
, clint_name
, "compatible",
274 (char **)&clint_compat
,
275 ARRAY_SIZE(clint_compat
));
276 qemu_fdt_setprop_cells(mc
->fdt
, clint_name
, "reg",
277 0x0, clint_addr
, 0x0, memmap
[VIRT_CLINT
].size
);
278 qemu_fdt_setprop(mc
->fdt
, clint_name
, "interrupts-extended",
279 clint_cells
, s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 4);
280 riscv_socket_fdt_write_id(mc
, mc
->fdt
, clint_name
, socket
);
286 static void create_fdt_socket_aclint(RISCVVirtState
*s
,
287 const MemMapEntry
*memmap
, int socket
,
288 uint32_t *intc_phandles
)
293 uint32_t aclint_cells_size
;
294 uint32_t *aclint_mswi_cells
;
295 uint32_t *aclint_sswi_cells
;
296 uint32_t *aclint_mtimer_cells
;
297 MachineState
*mc
= MACHINE(s
);
299 aclint_mswi_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
300 aclint_mtimer_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
301 aclint_sswi_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
303 for (cpu
= 0; cpu
< s
->soc
[socket
].num_harts
; cpu
++) {
304 aclint_mswi_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
305 aclint_mswi_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_M_SOFT
);
306 aclint_mtimer_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
307 aclint_mtimer_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_M_TIMER
);
308 aclint_sswi_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
309 aclint_sswi_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_S_SOFT
);
311 aclint_cells_size
= s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 2;
313 addr
= memmap
[VIRT_CLINT
].base
+ (memmap
[VIRT_CLINT
].size
* socket
);
314 name
= g_strdup_printf("/soc/mswi@%lx", addr
);
315 qemu_fdt_add_subnode(mc
->fdt
, name
);
316 qemu_fdt_setprop_string(mc
->fdt
, name
, "compatible", "riscv,aclint-mswi");
317 qemu_fdt_setprop_cells(mc
->fdt
, name
, "reg",
318 0x0, addr
, 0x0, RISCV_ACLINT_SWI_SIZE
);
319 qemu_fdt_setprop(mc
->fdt
, name
, "interrupts-extended",
320 aclint_mswi_cells
, aclint_cells_size
);
321 qemu_fdt_setprop(mc
->fdt
, name
, "interrupt-controller", NULL
, 0);
322 qemu_fdt_setprop_cell(mc
->fdt
, name
, "#interrupt-cells", 0);
323 riscv_socket_fdt_write_id(mc
, mc
->fdt
, name
, socket
);
326 addr
= memmap
[VIRT_CLINT
].base
+ RISCV_ACLINT_SWI_SIZE
+
327 (memmap
[VIRT_CLINT
].size
* socket
);
328 name
= g_strdup_printf("/soc/mtimer@%lx", addr
);
329 qemu_fdt_add_subnode(mc
->fdt
, name
);
330 qemu_fdt_setprop_string(mc
->fdt
, name
, "compatible",
331 "riscv,aclint-mtimer");
332 qemu_fdt_setprop_cells(mc
->fdt
, name
, "reg",
333 0x0, addr
+ RISCV_ACLINT_DEFAULT_MTIME
,
334 0x0, memmap
[VIRT_CLINT
].size
- RISCV_ACLINT_SWI_SIZE
-
335 RISCV_ACLINT_DEFAULT_MTIME
,
336 0x0, addr
+ RISCV_ACLINT_DEFAULT_MTIMECMP
,
337 0x0, RISCV_ACLINT_DEFAULT_MTIME
);
338 qemu_fdt_setprop(mc
->fdt
, name
, "interrupts-extended",
339 aclint_mtimer_cells
, aclint_cells_size
);
340 riscv_socket_fdt_write_id(mc
, mc
->fdt
, name
, socket
);
343 addr
= memmap
[VIRT_ACLINT_SSWI
].base
+
344 (memmap
[VIRT_ACLINT_SSWI
].size
* socket
);
345 name
= g_strdup_printf("/soc/sswi@%lx", addr
);
346 qemu_fdt_add_subnode(mc
->fdt
, name
);
347 qemu_fdt_setprop_string(mc
->fdt
, name
, "compatible", "riscv,aclint-sswi");
348 qemu_fdt_setprop_cells(mc
->fdt
, name
, "reg",
349 0x0, addr
, 0x0, memmap
[VIRT_ACLINT_SSWI
].size
);
350 qemu_fdt_setprop(mc
->fdt
, name
, "interrupts-extended",
351 aclint_sswi_cells
, aclint_cells_size
);
352 qemu_fdt_setprop(mc
->fdt
, name
, "interrupt-controller", NULL
, 0);
353 qemu_fdt_setprop_cell(mc
->fdt
, name
, "#interrupt-cells", 0);
354 riscv_socket_fdt_write_id(mc
, mc
->fdt
, name
, socket
);
357 g_free(aclint_mswi_cells
);
358 g_free(aclint_mtimer_cells
);
359 g_free(aclint_sswi_cells
);
362 static void create_fdt_socket_plic(RISCVVirtState
*s
,
363 const MemMapEntry
*memmap
, int socket
,
364 uint32_t *phandle
, uint32_t *intc_phandles
,
365 uint32_t *plic_phandles
)
369 uint32_t *plic_cells
;
370 unsigned long plic_addr
;
371 MachineState
*mc
= MACHINE(s
);
372 static const char * const plic_compat
[2] = {
373 "sifive,plic-1.0.0", "riscv,plic0"
377 plic_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
379 plic_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 4);
382 for (cpu
= 0; cpu
< s
->soc
[socket
].num_harts
; cpu
++) {
384 plic_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
385 plic_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_S_EXT
);
387 plic_cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
388 plic_cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_EXT
);
389 plic_cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandles
[cpu
]);
390 plic_cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_S_EXT
);
394 plic_phandles
[socket
] = (*phandle
)++;
395 plic_addr
= memmap
[VIRT_PLIC
].base
+ (memmap
[VIRT_PLIC
].size
* socket
);
396 plic_name
= g_strdup_printf("/soc/plic@%lx", plic_addr
);
397 qemu_fdt_add_subnode(mc
->fdt
, plic_name
);
398 qemu_fdt_setprop_cell(mc
->fdt
, plic_name
,
399 "#address-cells", FDT_PLIC_ADDR_CELLS
);
400 qemu_fdt_setprop_cell(mc
->fdt
, plic_name
,
401 "#interrupt-cells", FDT_PLIC_INT_CELLS
);
402 qemu_fdt_setprop_string_array(mc
->fdt
, plic_name
, "compatible",
403 (char **)&plic_compat
,
404 ARRAY_SIZE(plic_compat
));
405 qemu_fdt_setprop(mc
->fdt
, plic_name
, "interrupt-controller", NULL
, 0);
406 qemu_fdt_setprop(mc
->fdt
, plic_name
, "interrupts-extended",
407 plic_cells
, s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 4);
408 qemu_fdt_setprop_cells(mc
->fdt
, plic_name
, "reg",
409 0x0, plic_addr
, 0x0, memmap
[VIRT_PLIC
].size
);
410 qemu_fdt_setprop_cell(mc
->fdt
, plic_name
, "riscv,ndev", VIRTIO_NDEV
);
411 riscv_socket_fdt_write_id(mc
, mc
->fdt
, plic_name
, socket
);
412 qemu_fdt_setprop_cell(mc
->fdt
, plic_name
, "phandle",
413 plic_phandles
[socket
]);
419 static void create_fdt_sockets(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
420 bool is_32_bit
, uint32_t *phandle
,
421 uint32_t *irq_mmio_phandle
,
422 uint32_t *irq_pcie_phandle
,
423 uint32_t *irq_virtio_phandle
)
427 uint32_t *intc_phandles
;
428 MachineState
*mc
= MACHINE(s
);
429 uint32_t xplic_phandles
[MAX_NODES
];
431 qemu_fdt_add_subnode(mc
->fdt
, "/cpus");
432 qemu_fdt_setprop_cell(mc
->fdt
, "/cpus", "timebase-frequency",
433 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ
);
434 qemu_fdt_setprop_cell(mc
->fdt
, "/cpus", "#size-cells", 0x0);
435 qemu_fdt_setprop_cell(mc
->fdt
, "/cpus", "#address-cells", 0x1);
436 qemu_fdt_add_subnode(mc
->fdt
, "/cpus/cpu-map");
438 for (socket
= (riscv_socket_count(mc
) - 1); socket
>= 0; socket
--) {
439 clust_name
= g_strdup_printf("/cpus/cpu-map/cluster%d", socket
);
440 qemu_fdt_add_subnode(mc
->fdt
, clust_name
);
442 intc_phandles
= g_new0(uint32_t, s
->soc
[socket
].num_harts
);
444 create_fdt_socket_cpus(s
, socket
, clust_name
, phandle
,
445 is_32_bit
, intc_phandles
);
447 create_fdt_socket_memory(s
, memmap
, socket
);
449 if (!kvm_enabled()) {
450 if (s
->have_aclint
) {
451 create_fdt_socket_aclint(s
, memmap
, socket
, intc_phandles
);
453 create_fdt_socket_clint(s
, memmap
, socket
, intc_phandles
);
457 create_fdt_socket_plic(s
, memmap
, socket
, phandle
,
458 intc_phandles
, xplic_phandles
);
460 g_free(intc_phandles
);
464 for (socket
= 0; socket
< riscv_socket_count(mc
); socket
++) {
466 *irq_mmio_phandle
= xplic_phandles
[socket
];
467 *irq_virtio_phandle
= xplic_phandles
[socket
];
468 *irq_pcie_phandle
= xplic_phandles
[socket
];
471 *irq_virtio_phandle
= xplic_phandles
[socket
];
472 *irq_pcie_phandle
= xplic_phandles
[socket
];
475 *irq_pcie_phandle
= xplic_phandles
[socket
];
479 riscv_socket_fdt_write_distance_matrix(mc
, mc
->fdt
);
482 static void create_fdt_virtio(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
483 uint32_t irq_virtio_phandle
)
487 MachineState
*mc
= MACHINE(s
);
489 for (i
= 0; i
< VIRTIO_COUNT
; i
++) {
490 name
= g_strdup_printf("/soc/virtio_mmio@%lx",
491 (long)(memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
));
492 qemu_fdt_add_subnode(mc
->fdt
, name
);
493 qemu_fdt_setprop_string(mc
->fdt
, name
, "compatible", "virtio,mmio");
494 qemu_fdt_setprop_cells(mc
->fdt
, name
, "reg",
495 0x0, memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
,
496 0x0, memmap
[VIRT_VIRTIO
].size
);
497 qemu_fdt_setprop_cell(mc
->fdt
, name
, "interrupt-parent",
499 qemu_fdt_setprop_cell(mc
->fdt
, name
, "interrupts", VIRTIO_IRQ
+ i
);
504 static void create_fdt_pcie(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
505 uint32_t irq_pcie_phandle
)
508 MachineState
*mc
= MACHINE(s
);
510 name
= g_strdup_printf("/soc/pci@%lx",
511 (long) memmap
[VIRT_PCIE_ECAM
].base
);
512 qemu_fdt_add_subnode(mc
->fdt
, name
);
513 qemu_fdt_setprop_cell(mc
->fdt
, name
, "#address-cells",
515 qemu_fdt_setprop_cell(mc
->fdt
, name
, "#interrupt-cells",
517 qemu_fdt_setprop_cell(mc
->fdt
, name
, "#size-cells", 0x2);
518 qemu_fdt_setprop_string(mc
->fdt
, name
, "compatible",
519 "pci-host-ecam-generic");
520 qemu_fdt_setprop_string(mc
->fdt
, name
, "device_type", "pci");
521 qemu_fdt_setprop_cell(mc
->fdt
, name
, "linux,pci-domain", 0);
522 qemu_fdt_setprop_cells(mc
->fdt
, name
, "bus-range", 0,
523 memmap
[VIRT_PCIE_ECAM
].size
/ PCIE_MMCFG_SIZE_MIN
- 1);
524 qemu_fdt_setprop(mc
->fdt
, name
, "dma-coherent", NULL
, 0);
525 qemu_fdt_setprop_cells(mc
->fdt
, name
, "reg", 0,
526 memmap
[VIRT_PCIE_ECAM
].base
, 0, memmap
[VIRT_PCIE_ECAM
].size
);
527 qemu_fdt_setprop_sized_cells(mc
->fdt
, name
, "ranges",
528 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
529 2, memmap
[VIRT_PCIE_PIO
].base
, 2, memmap
[VIRT_PCIE_PIO
].size
,
530 1, FDT_PCI_RANGE_MMIO
,
531 2, memmap
[VIRT_PCIE_MMIO
].base
,
532 2, memmap
[VIRT_PCIE_MMIO
].base
, 2, memmap
[VIRT_PCIE_MMIO
].size
,
533 1, FDT_PCI_RANGE_MMIO_64BIT
,
534 2, virt_high_pcie_memmap
.base
,
535 2, virt_high_pcie_memmap
.base
, 2, virt_high_pcie_memmap
.size
);
537 create_pcie_irq_map(mc
->fdt
, name
, irq_pcie_phandle
);
541 static void create_fdt_reset(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
545 uint32_t test_phandle
;
546 MachineState
*mc
= MACHINE(s
);
548 test_phandle
= (*phandle
)++;
549 name
= g_strdup_printf("/soc/test@%lx",
550 (long)memmap
[VIRT_TEST
].base
);
551 qemu_fdt_add_subnode(mc
->fdt
, name
);
553 static const char * const compat
[3] = {
554 "sifive,test1", "sifive,test0", "syscon"
556 qemu_fdt_setprop_string_array(mc
->fdt
, name
, "compatible",
557 (char **)&compat
, ARRAY_SIZE(compat
));
559 qemu_fdt_setprop_cells(mc
->fdt
, name
, "reg",
560 0x0, memmap
[VIRT_TEST
].base
, 0x0, memmap
[VIRT_TEST
].size
);
561 qemu_fdt_setprop_cell(mc
->fdt
, name
, "phandle", test_phandle
);
562 test_phandle
= qemu_fdt_get_phandle(mc
->fdt
, name
);
565 name
= g_strdup_printf("/soc/reboot");
566 qemu_fdt_add_subnode(mc
->fdt
, name
);
567 qemu_fdt_setprop_string(mc
->fdt
, name
, "compatible", "syscon-reboot");
568 qemu_fdt_setprop_cell(mc
->fdt
, name
, "regmap", test_phandle
);
569 qemu_fdt_setprop_cell(mc
->fdt
, name
, "offset", 0x0);
570 qemu_fdt_setprop_cell(mc
->fdt
, name
, "value", FINISHER_RESET
);
573 name
= g_strdup_printf("/soc/poweroff");
574 qemu_fdt_add_subnode(mc
->fdt
, name
);
575 qemu_fdt_setprop_string(mc
->fdt
, name
, "compatible", "syscon-poweroff");
576 qemu_fdt_setprop_cell(mc
->fdt
, name
, "regmap", test_phandle
);
577 qemu_fdt_setprop_cell(mc
->fdt
, name
, "offset", 0x0);
578 qemu_fdt_setprop_cell(mc
->fdt
, name
, "value", FINISHER_PASS
);
582 static void create_fdt_uart(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
583 uint32_t irq_mmio_phandle
)
586 MachineState
*mc
= MACHINE(s
);
588 name
= g_strdup_printf("/soc/uart@%lx", (long)memmap
[VIRT_UART0
].base
);
589 qemu_fdt_add_subnode(mc
->fdt
, name
);
590 qemu_fdt_setprop_string(mc
->fdt
, name
, "compatible", "ns16550a");
591 qemu_fdt_setprop_cells(mc
->fdt
, name
, "reg",
592 0x0, memmap
[VIRT_UART0
].base
,
593 0x0, memmap
[VIRT_UART0
].size
);
594 qemu_fdt_setprop_cell(mc
->fdt
, name
, "clock-frequency", 3686400);
595 qemu_fdt_setprop_cell(mc
->fdt
, name
, "interrupt-parent", irq_mmio_phandle
);
596 qemu_fdt_setprop_cell(mc
->fdt
, name
, "interrupts", UART0_IRQ
);
598 qemu_fdt_add_subnode(mc
->fdt
, "/chosen");
599 qemu_fdt_setprop_string(mc
->fdt
, "/chosen", "stdout-path", name
);
603 static void create_fdt_rtc(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
604 uint32_t irq_mmio_phandle
)
607 MachineState
*mc
= MACHINE(s
);
609 name
= g_strdup_printf("/soc/rtc@%lx", (long)memmap
[VIRT_RTC
].base
);
610 qemu_fdt_add_subnode(mc
->fdt
, name
);
611 qemu_fdt_setprop_string(mc
->fdt
, name
, "compatible",
612 "google,goldfish-rtc");
613 qemu_fdt_setprop_cells(mc
->fdt
, name
, "reg",
614 0x0, memmap
[VIRT_RTC
].base
, 0x0, memmap
[VIRT_RTC
].size
);
615 qemu_fdt_setprop_cell(mc
->fdt
, name
, "interrupt-parent",
617 qemu_fdt_setprop_cell(mc
->fdt
, name
, "interrupts", RTC_IRQ
);
621 static void create_fdt_flash(RISCVVirtState
*s
, const MemMapEntry
*memmap
)
624 MachineState
*mc
= MACHINE(s
);
625 hwaddr flashsize
= virt_memmap
[VIRT_FLASH
].size
/ 2;
626 hwaddr flashbase
= virt_memmap
[VIRT_FLASH
].base
;
628 name
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
629 qemu_fdt_add_subnode(mc
->fdt
, name
);
630 qemu_fdt_setprop_string(mc
->fdt
, name
, "compatible", "cfi-flash");
631 qemu_fdt_setprop_sized_cells(mc
->fdt
, name
, "reg",
632 2, flashbase
, 2, flashsize
,
633 2, flashbase
+ flashsize
, 2, flashsize
);
634 qemu_fdt_setprop_cell(mc
->fdt
, name
, "bank-width", 4);
638 static void create_fdt(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
639 uint64_t mem_size
, const char *cmdline
, bool is_32_bit
)
641 MachineState
*mc
= MACHINE(s
);
642 uint32_t phandle
= 1, irq_mmio_phandle
= 1;
643 uint32_t irq_pcie_phandle
= 1, irq_virtio_phandle
= 1;
646 mc
->fdt
= load_device_tree(mc
->dtb
, &s
->fdt_size
);
648 error_report("load_device_tree() failed");
651 goto update_bootargs
;
653 mc
->fdt
= create_device_tree(&s
->fdt_size
);
655 error_report("create_device_tree() failed");
660 qemu_fdt_setprop_string(mc
->fdt
, "/", "model", "riscv-virtio,qemu");
661 qemu_fdt_setprop_string(mc
->fdt
, "/", "compatible", "riscv-virtio");
662 qemu_fdt_setprop_cell(mc
->fdt
, "/", "#size-cells", 0x2);
663 qemu_fdt_setprop_cell(mc
->fdt
, "/", "#address-cells", 0x2);
665 qemu_fdt_add_subnode(mc
->fdt
, "/soc");
666 qemu_fdt_setprop(mc
->fdt
, "/soc", "ranges", NULL
, 0);
667 qemu_fdt_setprop_string(mc
->fdt
, "/soc", "compatible", "simple-bus");
668 qemu_fdt_setprop_cell(mc
->fdt
, "/soc", "#size-cells", 0x2);
669 qemu_fdt_setprop_cell(mc
->fdt
, "/soc", "#address-cells", 0x2);
671 create_fdt_sockets(s
, memmap
, is_32_bit
, &phandle
,
672 &irq_mmio_phandle
, &irq_pcie_phandle
, &irq_virtio_phandle
);
674 create_fdt_virtio(s
, memmap
, irq_virtio_phandle
);
676 create_fdt_pcie(s
, memmap
, irq_pcie_phandle
);
678 create_fdt_reset(s
, memmap
, &phandle
);
680 create_fdt_uart(s
, memmap
, irq_mmio_phandle
);
682 create_fdt_rtc(s
, memmap
, irq_mmio_phandle
);
684 create_fdt_flash(s
, memmap
);
688 qemu_fdt_setprop_string(mc
->fdt
, "/chosen", "bootargs", cmdline
);
692 static inline DeviceState
*gpex_pcie_init(MemoryRegion
*sys_mem
,
693 hwaddr ecam_base
, hwaddr ecam_size
,
694 hwaddr mmio_base
, hwaddr mmio_size
,
695 hwaddr high_mmio_base
,
696 hwaddr high_mmio_size
,
701 MemoryRegion
*ecam_alias
, *ecam_reg
;
702 MemoryRegion
*mmio_alias
, *high_mmio_alias
, *mmio_reg
;
706 dev
= qdev_new(TYPE_GPEX_HOST
);
708 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
710 ecam_alias
= g_new0(MemoryRegion
, 1);
711 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
712 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
713 ecam_reg
, 0, ecam_size
);
714 memory_region_add_subregion(get_system_memory(), ecam_base
, ecam_alias
);
716 mmio_alias
= g_new0(MemoryRegion
, 1);
717 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
718 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
719 mmio_reg
, mmio_base
, mmio_size
);
720 memory_region_add_subregion(get_system_memory(), mmio_base
, mmio_alias
);
722 /* Map high MMIO space */
723 high_mmio_alias
= g_new0(MemoryRegion
, 1);
724 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
725 mmio_reg
, high_mmio_base
, high_mmio_size
);
726 memory_region_add_subregion(get_system_memory(), high_mmio_base
,
729 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, pio_base
);
731 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
732 irq
= qdev_get_gpio_in(plic
, PCIE_IRQ
+ i
);
734 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, irq
);
735 gpex_set_irq_num(GPEX_HOST(dev
), i
, PCIE_IRQ
+ i
);
741 static FWCfgState
*create_fw_cfg(const MachineState
*mc
)
743 hwaddr base
= virt_memmap
[VIRT_FW_CFG
].base
;
744 hwaddr size
= virt_memmap
[VIRT_FW_CFG
].size
;
748 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16,
749 &address_space_memory
);
750 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)mc
->smp
.cpus
);
752 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
753 qemu_fdt_add_subnode(mc
->fdt
, nodename
);
754 qemu_fdt_setprop_string(mc
->fdt
, nodename
,
755 "compatible", "qemu,fw-cfg-mmio");
756 qemu_fdt_setprop_sized_cells(mc
->fdt
, nodename
, "reg",
758 qemu_fdt_setprop(mc
->fdt
, nodename
, "dma-coherent", NULL
, 0);
763 static void virt_machine_init(MachineState
*machine
)
765 const MemMapEntry
*memmap
= virt_memmap
;
766 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(machine
);
767 MemoryRegion
*system_memory
= get_system_memory();
768 MemoryRegion
*mask_rom
= g_new(MemoryRegion
, 1);
769 char *plic_hart_config
, *soc_name
;
770 target_ulong start_addr
= memmap
[VIRT_DRAM
].base
;
771 target_ulong firmware_end_addr
, kernel_start_addr
;
772 uint32_t fdt_load_addr
;
773 uint64_t kernel_entry
;
774 DeviceState
*mmio_plic
, *virtio_plic
, *pcie_plic
;
775 int i
, base_hartid
, hart_count
;
777 /* Check socket count limit */
778 if (VIRT_SOCKETS_MAX
< riscv_socket_count(machine
)) {
779 error_report("number of sockets/nodes should be less than %d",
784 /* Initialize sockets */
785 mmio_plic
= virtio_plic
= pcie_plic
= NULL
;
786 for (i
= 0; i
< riscv_socket_count(machine
); i
++) {
787 if (!riscv_socket_check_hartids(machine
, i
)) {
788 error_report("discontinuous hartids in socket%d", i
);
792 base_hartid
= riscv_socket_first_hartid(machine
, i
);
793 if (base_hartid
< 0) {
794 error_report("can't find hartid base for socket%d", i
);
798 hart_count
= riscv_socket_hart_count(machine
, i
);
799 if (hart_count
< 0) {
800 error_report("can't find hart count for socket%d", i
);
804 soc_name
= g_strdup_printf("soc%d", i
);
805 object_initialize_child(OBJECT(machine
), soc_name
, &s
->soc
[i
],
806 TYPE_RISCV_HART_ARRAY
);
808 object_property_set_str(OBJECT(&s
->soc
[i
]), "cpu-type",
809 machine
->cpu_type
, &error_abort
);
810 object_property_set_int(OBJECT(&s
->soc
[i
]), "hartid-base",
811 base_hartid
, &error_abort
);
812 object_property_set_int(OBJECT(&s
->soc
[i
]), "num-harts",
813 hart_count
, &error_abort
);
814 sysbus_realize(SYS_BUS_DEVICE(&s
->soc
[i
]), &error_abort
);
816 if (!kvm_enabled()) {
817 /* Per-socket CLINT */
818 riscv_aclint_swi_create(
819 memmap
[VIRT_CLINT
].base
+ i
* memmap
[VIRT_CLINT
].size
,
820 base_hartid
, hart_count
, false);
821 riscv_aclint_mtimer_create(
822 memmap
[VIRT_CLINT
].base
+ i
* memmap
[VIRT_CLINT
].size
+
823 RISCV_ACLINT_SWI_SIZE
,
824 RISCV_ACLINT_DEFAULT_MTIMER_SIZE
, base_hartid
, hart_count
,
825 RISCV_ACLINT_DEFAULT_MTIMECMP
, RISCV_ACLINT_DEFAULT_MTIME
,
826 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ
, true);
828 /* Per-socket ACLINT SSWI */
829 if (s
->have_aclint
) {
830 riscv_aclint_swi_create(
831 memmap
[VIRT_ACLINT_SSWI
].base
+
832 i
* memmap
[VIRT_ACLINT_SSWI
].size
,
833 base_hartid
, hart_count
, true);
837 /* Per-socket PLIC hart topology configuration string */
838 plic_hart_config
= riscv_plic_hart_config_string(hart_count
);
840 /* Per-socket PLIC */
841 s
->plic
[i
] = sifive_plic_create(
842 memmap
[VIRT_PLIC
].base
+ i
* memmap
[VIRT_PLIC
].size
,
843 plic_hart_config
, hart_count
, base_hartid
,
844 VIRT_PLIC_NUM_SOURCES
,
845 VIRT_PLIC_NUM_PRIORITIES
,
846 VIRT_PLIC_PRIORITY_BASE
,
847 VIRT_PLIC_PENDING_BASE
,
848 VIRT_PLIC_ENABLE_BASE
,
849 VIRT_PLIC_ENABLE_STRIDE
,
850 VIRT_PLIC_CONTEXT_BASE
,
851 VIRT_PLIC_CONTEXT_STRIDE
,
852 memmap
[VIRT_PLIC
].size
);
853 g_free(plic_hart_config
);
855 /* Try to use different PLIC instance based device type */
857 mmio_plic
= s
->plic
[i
];
858 virtio_plic
= s
->plic
[i
];
859 pcie_plic
= s
->plic
[i
];
862 virtio_plic
= s
->plic
[i
];
863 pcie_plic
= s
->plic
[i
];
866 pcie_plic
= s
->plic
[i
];
870 if (riscv_is_32bit(&s
->soc
[0])) {
871 #if HOST_LONG_BITS == 64
872 /* limit RAM size in a 32-bit system */
873 if (machine
->ram_size
> 10 * GiB
) {
874 machine
->ram_size
= 10 * GiB
;
875 error_report("Limiting RAM size to 10 GiB");
878 virt_high_pcie_memmap
.base
= VIRT32_HIGH_PCIE_MMIO_BASE
;
879 virt_high_pcie_memmap
.size
= VIRT32_HIGH_PCIE_MMIO_SIZE
;
881 virt_high_pcie_memmap
.size
= VIRT64_HIGH_PCIE_MMIO_SIZE
;
882 virt_high_pcie_memmap
.base
= memmap
[VIRT_DRAM
].base
+ machine
->ram_size
;
883 virt_high_pcie_memmap
.base
=
884 ROUND_UP(virt_high_pcie_memmap
.base
, virt_high_pcie_memmap
.size
);
887 /* register system main memory (actual RAM) */
888 memory_region_add_subregion(system_memory
, memmap
[VIRT_DRAM
].base
,
891 /* create device tree */
892 create_fdt(s
, memmap
, machine
->ram_size
, machine
->kernel_cmdline
,
893 riscv_is_32bit(&s
->soc
[0]));
896 memory_region_init_rom(mask_rom
, NULL
, "riscv_virt_board.mrom",
897 memmap
[VIRT_MROM
].size
, &error_fatal
);
898 memory_region_add_subregion(system_memory
, memmap
[VIRT_MROM
].base
,
902 * Only direct boot kernel is currently supported for KVM VM,
903 * so the "-bios" parameter is ignored and treated like "-bios none"
904 * when KVM is enabled.
907 g_free(machine
->firmware
);
908 machine
->firmware
= g_strdup("none");
911 if (riscv_is_32bit(&s
->soc
[0])) {
912 firmware_end_addr
= riscv_find_and_load_firmware(machine
,
913 RISCV32_BIOS_BIN
, start_addr
, NULL
);
915 firmware_end_addr
= riscv_find_and_load_firmware(machine
,
916 RISCV64_BIOS_BIN
, start_addr
, NULL
);
919 if (machine
->kernel_filename
) {
920 kernel_start_addr
= riscv_calc_kernel_start_addr(&s
->soc
[0],
923 kernel_entry
= riscv_load_kernel(machine
->kernel_filename
,
924 kernel_start_addr
, NULL
);
926 if (machine
->initrd_filename
) {
928 hwaddr end
= riscv_load_initrd(machine
->initrd_filename
,
929 machine
->ram_size
, kernel_entry
,
931 qemu_fdt_setprop_cell(machine
->fdt
, "/chosen",
932 "linux,initrd-start", start
);
933 qemu_fdt_setprop_cell(machine
->fdt
, "/chosen", "linux,initrd-end",
938 * If dynamic firmware is used, it doesn't know where is the next mode
939 * if kernel argument is not set.
944 if (drive_get(IF_PFLASH
, 0, 0)) {
946 * Pflash was supplied, let's overwrite the address we jump to after
947 * reset to the base of the flash.
949 start_addr
= virt_memmap
[VIRT_FLASH
].base
;
953 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
954 * tree cannot be altered and we get FDT_ERR_NOSPACE.
956 s
->fw_cfg
= create_fw_cfg(machine
);
957 rom_set_fw(s
->fw_cfg
);
959 /* Compute the fdt load address in dram */
960 fdt_load_addr
= riscv_load_fdt(memmap
[VIRT_DRAM
].base
,
961 machine
->ram_size
, machine
->fdt
);
962 /* load the reset vector */
963 riscv_setup_rom_reset_vec(machine
, &s
->soc
[0], start_addr
,
964 virt_memmap
[VIRT_MROM
].base
,
965 virt_memmap
[VIRT_MROM
].size
, kernel_entry
,
966 fdt_load_addr
, machine
->fdt
);
969 * Only direct boot kernel is currently supported for KVM VM,
970 * So here setup kernel start address and fdt address.
971 * TODO:Support firmware loading and integrate to TCG start
974 riscv_setup_direct_kernel(kernel_entry
, fdt_load_addr
);
977 /* SiFive Test MMIO device */
978 sifive_test_create(memmap
[VIRT_TEST
].base
);
980 /* VirtIO MMIO devices */
981 for (i
= 0; i
< VIRTIO_COUNT
; i
++) {
982 sysbus_create_simple("virtio-mmio",
983 memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
,
984 qdev_get_gpio_in(DEVICE(virtio_plic
), VIRTIO_IRQ
+ i
));
987 gpex_pcie_init(system_memory
,
988 memmap
[VIRT_PCIE_ECAM
].base
,
989 memmap
[VIRT_PCIE_ECAM
].size
,
990 memmap
[VIRT_PCIE_MMIO
].base
,
991 memmap
[VIRT_PCIE_MMIO
].size
,
992 virt_high_pcie_memmap
.base
,
993 virt_high_pcie_memmap
.size
,
994 memmap
[VIRT_PCIE_PIO
].base
,
997 serial_mm_init(system_memory
, memmap
[VIRT_UART0
].base
,
998 0, qdev_get_gpio_in(DEVICE(mmio_plic
), UART0_IRQ
), 399193,
999 serial_hd(0), DEVICE_LITTLE_ENDIAN
);
1001 sysbus_create_simple("goldfish_rtc", memmap
[VIRT_RTC
].base
,
1002 qdev_get_gpio_in(DEVICE(mmio_plic
), RTC_IRQ
));
1004 virt_flash_create(s
);
1006 for (i
= 0; i
< ARRAY_SIZE(s
->flash
); i
++) {
1007 /* Map legacy -drive if=pflash to machine properties */
1008 pflash_cfi01_legacy_drive(s
->flash
[i
],
1009 drive_get(IF_PFLASH
, 0, i
));
1011 virt_flash_map(s
, system_memory
);
1014 static void virt_machine_instance_init(Object
*obj
)
1018 static bool virt_get_aclint(Object
*obj
, Error
**errp
)
1020 MachineState
*ms
= MACHINE(obj
);
1021 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(ms
);
1023 return s
->have_aclint
;
1026 static void virt_set_aclint(Object
*obj
, bool value
, Error
**errp
)
1028 MachineState
*ms
= MACHINE(obj
);
1029 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(ms
);
1031 s
->have_aclint
= value
;
1034 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1036 MachineClass
*mc
= MACHINE_CLASS(oc
);
1038 mc
->desc
= "RISC-V VirtIO board";
1039 mc
->init
= virt_machine_init
;
1040 mc
->max_cpus
= VIRT_CPUS_MAX
;
1041 mc
->default_cpu_type
= TYPE_RISCV_CPU_BASE
;
1042 mc
->pci_allow_0_address
= true;
1043 mc
->possible_cpu_arch_ids
= riscv_numa_possible_cpu_arch_ids
;
1044 mc
->cpu_index_to_instance_props
= riscv_numa_cpu_index_to_props
;
1045 mc
->get_default_cpu_node_id
= riscv_numa_get_default_cpu_node_id
;
1046 mc
->numa_mem_supported
= true;
1047 mc
->default_ram_id
= "riscv_virt_board.ram";
1049 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
1051 object_class_property_add_bool(oc
, "aclint", virt_get_aclint
,
1053 object_class_property_set_description(oc
, "aclint",
1054 "Set on/off to enable/disable "
1055 "emulating ACLINT devices");
1058 static const TypeInfo virt_machine_typeinfo
= {
1059 .name
= MACHINE_TYPE_NAME("virt"),
1060 .parent
= TYPE_MACHINE
,
1061 .class_init
= virt_machine_class_init
,
1062 .instance_init
= virt_machine_instance_init
,
1063 .instance_size
= sizeof(RISCVVirtState
),
1066 static void virt_machine_init_register_types(void)
1068 type_register_static(&virt_machine_typeinfo
);
1071 type_init(virt_machine_init_register_types
)