2 * QEMU RISC-V VirtIO Board
4 * Copyright (c) 2017 SiFive, Inc.
6 * RISC-V machine with 16550a UART and VirtIO MMIO
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
25 #include "qapi/error.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/sysbus.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial.h"
31 #include "target/riscv/cpu.h"
32 #include "hw/core/sysbus-fdt.h"
33 #include "target/riscv/pmu.h"
34 #include "hw/riscv/riscv_hart.h"
35 #include "hw/riscv/virt.h"
36 #include "hw/riscv/boot.h"
37 #include "hw/riscv/numa.h"
38 #include "hw/intc/riscv_aclint.h"
39 #include "hw/intc/riscv_aplic.h"
40 #include "hw/intc/riscv_imsic.h"
41 #include "hw/intc/sifive_plic.h"
42 #include "hw/misc/sifive_test.h"
43 #include "hw/platform-bus.h"
44 #include "chardev/char.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/sysemu.h"
47 #include "sysemu/kvm.h"
48 #include "sysemu/tpm.h"
49 #include "hw/pci/pci.h"
50 #include "hw/pci-host/gpex.h"
51 #include "hw/display/ramfb.h"
54 * The virt machine physical address space used by some of the devices
55 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
56 * number of CPUs, and number of IMSIC guest files.
58 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
59 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
60 * of virt machine physical address space.
63 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
64 #if VIRT_IMSIC_GROUP_MAX_SIZE < \
65 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
66 #error "Can't accomodate single IMSIC group in address space"
69 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \
70 VIRT_IMSIC_GROUP_MAX_SIZE)
71 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE
72 #error "Can't accomodate all IMSIC groups in address space"
75 static const MemMapEntry virt_memmap
[] = {
76 [VIRT_DEBUG
] = { 0x0, 0x100 },
77 [VIRT_MROM
] = { 0x1000, 0xf000 },
78 [VIRT_TEST
] = { 0x100000, 0x1000 },
79 [VIRT_RTC
] = { 0x101000, 0x1000 },
80 [VIRT_CLINT
] = { 0x2000000, 0x10000 },
81 [VIRT_ACLINT_SSWI
] = { 0x2F00000, 0x4000 },
82 [VIRT_PCIE_PIO
] = { 0x3000000, 0x10000 },
83 [VIRT_PLATFORM_BUS
] = { 0x4000000, 0x2000000 },
84 [VIRT_PLIC
] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX
* 2) },
85 [VIRT_APLIC_M
] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX
) },
86 [VIRT_APLIC_S
] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX
) },
87 [VIRT_UART0
] = { 0x10000000, 0x100 },
88 [VIRT_VIRTIO
] = { 0x10001000, 0x1000 },
89 [VIRT_FW_CFG
] = { 0x10100000, 0x18 },
90 [VIRT_FLASH
] = { 0x20000000, 0x4000000 },
91 [VIRT_IMSIC_M
] = { 0x24000000, VIRT_IMSIC_MAX_SIZE
},
92 [VIRT_IMSIC_S
] = { 0x28000000, VIRT_IMSIC_MAX_SIZE
},
93 [VIRT_PCIE_ECAM
] = { 0x30000000, 0x10000000 },
94 [VIRT_PCIE_MMIO
] = { 0x40000000, 0x40000000 },
95 [VIRT_DRAM
] = { 0x80000000, 0x0 },
98 /* PCIe high mmio is fixed for RV32 */
99 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
100 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
102 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
103 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
105 static MemMapEntry virt_high_pcie_memmap
;
107 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
109 static PFlashCFI01
*virt_flash_create1(RISCVVirtState
*s
,
111 const char *alias_prop_name
)
114 * Create a single flash device. We use the same parameters as
115 * the flash devices on the ARM virt board.
117 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
119 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
120 qdev_prop_set_uint8(dev
, "width", 4);
121 qdev_prop_set_uint8(dev
, "device-width", 2);
122 qdev_prop_set_bit(dev
, "big-endian", false);
123 qdev_prop_set_uint16(dev
, "id0", 0x89);
124 qdev_prop_set_uint16(dev
, "id1", 0x18);
125 qdev_prop_set_uint16(dev
, "id2", 0x00);
126 qdev_prop_set_uint16(dev
, "id3", 0x00);
127 qdev_prop_set_string(dev
, "name", name
);
129 object_property_add_child(OBJECT(s
), name
, OBJECT(dev
));
130 object_property_add_alias(OBJECT(s
), alias_prop_name
,
131 OBJECT(dev
), "drive");
133 return PFLASH_CFI01(dev
);
136 static void virt_flash_create(RISCVVirtState
*s
)
138 s
->flash
[0] = virt_flash_create1(s
, "virt.flash0", "pflash0");
139 s
->flash
[1] = virt_flash_create1(s
, "virt.flash1", "pflash1");
142 static void virt_flash_map1(PFlashCFI01
*flash
,
143 hwaddr base
, hwaddr size
,
144 MemoryRegion
*sysmem
)
146 DeviceState
*dev
= DEVICE(flash
);
148 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
149 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
150 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
151 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
153 memory_region_add_subregion(sysmem
, base
,
154 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
158 static void virt_flash_map(RISCVVirtState
*s
,
159 MemoryRegion
*sysmem
)
161 hwaddr flashsize
= virt_memmap
[VIRT_FLASH
].size
/ 2;
162 hwaddr flashbase
= virt_memmap
[VIRT_FLASH
].base
;
164 virt_flash_map1(s
->flash
[0], flashbase
, flashsize
,
166 virt_flash_map1(s
->flash
[1], flashbase
+ flashsize
, flashsize
,
170 static void create_pcie_irq_map(RISCVVirtState
*s
, void *fdt
, char *nodename
,
171 uint32_t irqchip_phandle
)
174 uint32_t irq_map_stride
= 0;
175 uint32_t full_irq_map
[GPEX_NUM_IRQS
* GPEX_NUM_IRQS
*
176 FDT_MAX_INT_MAP_WIDTH
] = {};
177 uint32_t *irq_map
= full_irq_map
;
179 /* This code creates a standard swizzle of interrupts such that
180 * each device's first interrupt is based on it's PCI_SLOT number.
181 * (See pci_swizzle_map_irq_fn())
183 * We only need one entry per interrupt in the table (not one per
184 * possible slot) seeing the interrupt-map-mask will allow the table
185 * to wrap to any number of devices.
187 for (dev
= 0; dev
< GPEX_NUM_IRQS
; dev
++) {
188 int devfn
= dev
* 0x8;
190 for (pin
= 0; pin
< GPEX_NUM_IRQS
; pin
++) {
191 int irq_nr
= PCIE_IRQ
+ ((pin
+ PCI_SLOT(devfn
)) % GPEX_NUM_IRQS
);
194 /* Fill PCI address cells */
195 irq_map
[i
] = cpu_to_be32(devfn
<< 8);
196 i
+= FDT_PCI_ADDR_CELLS
;
198 /* Fill PCI Interrupt cells */
199 irq_map
[i
] = cpu_to_be32(pin
+ 1);
200 i
+= FDT_PCI_INT_CELLS
;
202 /* Fill interrupt controller phandle and cells */
203 irq_map
[i
++] = cpu_to_be32(irqchip_phandle
);
204 irq_map
[i
++] = cpu_to_be32(irq_nr
);
205 if (s
->aia_type
!= VIRT_AIA_TYPE_NONE
) {
206 irq_map
[i
++] = cpu_to_be32(0x4);
209 if (!irq_map_stride
) {
212 irq_map
+= irq_map_stride
;
216 qemu_fdt_setprop(fdt
, nodename
, "interrupt-map", full_irq_map
,
217 GPEX_NUM_IRQS
* GPEX_NUM_IRQS
*
218 irq_map_stride
* sizeof(uint32_t));
220 qemu_fdt_setprop_cells(fdt
, nodename
, "interrupt-map-mask",
224 static void create_fdt_socket_cpus(RISCVVirtState
*s
, int socket
,
225 char *clust_name
, uint32_t *phandle
,
226 uint32_t *intc_phandles
)
229 uint32_t cpu_phandle
;
230 MachineState
*ms
= MACHINE(s
);
231 char *name
, *cpu_name
, *core_name
, *intc_name
;
232 bool is_32_bit
= riscv_is_32bit(&s
->soc
[0]);
234 for (cpu
= s
->soc
[socket
].num_harts
- 1; cpu
>= 0; cpu
--) {
235 RISCVCPU
*cpu_ptr
= &s
->soc
[socket
].harts
[cpu
];
237 cpu_phandle
= (*phandle
)++;
239 cpu_name
= g_strdup_printf("/cpus/cpu@%d",
240 s
->soc
[socket
].hartid_base
+ cpu
);
241 qemu_fdt_add_subnode(ms
->fdt
, cpu_name
);
242 if (cpu_ptr
->cfg
.mmu
) {
243 qemu_fdt_setprop_string(ms
->fdt
, cpu_name
, "mmu-type",
244 (is_32_bit
) ? "riscv,sv32" : "riscv,sv48");
246 qemu_fdt_setprop_string(ms
->fdt
, cpu_name
, "mmu-type",
249 name
= riscv_isa_string(cpu_ptr
);
250 qemu_fdt_setprop_string(ms
->fdt
, cpu_name
, "riscv,isa", name
);
252 qemu_fdt_setprop_string(ms
->fdt
, cpu_name
, "compatible", "riscv");
253 qemu_fdt_setprop_string(ms
->fdt
, cpu_name
, "status", "okay");
254 qemu_fdt_setprop_cell(ms
->fdt
, cpu_name
, "reg",
255 s
->soc
[socket
].hartid_base
+ cpu
);
256 qemu_fdt_setprop_string(ms
->fdt
, cpu_name
, "device_type", "cpu");
257 riscv_socket_fdt_write_id(ms
, cpu_name
, socket
);
258 qemu_fdt_setprop_cell(ms
->fdt
, cpu_name
, "phandle", cpu_phandle
);
260 intc_phandles
[cpu
] = (*phandle
)++;
262 intc_name
= g_strdup_printf("%s/interrupt-controller", cpu_name
);
263 qemu_fdt_add_subnode(ms
->fdt
, intc_name
);
264 qemu_fdt_setprop_cell(ms
->fdt
, intc_name
, "phandle",
266 qemu_fdt_setprop_string(ms
->fdt
, intc_name
, "compatible",
268 qemu_fdt_setprop(ms
->fdt
, intc_name
, "interrupt-controller", NULL
, 0);
269 qemu_fdt_setprop_cell(ms
->fdt
, intc_name
, "#interrupt-cells", 1);
271 core_name
= g_strdup_printf("%s/core%d", clust_name
, cpu
);
272 qemu_fdt_add_subnode(ms
->fdt
, core_name
);
273 qemu_fdt_setprop_cell(ms
->fdt
, core_name
, "cpu", cpu_phandle
);
281 static void create_fdt_socket_memory(RISCVVirtState
*s
,
282 const MemMapEntry
*memmap
, int socket
)
286 MachineState
*ms
= MACHINE(s
);
288 addr
= memmap
[VIRT_DRAM
].base
+ riscv_socket_mem_offset(ms
, socket
);
289 size
= riscv_socket_mem_size(ms
, socket
);
290 mem_name
= g_strdup_printf("/memory@%lx", (long)addr
);
291 qemu_fdt_add_subnode(ms
->fdt
, mem_name
);
292 qemu_fdt_setprop_cells(ms
->fdt
, mem_name
, "reg",
293 addr
>> 32, addr
, size
>> 32, size
);
294 qemu_fdt_setprop_string(ms
->fdt
, mem_name
, "device_type", "memory");
295 riscv_socket_fdt_write_id(ms
, mem_name
, socket
);
299 static void create_fdt_socket_clint(RISCVVirtState
*s
,
300 const MemMapEntry
*memmap
, int socket
,
301 uint32_t *intc_phandles
)
305 uint32_t *clint_cells
;
306 unsigned long clint_addr
;
307 MachineState
*ms
= MACHINE(s
);
308 static const char * const clint_compat
[2] = {
309 "sifive,clint0", "riscv,clint0"
312 clint_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 4);
314 for (cpu
= 0; cpu
< s
->soc
[socket
].num_harts
; cpu
++) {
315 clint_cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
316 clint_cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_SOFT
);
317 clint_cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandles
[cpu
]);
318 clint_cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_M_TIMER
);
321 clint_addr
= memmap
[VIRT_CLINT
].base
+ (memmap
[VIRT_CLINT
].size
* socket
);
322 clint_name
= g_strdup_printf("/soc/clint@%lx", clint_addr
);
323 qemu_fdt_add_subnode(ms
->fdt
, clint_name
);
324 qemu_fdt_setprop_string_array(ms
->fdt
, clint_name
, "compatible",
325 (char **)&clint_compat
,
326 ARRAY_SIZE(clint_compat
));
327 qemu_fdt_setprop_cells(ms
->fdt
, clint_name
, "reg",
328 0x0, clint_addr
, 0x0, memmap
[VIRT_CLINT
].size
);
329 qemu_fdt_setprop(ms
->fdt
, clint_name
, "interrupts-extended",
330 clint_cells
, s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 4);
331 riscv_socket_fdt_write_id(ms
, clint_name
, socket
);
337 static void create_fdt_socket_aclint(RISCVVirtState
*s
,
338 const MemMapEntry
*memmap
, int socket
,
339 uint32_t *intc_phandles
)
343 unsigned long addr
, size
;
344 uint32_t aclint_cells_size
;
345 uint32_t *aclint_mswi_cells
;
346 uint32_t *aclint_sswi_cells
;
347 uint32_t *aclint_mtimer_cells
;
348 MachineState
*ms
= MACHINE(s
);
350 aclint_mswi_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
351 aclint_mtimer_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
352 aclint_sswi_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
354 for (cpu
= 0; cpu
< s
->soc
[socket
].num_harts
; cpu
++) {
355 aclint_mswi_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
356 aclint_mswi_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_M_SOFT
);
357 aclint_mtimer_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
358 aclint_mtimer_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_M_TIMER
);
359 aclint_sswi_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
360 aclint_sswi_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_S_SOFT
);
362 aclint_cells_size
= s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 2;
364 if (s
->aia_type
!= VIRT_AIA_TYPE_APLIC_IMSIC
) {
365 addr
= memmap
[VIRT_CLINT
].base
+ (memmap
[VIRT_CLINT
].size
* socket
);
366 name
= g_strdup_printf("/soc/mswi@%lx", addr
);
367 qemu_fdt_add_subnode(ms
->fdt
, name
);
368 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible",
369 "riscv,aclint-mswi");
370 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
371 0x0, addr
, 0x0, RISCV_ACLINT_SWI_SIZE
);
372 qemu_fdt_setprop(ms
->fdt
, name
, "interrupts-extended",
373 aclint_mswi_cells
, aclint_cells_size
);
374 qemu_fdt_setprop(ms
->fdt
, name
, "interrupt-controller", NULL
, 0);
375 qemu_fdt_setprop_cell(ms
->fdt
, name
, "#interrupt-cells", 0);
376 riscv_socket_fdt_write_id(ms
, name
, socket
);
380 if (s
->aia_type
== VIRT_AIA_TYPE_APLIC_IMSIC
) {
381 addr
= memmap
[VIRT_CLINT
].base
+
382 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE
* socket
);
383 size
= RISCV_ACLINT_DEFAULT_MTIMER_SIZE
;
385 addr
= memmap
[VIRT_CLINT
].base
+ RISCV_ACLINT_SWI_SIZE
+
386 (memmap
[VIRT_CLINT
].size
* socket
);
387 size
= memmap
[VIRT_CLINT
].size
- RISCV_ACLINT_SWI_SIZE
;
389 name
= g_strdup_printf("/soc/mtimer@%lx", addr
);
390 qemu_fdt_add_subnode(ms
->fdt
, name
);
391 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible",
392 "riscv,aclint-mtimer");
393 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
394 0x0, addr
+ RISCV_ACLINT_DEFAULT_MTIME
,
395 0x0, size
- RISCV_ACLINT_DEFAULT_MTIME
,
396 0x0, addr
+ RISCV_ACLINT_DEFAULT_MTIMECMP
,
397 0x0, RISCV_ACLINT_DEFAULT_MTIME
);
398 qemu_fdt_setprop(ms
->fdt
, name
, "interrupts-extended",
399 aclint_mtimer_cells
, aclint_cells_size
);
400 riscv_socket_fdt_write_id(ms
, name
, socket
);
403 if (s
->aia_type
!= VIRT_AIA_TYPE_APLIC_IMSIC
) {
404 addr
= memmap
[VIRT_ACLINT_SSWI
].base
+
405 (memmap
[VIRT_ACLINT_SSWI
].size
* socket
);
406 name
= g_strdup_printf("/soc/sswi@%lx", addr
);
407 qemu_fdt_add_subnode(ms
->fdt
, name
);
408 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible",
409 "riscv,aclint-sswi");
410 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
411 0x0, addr
, 0x0, memmap
[VIRT_ACLINT_SSWI
].size
);
412 qemu_fdt_setprop(ms
->fdt
, name
, "interrupts-extended",
413 aclint_sswi_cells
, aclint_cells_size
);
414 qemu_fdt_setprop(ms
->fdt
, name
, "interrupt-controller", NULL
, 0);
415 qemu_fdt_setprop_cell(ms
->fdt
, name
, "#interrupt-cells", 0);
416 riscv_socket_fdt_write_id(ms
, name
, socket
);
420 g_free(aclint_mswi_cells
);
421 g_free(aclint_mtimer_cells
);
422 g_free(aclint_sswi_cells
);
425 static void create_fdt_socket_plic(RISCVVirtState
*s
,
426 const MemMapEntry
*memmap
, int socket
,
427 uint32_t *phandle
, uint32_t *intc_phandles
,
428 uint32_t *plic_phandles
)
432 uint32_t *plic_cells
;
433 unsigned long plic_addr
;
434 MachineState
*ms
= MACHINE(s
);
435 static const char * const plic_compat
[2] = {
436 "sifive,plic-1.0.0", "riscv,plic0"
440 plic_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
442 plic_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 4);
445 for (cpu
= 0; cpu
< s
->soc
[socket
].num_harts
; cpu
++) {
447 plic_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
448 plic_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_S_EXT
);
450 plic_cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
451 plic_cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_EXT
);
452 plic_cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandles
[cpu
]);
453 plic_cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_S_EXT
);
457 plic_phandles
[socket
] = (*phandle
)++;
458 plic_addr
= memmap
[VIRT_PLIC
].base
+ (memmap
[VIRT_PLIC
].size
* socket
);
459 plic_name
= g_strdup_printf("/soc/plic@%lx", plic_addr
);
460 qemu_fdt_add_subnode(ms
->fdt
, plic_name
);
461 qemu_fdt_setprop_cell(ms
->fdt
, plic_name
,
462 "#interrupt-cells", FDT_PLIC_INT_CELLS
);
463 qemu_fdt_setprop_cell(ms
->fdt
, plic_name
,
464 "#address-cells", FDT_PLIC_ADDR_CELLS
);
465 qemu_fdt_setprop_string_array(ms
->fdt
, plic_name
, "compatible",
466 (char **)&plic_compat
,
467 ARRAY_SIZE(plic_compat
));
468 qemu_fdt_setprop(ms
->fdt
, plic_name
, "interrupt-controller", NULL
, 0);
469 qemu_fdt_setprop(ms
->fdt
, plic_name
, "interrupts-extended",
470 plic_cells
, s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 4);
471 qemu_fdt_setprop_cells(ms
->fdt
, plic_name
, "reg",
472 0x0, plic_addr
, 0x0, memmap
[VIRT_PLIC
].size
);
473 qemu_fdt_setprop_cell(ms
->fdt
, plic_name
, "riscv,ndev",
474 VIRT_IRQCHIP_NUM_SOURCES
- 1);
475 riscv_socket_fdt_write_id(ms
, plic_name
, socket
);
476 qemu_fdt_setprop_cell(ms
->fdt
, plic_name
, "phandle",
477 plic_phandles
[socket
]);
480 platform_bus_add_all_fdt_nodes(ms
->fdt
, plic_name
,
481 memmap
[VIRT_PLATFORM_BUS
].base
,
482 memmap
[VIRT_PLATFORM_BUS
].size
,
483 VIRT_PLATFORM_BUS_IRQ
);
491 static uint32_t imsic_num_bits(uint32_t count
)
495 while (BIT(ret
) < count
) {
502 static void create_fdt_imsic(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
503 uint32_t *phandle
, uint32_t *intc_phandles
,
504 uint32_t *msi_m_phandle
, uint32_t *msi_s_phandle
)
508 MachineState
*ms
= MACHINE(s
);
509 int socket_count
= riscv_socket_count(ms
);
510 uint32_t imsic_max_hart_per_socket
, imsic_guest_bits
;
511 uint32_t *imsic_cells
, *imsic_regs
, imsic_addr
, imsic_size
;
513 *msi_m_phandle
= (*phandle
)++;
514 *msi_s_phandle
= (*phandle
)++;
515 imsic_cells
= g_new0(uint32_t, ms
->smp
.cpus
* 2);
516 imsic_regs
= g_new0(uint32_t, socket_count
* 4);
518 /* M-level IMSIC node */
519 for (cpu
= 0; cpu
< ms
->smp
.cpus
; cpu
++) {
520 imsic_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
521 imsic_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_M_EXT
);
523 imsic_max_hart_per_socket
= 0;
524 for (socket
= 0; socket
< socket_count
; socket
++) {
525 imsic_addr
= memmap
[VIRT_IMSIC_M
].base
+
526 socket
* VIRT_IMSIC_GROUP_MAX_SIZE
;
527 imsic_size
= IMSIC_HART_SIZE(0) * s
->soc
[socket
].num_harts
;
528 imsic_regs
[socket
* 4 + 0] = 0;
529 imsic_regs
[socket
* 4 + 1] = cpu_to_be32(imsic_addr
);
530 imsic_regs
[socket
* 4 + 2] = 0;
531 imsic_regs
[socket
* 4 + 3] = cpu_to_be32(imsic_size
);
532 if (imsic_max_hart_per_socket
< s
->soc
[socket
].num_harts
) {
533 imsic_max_hart_per_socket
= s
->soc
[socket
].num_harts
;
536 imsic_name
= g_strdup_printf("/soc/imsics@%lx",
537 (unsigned long)memmap
[VIRT_IMSIC_M
].base
);
538 qemu_fdt_add_subnode(ms
->fdt
, imsic_name
);
539 qemu_fdt_setprop_string(ms
->fdt
, imsic_name
, "compatible",
541 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "#interrupt-cells",
542 FDT_IMSIC_INT_CELLS
);
543 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "interrupt-controller",
545 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "msi-controller",
547 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "interrupts-extended",
548 imsic_cells
, ms
->smp
.cpus
* sizeof(uint32_t) * 2);
549 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "reg", imsic_regs
,
550 socket_count
* sizeof(uint32_t) * 4);
551 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,num-ids",
552 VIRT_IRQCHIP_NUM_MSIS
);
553 if (socket_count
> 1) {
554 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,hart-index-bits",
555 imsic_num_bits(imsic_max_hart_per_socket
));
556 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,group-index-bits",
557 imsic_num_bits(socket_count
));
558 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,group-index-shift",
559 IMSIC_MMIO_GROUP_MIN_SHIFT
);
561 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "phandle", *msi_m_phandle
);
565 /* S-level IMSIC node */
566 for (cpu
= 0; cpu
< ms
->smp
.cpus
; cpu
++) {
567 imsic_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
568 imsic_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_S_EXT
);
570 imsic_guest_bits
= imsic_num_bits(s
->aia_guests
+ 1);
571 imsic_max_hart_per_socket
= 0;
572 for (socket
= 0; socket
< socket_count
; socket
++) {
573 imsic_addr
= memmap
[VIRT_IMSIC_S
].base
+
574 socket
* VIRT_IMSIC_GROUP_MAX_SIZE
;
575 imsic_size
= IMSIC_HART_SIZE(imsic_guest_bits
) *
576 s
->soc
[socket
].num_harts
;
577 imsic_regs
[socket
* 4 + 0] = 0;
578 imsic_regs
[socket
* 4 + 1] = cpu_to_be32(imsic_addr
);
579 imsic_regs
[socket
* 4 + 2] = 0;
580 imsic_regs
[socket
* 4 + 3] = cpu_to_be32(imsic_size
);
581 if (imsic_max_hart_per_socket
< s
->soc
[socket
].num_harts
) {
582 imsic_max_hart_per_socket
= s
->soc
[socket
].num_harts
;
585 imsic_name
= g_strdup_printf("/soc/imsics@%lx",
586 (unsigned long)memmap
[VIRT_IMSIC_S
].base
);
587 qemu_fdt_add_subnode(ms
->fdt
, imsic_name
);
588 qemu_fdt_setprop_string(ms
->fdt
, imsic_name
, "compatible",
590 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "#interrupt-cells",
591 FDT_IMSIC_INT_CELLS
);
592 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "interrupt-controller",
594 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "msi-controller",
596 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "interrupts-extended",
597 imsic_cells
, ms
->smp
.cpus
* sizeof(uint32_t) * 2);
598 qemu_fdt_setprop(ms
->fdt
, imsic_name
, "reg", imsic_regs
,
599 socket_count
* sizeof(uint32_t) * 4);
600 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,num-ids",
601 VIRT_IRQCHIP_NUM_MSIS
);
602 if (imsic_guest_bits
) {
603 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,guest-index-bits",
606 if (socket_count
> 1) {
607 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,hart-index-bits",
608 imsic_num_bits(imsic_max_hart_per_socket
));
609 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,group-index-bits",
610 imsic_num_bits(socket_count
));
611 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "riscv,group-index-shift",
612 IMSIC_MMIO_GROUP_MIN_SHIFT
);
614 qemu_fdt_setprop_cell(ms
->fdt
, imsic_name
, "phandle", *msi_s_phandle
);
621 static void create_fdt_socket_aplic(RISCVVirtState
*s
,
622 const MemMapEntry
*memmap
, int socket
,
623 uint32_t msi_m_phandle
,
624 uint32_t msi_s_phandle
,
626 uint32_t *intc_phandles
,
627 uint32_t *aplic_phandles
)
631 uint32_t *aplic_cells
;
632 unsigned long aplic_addr
;
633 MachineState
*ms
= MACHINE(s
);
634 uint32_t aplic_m_phandle
, aplic_s_phandle
;
636 aplic_m_phandle
= (*phandle
)++;
637 aplic_s_phandle
= (*phandle
)++;
638 aplic_cells
= g_new0(uint32_t, s
->soc
[socket
].num_harts
* 2);
640 /* M-level APLIC node */
641 for (cpu
= 0; cpu
< s
->soc
[socket
].num_harts
; cpu
++) {
642 aplic_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
643 aplic_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_M_EXT
);
645 aplic_addr
= memmap
[VIRT_APLIC_M
].base
+
646 (memmap
[VIRT_APLIC_M
].size
* socket
);
647 aplic_name
= g_strdup_printf("/soc/aplic@%lx", aplic_addr
);
648 qemu_fdt_add_subnode(ms
->fdt
, aplic_name
);
649 qemu_fdt_setprop_string(ms
->fdt
, aplic_name
, "compatible", "riscv,aplic");
650 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
,
651 "#interrupt-cells", FDT_APLIC_INT_CELLS
);
652 qemu_fdt_setprop(ms
->fdt
, aplic_name
, "interrupt-controller", NULL
, 0);
653 if (s
->aia_type
== VIRT_AIA_TYPE_APLIC
) {
654 qemu_fdt_setprop(ms
->fdt
, aplic_name
, "interrupts-extended",
655 aplic_cells
, s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 2);
657 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "msi-parent",
660 qemu_fdt_setprop_cells(ms
->fdt
, aplic_name
, "reg",
661 0x0, aplic_addr
, 0x0, memmap
[VIRT_APLIC_M
].size
);
662 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "riscv,num-sources",
663 VIRT_IRQCHIP_NUM_SOURCES
);
664 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "riscv,children",
666 qemu_fdt_setprop_cells(ms
->fdt
, aplic_name
, "riscv,delegate",
667 aplic_s_phandle
, 0x1, VIRT_IRQCHIP_NUM_SOURCES
);
668 riscv_socket_fdt_write_id(ms
, aplic_name
, socket
);
669 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "phandle", aplic_m_phandle
);
672 /* S-level APLIC node */
673 for (cpu
= 0; cpu
< s
->soc
[socket
].num_harts
; cpu
++) {
674 aplic_cells
[cpu
* 2 + 0] = cpu_to_be32(intc_phandles
[cpu
]);
675 aplic_cells
[cpu
* 2 + 1] = cpu_to_be32(IRQ_S_EXT
);
677 aplic_addr
= memmap
[VIRT_APLIC_S
].base
+
678 (memmap
[VIRT_APLIC_S
].size
* socket
);
679 aplic_name
= g_strdup_printf("/soc/aplic@%lx", aplic_addr
);
680 qemu_fdt_add_subnode(ms
->fdt
, aplic_name
);
681 qemu_fdt_setprop_string(ms
->fdt
, aplic_name
, "compatible", "riscv,aplic");
682 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
,
683 "#interrupt-cells", FDT_APLIC_INT_CELLS
);
684 qemu_fdt_setprop(ms
->fdt
, aplic_name
, "interrupt-controller", NULL
, 0);
685 if (s
->aia_type
== VIRT_AIA_TYPE_APLIC
) {
686 qemu_fdt_setprop(ms
->fdt
, aplic_name
, "interrupts-extended",
687 aplic_cells
, s
->soc
[socket
].num_harts
* sizeof(uint32_t) * 2);
689 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "msi-parent",
692 qemu_fdt_setprop_cells(ms
->fdt
, aplic_name
, "reg",
693 0x0, aplic_addr
, 0x0, memmap
[VIRT_APLIC_S
].size
);
694 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "riscv,num-sources",
695 VIRT_IRQCHIP_NUM_SOURCES
);
696 riscv_socket_fdt_write_id(ms
, aplic_name
, socket
);
697 qemu_fdt_setprop_cell(ms
->fdt
, aplic_name
, "phandle", aplic_s_phandle
);
700 platform_bus_add_all_fdt_nodes(ms
->fdt
, aplic_name
,
701 memmap
[VIRT_PLATFORM_BUS
].base
,
702 memmap
[VIRT_PLATFORM_BUS
].size
,
703 VIRT_PLATFORM_BUS_IRQ
);
709 aplic_phandles
[socket
] = aplic_s_phandle
;
712 static void create_fdt_pmu(RISCVVirtState
*s
)
715 MachineState
*ms
= MACHINE(s
);
716 RISCVCPU hart
= s
->soc
[0].harts
[0];
718 pmu_name
= g_strdup_printf("/soc/pmu");
719 qemu_fdt_add_subnode(ms
->fdt
, pmu_name
);
720 qemu_fdt_setprop_string(ms
->fdt
, pmu_name
, "compatible", "riscv,pmu");
721 riscv_pmu_generate_fdt_node(ms
->fdt
, hart
.cfg
.pmu_num
, pmu_name
);
726 static void create_fdt_sockets(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
728 uint32_t *irq_mmio_phandle
,
729 uint32_t *irq_pcie_phandle
,
730 uint32_t *irq_virtio_phandle
,
731 uint32_t *msi_pcie_phandle
)
734 int socket
, phandle_pos
;
735 MachineState
*ms
= MACHINE(s
);
736 uint32_t msi_m_phandle
= 0, msi_s_phandle
= 0;
737 uint32_t *intc_phandles
, xplic_phandles
[MAX_NODES
];
738 int socket_count
= riscv_socket_count(ms
);
740 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
741 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "timebase-frequency",
742 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ
);
743 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
744 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", 0x1);
745 qemu_fdt_add_subnode(ms
->fdt
, "/cpus/cpu-map");
747 intc_phandles
= g_new0(uint32_t, ms
->smp
.cpus
);
749 phandle_pos
= ms
->smp
.cpus
;
750 for (socket
= (socket_count
- 1); socket
>= 0; socket
--) {
751 phandle_pos
-= s
->soc
[socket
].num_harts
;
753 clust_name
= g_strdup_printf("/cpus/cpu-map/cluster%d", socket
);
754 qemu_fdt_add_subnode(ms
->fdt
, clust_name
);
756 create_fdt_socket_cpus(s
, socket
, clust_name
, phandle
,
757 &intc_phandles
[phandle_pos
]);
759 create_fdt_socket_memory(s
, memmap
, socket
);
763 if (!kvm_enabled()) {
764 if (s
->have_aclint
) {
765 create_fdt_socket_aclint(s
, memmap
, socket
,
766 &intc_phandles
[phandle_pos
]);
768 create_fdt_socket_clint(s
, memmap
, socket
,
769 &intc_phandles
[phandle_pos
]);
774 if (s
->aia_type
== VIRT_AIA_TYPE_APLIC_IMSIC
) {
775 create_fdt_imsic(s
, memmap
, phandle
, intc_phandles
,
776 &msi_m_phandle
, &msi_s_phandle
);
777 *msi_pcie_phandle
= msi_s_phandle
;
780 phandle_pos
= ms
->smp
.cpus
;
781 for (socket
= (socket_count
- 1); socket
>= 0; socket
--) {
782 phandle_pos
-= s
->soc
[socket
].num_harts
;
784 if (s
->aia_type
== VIRT_AIA_TYPE_NONE
) {
785 create_fdt_socket_plic(s
, memmap
, socket
, phandle
,
786 &intc_phandles
[phandle_pos
], xplic_phandles
);
788 create_fdt_socket_aplic(s
, memmap
, socket
,
789 msi_m_phandle
, msi_s_phandle
, phandle
,
790 &intc_phandles
[phandle_pos
], xplic_phandles
);
794 g_free(intc_phandles
);
796 for (socket
= 0; socket
< socket_count
; socket
++) {
798 *irq_mmio_phandle
= xplic_phandles
[socket
];
799 *irq_virtio_phandle
= xplic_phandles
[socket
];
800 *irq_pcie_phandle
= xplic_phandles
[socket
];
803 *irq_virtio_phandle
= xplic_phandles
[socket
];
804 *irq_pcie_phandle
= xplic_phandles
[socket
];
807 *irq_pcie_phandle
= xplic_phandles
[socket
];
811 riscv_socket_fdt_write_distance_matrix(ms
);
814 static void create_fdt_virtio(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
815 uint32_t irq_virtio_phandle
)
819 MachineState
*ms
= MACHINE(s
);
821 for (i
= 0; i
< VIRTIO_COUNT
; i
++) {
822 name
= g_strdup_printf("/soc/virtio_mmio@%lx",
823 (long)(memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
));
824 qemu_fdt_add_subnode(ms
->fdt
, name
);
825 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible", "virtio,mmio");
826 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
827 0x0, memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
,
828 0x0, memmap
[VIRT_VIRTIO
].size
);
829 qemu_fdt_setprop_cell(ms
->fdt
, name
, "interrupt-parent",
831 if (s
->aia_type
== VIRT_AIA_TYPE_NONE
) {
832 qemu_fdt_setprop_cell(ms
->fdt
, name
, "interrupts",
835 qemu_fdt_setprop_cells(ms
->fdt
, name
, "interrupts",
836 VIRTIO_IRQ
+ i
, 0x4);
842 static void create_fdt_pcie(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
843 uint32_t irq_pcie_phandle
,
844 uint32_t msi_pcie_phandle
)
847 MachineState
*ms
= MACHINE(s
);
849 name
= g_strdup_printf("/soc/pci@%lx",
850 (long) memmap
[VIRT_PCIE_ECAM
].base
);
851 qemu_fdt_add_subnode(ms
->fdt
, name
);
852 qemu_fdt_setprop_cell(ms
->fdt
, name
, "#address-cells",
854 qemu_fdt_setprop_cell(ms
->fdt
, name
, "#interrupt-cells",
856 qemu_fdt_setprop_cell(ms
->fdt
, name
, "#size-cells", 0x2);
857 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible",
858 "pci-host-ecam-generic");
859 qemu_fdt_setprop_string(ms
->fdt
, name
, "device_type", "pci");
860 qemu_fdt_setprop_cell(ms
->fdt
, name
, "linux,pci-domain", 0);
861 qemu_fdt_setprop_cells(ms
->fdt
, name
, "bus-range", 0,
862 memmap
[VIRT_PCIE_ECAM
].size
/ PCIE_MMCFG_SIZE_MIN
- 1);
863 qemu_fdt_setprop(ms
->fdt
, name
, "dma-coherent", NULL
, 0);
864 if (s
->aia_type
== VIRT_AIA_TYPE_APLIC_IMSIC
) {
865 qemu_fdt_setprop_cell(ms
->fdt
, name
, "msi-parent", msi_pcie_phandle
);
867 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg", 0,
868 memmap
[VIRT_PCIE_ECAM
].base
, 0, memmap
[VIRT_PCIE_ECAM
].size
);
869 qemu_fdt_setprop_sized_cells(ms
->fdt
, name
, "ranges",
870 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
871 2, memmap
[VIRT_PCIE_PIO
].base
, 2, memmap
[VIRT_PCIE_PIO
].size
,
872 1, FDT_PCI_RANGE_MMIO
,
873 2, memmap
[VIRT_PCIE_MMIO
].base
,
874 2, memmap
[VIRT_PCIE_MMIO
].base
, 2, memmap
[VIRT_PCIE_MMIO
].size
,
875 1, FDT_PCI_RANGE_MMIO_64BIT
,
876 2, virt_high_pcie_memmap
.base
,
877 2, virt_high_pcie_memmap
.base
, 2, virt_high_pcie_memmap
.size
);
879 create_pcie_irq_map(s
, ms
->fdt
, name
, irq_pcie_phandle
);
883 static void create_fdt_reset(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
887 uint32_t test_phandle
;
888 MachineState
*ms
= MACHINE(s
);
890 test_phandle
= (*phandle
)++;
891 name
= g_strdup_printf("/soc/test@%lx",
892 (long)memmap
[VIRT_TEST
].base
);
893 qemu_fdt_add_subnode(ms
->fdt
, name
);
895 static const char * const compat
[3] = {
896 "sifive,test1", "sifive,test0", "syscon"
898 qemu_fdt_setprop_string_array(ms
->fdt
, name
, "compatible",
899 (char **)&compat
, ARRAY_SIZE(compat
));
901 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
902 0x0, memmap
[VIRT_TEST
].base
, 0x0, memmap
[VIRT_TEST
].size
);
903 qemu_fdt_setprop_cell(ms
->fdt
, name
, "phandle", test_phandle
);
904 test_phandle
= qemu_fdt_get_phandle(ms
->fdt
, name
);
907 name
= g_strdup_printf("/reboot");
908 qemu_fdt_add_subnode(ms
->fdt
, name
);
909 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible", "syscon-reboot");
910 qemu_fdt_setprop_cell(ms
->fdt
, name
, "regmap", test_phandle
);
911 qemu_fdt_setprop_cell(ms
->fdt
, name
, "offset", 0x0);
912 qemu_fdt_setprop_cell(ms
->fdt
, name
, "value", FINISHER_RESET
);
915 name
= g_strdup_printf("/poweroff");
916 qemu_fdt_add_subnode(ms
->fdt
, name
);
917 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible", "syscon-poweroff");
918 qemu_fdt_setprop_cell(ms
->fdt
, name
, "regmap", test_phandle
);
919 qemu_fdt_setprop_cell(ms
->fdt
, name
, "offset", 0x0);
920 qemu_fdt_setprop_cell(ms
->fdt
, name
, "value", FINISHER_PASS
);
924 static void create_fdt_uart(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
925 uint32_t irq_mmio_phandle
)
928 MachineState
*ms
= MACHINE(s
);
930 name
= g_strdup_printf("/soc/serial@%lx", (long)memmap
[VIRT_UART0
].base
);
931 qemu_fdt_add_subnode(ms
->fdt
, name
);
932 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible", "ns16550a");
933 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
934 0x0, memmap
[VIRT_UART0
].base
,
935 0x0, memmap
[VIRT_UART0
].size
);
936 qemu_fdt_setprop_cell(ms
->fdt
, name
, "clock-frequency", 3686400);
937 qemu_fdt_setprop_cell(ms
->fdt
, name
, "interrupt-parent", irq_mmio_phandle
);
938 if (s
->aia_type
== VIRT_AIA_TYPE_NONE
) {
939 qemu_fdt_setprop_cell(ms
->fdt
, name
, "interrupts", UART0_IRQ
);
941 qemu_fdt_setprop_cells(ms
->fdt
, name
, "interrupts", UART0_IRQ
, 0x4);
944 qemu_fdt_add_subnode(ms
->fdt
, "/chosen");
945 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", name
);
949 static void create_fdt_rtc(RISCVVirtState
*s
, const MemMapEntry
*memmap
,
950 uint32_t irq_mmio_phandle
)
953 MachineState
*ms
= MACHINE(s
);
955 name
= g_strdup_printf("/soc/rtc@%lx", (long)memmap
[VIRT_RTC
].base
);
956 qemu_fdt_add_subnode(ms
->fdt
, name
);
957 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible",
958 "google,goldfish-rtc");
959 qemu_fdt_setprop_cells(ms
->fdt
, name
, "reg",
960 0x0, memmap
[VIRT_RTC
].base
, 0x0, memmap
[VIRT_RTC
].size
);
961 qemu_fdt_setprop_cell(ms
->fdt
, name
, "interrupt-parent",
963 if (s
->aia_type
== VIRT_AIA_TYPE_NONE
) {
964 qemu_fdt_setprop_cell(ms
->fdt
, name
, "interrupts", RTC_IRQ
);
966 qemu_fdt_setprop_cells(ms
->fdt
, name
, "interrupts", RTC_IRQ
, 0x4);
971 static void create_fdt_flash(RISCVVirtState
*s
, const MemMapEntry
*memmap
)
974 MachineState
*ms
= MACHINE(s
);
975 hwaddr flashsize
= virt_memmap
[VIRT_FLASH
].size
/ 2;
976 hwaddr flashbase
= virt_memmap
[VIRT_FLASH
].base
;
978 name
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
979 qemu_fdt_add_subnode(ms
->fdt
, name
);
980 qemu_fdt_setprop_string(ms
->fdt
, name
, "compatible", "cfi-flash");
981 qemu_fdt_setprop_sized_cells(ms
->fdt
, name
, "reg",
982 2, flashbase
, 2, flashsize
,
983 2, flashbase
+ flashsize
, 2, flashsize
);
984 qemu_fdt_setprop_cell(ms
->fdt
, name
, "bank-width", 4);
988 static void create_fdt_fw_cfg(RISCVVirtState
*s
, const MemMapEntry
*memmap
)
991 MachineState
*ms
= MACHINE(s
);
992 hwaddr base
= memmap
[VIRT_FW_CFG
].base
;
993 hwaddr size
= memmap
[VIRT_FW_CFG
].size
;
995 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
996 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
997 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
998 "compatible", "qemu,fw-cfg-mmio");
999 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1001 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1005 static void create_fdt(RISCVVirtState
*s
, const MemMapEntry
*memmap
)
1007 MachineState
*ms
= MACHINE(s
);
1008 uint32_t phandle
= 1, irq_mmio_phandle
= 1, msi_pcie_phandle
= 1;
1009 uint32_t irq_pcie_phandle
= 1, irq_virtio_phandle
= 1;
1010 uint8_t rng_seed
[32];
1012 ms
->fdt
= create_device_tree(&s
->fdt_size
);
1014 error_report("create_device_tree() failed");
1018 qemu_fdt_setprop_string(ms
->fdt
, "/", "model", "riscv-virtio,qemu");
1019 qemu_fdt_setprop_string(ms
->fdt
, "/", "compatible", "riscv-virtio");
1020 qemu_fdt_setprop_cell(ms
->fdt
, "/", "#size-cells", 0x2);
1021 qemu_fdt_setprop_cell(ms
->fdt
, "/", "#address-cells", 0x2);
1023 qemu_fdt_add_subnode(ms
->fdt
, "/soc");
1024 qemu_fdt_setprop(ms
->fdt
, "/soc", "ranges", NULL
, 0);
1025 qemu_fdt_setprop_string(ms
->fdt
, "/soc", "compatible", "simple-bus");
1026 qemu_fdt_setprop_cell(ms
->fdt
, "/soc", "#size-cells", 0x2);
1027 qemu_fdt_setprop_cell(ms
->fdt
, "/soc", "#address-cells", 0x2);
1029 create_fdt_sockets(s
, memmap
, &phandle
, &irq_mmio_phandle
,
1030 &irq_pcie_phandle
, &irq_virtio_phandle
,
1033 create_fdt_virtio(s
, memmap
, irq_virtio_phandle
);
1035 create_fdt_pcie(s
, memmap
, irq_pcie_phandle
, msi_pcie_phandle
);
1037 create_fdt_reset(s
, memmap
, &phandle
);
1039 create_fdt_uart(s
, memmap
, irq_mmio_phandle
);
1041 create_fdt_rtc(s
, memmap
, irq_mmio_phandle
);
1043 create_fdt_flash(s
, memmap
);
1044 create_fdt_fw_cfg(s
, memmap
);
1047 /* Pass seed to RNG */
1048 qemu_guest_getrandom_nofail(rng_seed
, sizeof(rng_seed
));
1049 qemu_fdt_setprop(ms
->fdt
, "/chosen", "rng-seed",
1050 rng_seed
, sizeof(rng_seed
));
1053 static inline DeviceState
*gpex_pcie_init(MemoryRegion
*sys_mem
,
1054 hwaddr ecam_base
, hwaddr ecam_size
,
1055 hwaddr mmio_base
, hwaddr mmio_size
,
1056 hwaddr high_mmio_base
,
1057 hwaddr high_mmio_size
,
1059 DeviceState
*irqchip
)
1062 MemoryRegion
*ecam_alias
, *ecam_reg
;
1063 MemoryRegion
*mmio_alias
, *high_mmio_alias
, *mmio_reg
;
1067 dev
= qdev_new(TYPE_GPEX_HOST
);
1069 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1071 ecam_alias
= g_new0(MemoryRegion
, 1);
1072 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1073 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1074 ecam_reg
, 0, ecam_size
);
1075 memory_region_add_subregion(get_system_memory(), ecam_base
, ecam_alias
);
1077 mmio_alias
= g_new0(MemoryRegion
, 1);
1078 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1079 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1080 mmio_reg
, mmio_base
, mmio_size
);
1081 memory_region_add_subregion(get_system_memory(), mmio_base
, mmio_alias
);
1083 /* Map high MMIO space */
1084 high_mmio_alias
= g_new0(MemoryRegion
, 1);
1085 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1086 mmio_reg
, high_mmio_base
, high_mmio_size
);
1087 memory_region_add_subregion(get_system_memory(), high_mmio_base
,
1090 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, pio_base
);
1092 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1093 irq
= qdev_get_gpio_in(irqchip
, PCIE_IRQ
+ i
);
1095 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, irq
);
1096 gpex_set_irq_num(GPEX_HOST(dev
), i
, PCIE_IRQ
+ i
);
1102 static FWCfgState
*create_fw_cfg(const MachineState
*ms
)
1104 hwaddr base
= virt_memmap
[VIRT_FW_CFG
].base
;
1107 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16,
1108 &address_space_memory
);
1109 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1114 static DeviceState
*virt_create_plic(const MemMapEntry
*memmap
, int socket
,
1115 int base_hartid
, int hart_count
)
1118 char *plic_hart_config
;
1120 /* Per-socket PLIC hart topology configuration string */
1121 plic_hart_config
= riscv_plic_hart_config_string(hart_count
);
1123 /* Per-socket PLIC */
1124 ret
= sifive_plic_create(
1125 memmap
[VIRT_PLIC
].base
+ socket
* memmap
[VIRT_PLIC
].size
,
1126 plic_hart_config
, hart_count
, base_hartid
,
1127 VIRT_IRQCHIP_NUM_SOURCES
,
1128 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS
) - 1),
1129 VIRT_PLIC_PRIORITY_BASE
,
1130 VIRT_PLIC_PENDING_BASE
,
1131 VIRT_PLIC_ENABLE_BASE
,
1132 VIRT_PLIC_ENABLE_STRIDE
,
1133 VIRT_PLIC_CONTEXT_BASE
,
1134 VIRT_PLIC_CONTEXT_STRIDE
,
1135 memmap
[VIRT_PLIC
].size
);
1137 g_free(plic_hart_config
);
1142 static DeviceState
*virt_create_aia(RISCVVirtAIAType aia_type
, int aia_guests
,
1143 const MemMapEntry
*memmap
, int socket
,
1144 int base_hartid
, int hart_count
)
1148 uint32_t guest_bits
;
1149 DeviceState
*aplic_m
;
1150 bool msimode
= (aia_type
== VIRT_AIA_TYPE_APLIC_IMSIC
) ? true : false;
1153 /* Per-socket M-level IMSICs */
1154 addr
= memmap
[VIRT_IMSIC_M
].base
+ socket
* VIRT_IMSIC_GROUP_MAX_SIZE
;
1155 for (i
= 0; i
< hart_count
; i
++) {
1156 riscv_imsic_create(addr
+ i
* IMSIC_HART_SIZE(0),
1157 base_hartid
+ i
, true, 1,
1158 VIRT_IRQCHIP_NUM_MSIS
);
1161 /* Per-socket S-level IMSICs */
1162 guest_bits
= imsic_num_bits(aia_guests
+ 1);
1163 addr
= memmap
[VIRT_IMSIC_S
].base
+ socket
* VIRT_IMSIC_GROUP_MAX_SIZE
;
1164 for (i
= 0; i
< hart_count
; i
++) {
1165 riscv_imsic_create(addr
+ i
* IMSIC_HART_SIZE(guest_bits
),
1166 base_hartid
+ i
, false, 1 + aia_guests
,
1167 VIRT_IRQCHIP_NUM_MSIS
);
1171 /* Per-socket M-level APLIC */
1172 aplic_m
= riscv_aplic_create(
1173 memmap
[VIRT_APLIC_M
].base
+ socket
* memmap
[VIRT_APLIC_M
].size
,
1174 memmap
[VIRT_APLIC_M
].size
,
1175 (msimode
) ? 0 : base_hartid
,
1176 (msimode
) ? 0 : hart_count
,
1177 VIRT_IRQCHIP_NUM_SOURCES
,
1178 VIRT_IRQCHIP_NUM_PRIO_BITS
,
1179 msimode
, true, NULL
);
1182 /* Per-socket S-level APLIC */
1184 memmap
[VIRT_APLIC_S
].base
+ socket
* memmap
[VIRT_APLIC_S
].size
,
1185 memmap
[VIRT_APLIC_S
].size
,
1186 (msimode
) ? 0 : base_hartid
,
1187 (msimode
) ? 0 : hart_count
,
1188 VIRT_IRQCHIP_NUM_SOURCES
,
1189 VIRT_IRQCHIP_NUM_PRIO_BITS
,
1190 msimode
, false, aplic_m
);
1196 static void create_platform_bus(RISCVVirtState
*s
, DeviceState
*irqchip
)
1199 SysBusDevice
*sysbus
;
1200 const MemMapEntry
*memmap
= virt_memmap
;
1202 MemoryRegion
*sysmem
= get_system_memory();
1204 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1205 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1206 qdev_prop_set_uint32(dev
, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS
);
1207 qdev_prop_set_uint32(dev
, "mmio_size", memmap
[VIRT_PLATFORM_BUS
].size
);
1208 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1209 s
->platform_bus_dev
= dev
;
1211 sysbus
= SYS_BUS_DEVICE(dev
);
1212 for (i
= 0; i
< VIRT_PLATFORM_BUS_NUM_IRQS
; i
++) {
1213 int irq
= VIRT_PLATFORM_BUS_IRQ
+ i
;
1214 sysbus_connect_irq(sysbus
, i
, qdev_get_gpio_in(irqchip
, irq
));
1217 memory_region_add_subregion(sysmem
,
1218 memmap
[VIRT_PLATFORM_BUS
].base
,
1219 sysbus_mmio_get_region(sysbus
, 0));
1222 static void virt_machine_done(Notifier
*notifier
, void *data
)
1224 RISCVVirtState
*s
= container_of(notifier
, RISCVVirtState
,
1226 const MemMapEntry
*memmap
= virt_memmap
;
1227 MachineState
*machine
= MACHINE(s
);
1228 target_ulong start_addr
= memmap
[VIRT_DRAM
].base
;
1229 target_ulong firmware_end_addr
, kernel_start_addr
;
1230 const char *firmware_name
= riscv_default_firmware_name(&s
->soc
[0]);
1231 uint32_t fdt_load_addr
;
1232 uint64_t kernel_entry
;
1235 * Only direct boot kernel is currently supported for KVM VM,
1236 * so the "-bios" parameter is not supported when KVM is enabled.
1238 if (kvm_enabled()) {
1239 if (machine
->firmware
) {
1240 if (strcmp(machine
->firmware
, "none")) {
1241 error_report("Machine mode firmware is not supported in "
1242 "combination with KVM.");
1246 machine
->firmware
= g_strdup("none");
1250 firmware_end_addr
= riscv_find_and_load_firmware(machine
, firmware_name
,
1253 if (drive_get(IF_PFLASH
, 0, 1)) {
1255 * S-mode FW like EDK2 will be kept in second plash (unit 1).
1256 * When both kernel, initrd and pflash options are provided in the
1257 * command line, the kernel and initrd will be copied to the fw_cfg
1258 * table and opensbi will jump to the flash address which is the
1259 * entry point of S-mode FW. It is the job of the S-mode FW to load
1260 * the kernel and initrd using fw_cfg table.
1262 * If only pflash is given but not -kernel, then it is the job of
1263 * of the S-mode firmware to locate and load the kernel.
1264 * In either case, the next_addr for opensbi will be the flash address.
1266 riscv_setup_firmware_boot(machine
);
1267 kernel_entry
= virt_memmap
[VIRT_FLASH
].base
+
1268 virt_memmap
[VIRT_FLASH
].size
/ 2;
1269 } else if (machine
->kernel_filename
) {
1270 kernel_start_addr
= riscv_calc_kernel_start_addr(&s
->soc
[0],
1273 kernel_entry
= riscv_load_kernel(machine
, &s
->soc
[0],
1274 kernel_start_addr
, true, NULL
);
1277 * If dynamic firmware is used, it doesn't know where is the next mode
1278 * if kernel argument is not set.
1283 if (drive_get(IF_PFLASH
, 0, 0)) {
1285 * Pflash was supplied, let's overwrite the address we jump to after
1286 * reset to the base of the flash.
1288 start_addr
= virt_memmap
[VIRT_FLASH
].base
;
1291 fdt_load_addr
= riscv_compute_fdt_addr(memmap
[VIRT_DRAM
].base
,
1292 memmap
[VIRT_DRAM
].size
,
1294 riscv_load_fdt(fdt_load_addr
, machine
->fdt
);
1296 /* load the reset vector */
1297 riscv_setup_rom_reset_vec(machine
, &s
->soc
[0], start_addr
,
1298 virt_memmap
[VIRT_MROM
].base
,
1299 virt_memmap
[VIRT_MROM
].size
, kernel_entry
,
1303 * Only direct boot kernel is currently supported for KVM VM,
1304 * So here setup kernel start address and fdt address.
1305 * TODO:Support firmware loading and integrate to TCG start
1307 if (kvm_enabled()) {
1308 riscv_setup_direct_kernel(kernel_entry
, fdt_load_addr
);
1312 static void virt_machine_init(MachineState
*machine
)
1314 const MemMapEntry
*memmap
= virt_memmap
;
1315 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(machine
);
1316 MemoryRegion
*system_memory
= get_system_memory();
1317 MemoryRegion
*mask_rom
= g_new(MemoryRegion
, 1);
1319 DeviceState
*mmio_irqchip
, *virtio_irqchip
, *pcie_irqchip
;
1320 int i
, base_hartid
, hart_count
;
1321 int socket_count
= riscv_socket_count(machine
);
1323 /* Check socket count limit */
1324 if (VIRT_SOCKETS_MAX
< socket_count
) {
1325 error_report("number of sockets/nodes should be less than %d",
1330 /* Initialize sockets */
1331 mmio_irqchip
= virtio_irqchip
= pcie_irqchip
= NULL
;
1332 for (i
= 0; i
< socket_count
; i
++) {
1333 if (!riscv_socket_check_hartids(machine
, i
)) {
1334 error_report("discontinuous hartids in socket%d", i
);
1338 base_hartid
= riscv_socket_first_hartid(machine
, i
);
1339 if (base_hartid
< 0) {
1340 error_report("can't find hartid base for socket%d", i
);
1344 hart_count
= riscv_socket_hart_count(machine
, i
);
1345 if (hart_count
< 0) {
1346 error_report("can't find hart count for socket%d", i
);
1350 soc_name
= g_strdup_printf("soc%d", i
);
1351 object_initialize_child(OBJECT(machine
), soc_name
, &s
->soc
[i
],
1352 TYPE_RISCV_HART_ARRAY
);
1354 object_property_set_str(OBJECT(&s
->soc
[i
]), "cpu-type",
1355 machine
->cpu_type
, &error_abort
);
1356 object_property_set_int(OBJECT(&s
->soc
[i
]), "hartid-base",
1357 base_hartid
, &error_abort
);
1358 object_property_set_int(OBJECT(&s
->soc
[i
]), "num-harts",
1359 hart_count
, &error_abort
);
1360 sysbus_realize(SYS_BUS_DEVICE(&s
->soc
[i
]), &error_fatal
);
1362 if (!kvm_enabled()) {
1363 if (s
->have_aclint
) {
1364 if (s
->aia_type
== VIRT_AIA_TYPE_APLIC_IMSIC
) {
1365 /* Per-socket ACLINT MTIMER */
1366 riscv_aclint_mtimer_create(memmap
[VIRT_CLINT
].base
+
1367 i
* RISCV_ACLINT_DEFAULT_MTIMER_SIZE
,
1368 RISCV_ACLINT_DEFAULT_MTIMER_SIZE
,
1369 base_hartid
, hart_count
,
1370 RISCV_ACLINT_DEFAULT_MTIMECMP
,
1371 RISCV_ACLINT_DEFAULT_MTIME
,
1372 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ
, true);
1374 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
1375 riscv_aclint_swi_create(memmap
[VIRT_CLINT
].base
+
1376 i
* memmap
[VIRT_CLINT
].size
,
1377 base_hartid
, hart_count
, false);
1378 riscv_aclint_mtimer_create(memmap
[VIRT_CLINT
].base
+
1379 i
* memmap
[VIRT_CLINT
].size
+
1380 RISCV_ACLINT_SWI_SIZE
,
1381 RISCV_ACLINT_DEFAULT_MTIMER_SIZE
,
1382 base_hartid
, hart_count
,
1383 RISCV_ACLINT_DEFAULT_MTIMECMP
,
1384 RISCV_ACLINT_DEFAULT_MTIME
,
1385 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ
, true);
1386 riscv_aclint_swi_create(memmap
[VIRT_ACLINT_SSWI
].base
+
1387 i
* memmap
[VIRT_ACLINT_SSWI
].size
,
1388 base_hartid
, hart_count
, true);
1391 /* Per-socket SiFive CLINT */
1392 riscv_aclint_swi_create(
1393 memmap
[VIRT_CLINT
].base
+ i
* memmap
[VIRT_CLINT
].size
,
1394 base_hartid
, hart_count
, false);
1395 riscv_aclint_mtimer_create(memmap
[VIRT_CLINT
].base
+
1396 i
* memmap
[VIRT_CLINT
].size
+ RISCV_ACLINT_SWI_SIZE
,
1397 RISCV_ACLINT_DEFAULT_MTIMER_SIZE
, base_hartid
, hart_count
,
1398 RISCV_ACLINT_DEFAULT_MTIMECMP
, RISCV_ACLINT_DEFAULT_MTIME
,
1399 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ
, true);
1403 /* Per-socket interrupt controller */
1404 if (s
->aia_type
== VIRT_AIA_TYPE_NONE
) {
1405 s
->irqchip
[i
] = virt_create_plic(memmap
, i
,
1406 base_hartid
, hart_count
);
1408 s
->irqchip
[i
] = virt_create_aia(s
->aia_type
, s
->aia_guests
,
1409 memmap
, i
, base_hartid
,
1413 /* Try to use different IRQCHIP instance based device type */
1415 mmio_irqchip
= s
->irqchip
[i
];
1416 virtio_irqchip
= s
->irqchip
[i
];
1417 pcie_irqchip
= s
->irqchip
[i
];
1420 virtio_irqchip
= s
->irqchip
[i
];
1421 pcie_irqchip
= s
->irqchip
[i
];
1424 pcie_irqchip
= s
->irqchip
[i
];
1428 if (riscv_is_32bit(&s
->soc
[0])) {
1429 #if HOST_LONG_BITS == 64
1430 /* limit RAM size in a 32-bit system */
1431 if (machine
->ram_size
> 10 * GiB
) {
1432 machine
->ram_size
= 10 * GiB
;
1433 error_report("Limiting RAM size to 10 GiB");
1436 virt_high_pcie_memmap
.base
= VIRT32_HIGH_PCIE_MMIO_BASE
;
1437 virt_high_pcie_memmap
.size
= VIRT32_HIGH_PCIE_MMIO_SIZE
;
1439 virt_high_pcie_memmap
.size
= VIRT64_HIGH_PCIE_MMIO_SIZE
;
1440 virt_high_pcie_memmap
.base
= memmap
[VIRT_DRAM
].base
+ machine
->ram_size
;
1441 virt_high_pcie_memmap
.base
=
1442 ROUND_UP(virt_high_pcie_memmap
.base
, virt_high_pcie_memmap
.size
);
1445 /* register system main memory (actual RAM) */
1446 memory_region_add_subregion(system_memory
, memmap
[VIRT_DRAM
].base
,
1450 memory_region_init_rom(mask_rom
, NULL
, "riscv_virt_board.mrom",
1451 memmap
[VIRT_MROM
].size
, &error_fatal
);
1452 memory_region_add_subregion(system_memory
, memmap
[VIRT_MROM
].base
,
1456 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the
1457 * device tree cannot be altered and we get FDT_ERR_NOSPACE.
1459 s
->fw_cfg
= create_fw_cfg(machine
);
1460 rom_set_fw(s
->fw_cfg
);
1462 /* SiFive Test MMIO device */
1463 sifive_test_create(memmap
[VIRT_TEST
].base
);
1465 /* VirtIO MMIO devices */
1466 for (i
= 0; i
< VIRTIO_COUNT
; i
++) {
1467 sysbus_create_simple("virtio-mmio",
1468 memmap
[VIRT_VIRTIO
].base
+ i
* memmap
[VIRT_VIRTIO
].size
,
1469 qdev_get_gpio_in(DEVICE(virtio_irqchip
), VIRTIO_IRQ
+ i
));
1472 gpex_pcie_init(system_memory
,
1473 memmap
[VIRT_PCIE_ECAM
].base
,
1474 memmap
[VIRT_PCIE_ECAM
].size
,
1475 memmap
[VIRT_PCIE_MMIO
].base
,
1476 memmap
[VIRT_PCIE_MMIO
].size
,
1477 virt_high_pcie_memmap
.base
,
1478 virt_high_pcie_memmap
.size
,
1479 memmap
[VIRT_PCIE_PIO
].base
,
1480 DEVICE(pcie_irqchip
));
1482 create_platform_bus(s
, DEVICE(mmio_irqchip
));
1484 serial_mm_init(system_memory
, memmap
[VIRT_UART0
].base
,
1485 0, qdev_get_gpio_in(DEVICE(mmio_irqchip
), UART0_IRQ
), 399193,
1486 serial_hd(0), DEVICE_LITTLE_ENDIAN
);
1488 sysbus_create_simple("goldfish_rtc", memmap
[VIRT_RTC
].base
,
1489 qdev_get_gpio_in(DEVICE(mmio_irqchip
), RTC_IRQ
));
1491 virt_flash_create(s
);
1493 for (i
= 0; i
< ARRAY_SIZE(s
->flash
); i
++) {
1494 /* Map legacy -drive if=pflash to machine properties */
1495 pflash_cfi01_legacy_drive(s
->flash
[i
],
1496 drive_get(IF_PFLASH
, 0, i
));
1498 virt_flash_map(s
, system_memory
);
1500 /* load/create device tree */
1502 machine
->fdt
= load_device_tree(machine
->dtb
, &s
->fdt_size
);
1503 if (!machine
->fdt
) {
1504 error_report("load_device_tree() failed");
1508 create_fdt(s
, memmap
);
1511 s
->machine_done
.notify
= virt_machine_done
;
1512 qemu_add_machine_init_done_notifier(&s
->machine_done
);
1515 static void virt_machine_instance_init(Object
*obj
)
1519 static char *virt_get_aia_guests(Object
*obj
, Error
**errp
)
1521 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1524 sprintf(val
, "%d", s
->aia_guests
);
1525 return g_strdup(val
);
1528 static void virt_set_aia_guests(Object
*obj
, const char *val
, Error
**errp
)
1530 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1532 s
->aia_guests
= atoi(val
);
1533 if (s
->aia_guests
< 0 || s
->aia_guests
> VIRT_IRQCHIP_MAX_GUESTS
) {
1534 error_setg(errp
, "Invalid number of AIA IMSIC guests");
1535 error_append_hint(errp
, "Valid values be between 0 and %d.\n",
1536 VIRT_IRQCHIP_MAX_GUESTS
);
1540 static char *virt_get_aia(Object
*obj
, Error
**errp
)
1542 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1545 switch (s
->aia_type
) {
1546 case VIRT_AIA_TYPE_APLIC
:
1549 case VIRT_AIA_TYPE_APLIC_IMSIC
:
1550 val
= "aplic-imsic";
1557 return g_strdup(val
);
1560 static void virt_set_aia(Object
*obj
, const char *val
, Error
**errp
)
1562 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1564 if (!strcmp(val
, "none")) {
1565 s
->aia_type
= VIRT_AIA_TYPE_NONE
;
1566 } else if (!strcmp(val
, "aplic")) {
1567 s
->aia_type
= VIRT_AIA_TYPE_APLIC
;
1568 } else if (!strcmp(val
, "aplic-imsic")) {
1569 s
->aia_type
= VIRT_AIA_TYPE_APLIC_IMSIC
;
1571 error_setg(errp
, "Invalid AIA interrupt controller type");
1572 error_append_hint(errp
, "Valid values are none, aplic, and "
1577 static bool virt_get_aclint(Object
*obj
, Error
**errp
)
1579 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1581 return s
->have_aclint
;
1584 static void virt_set_aclint(Object
*obj
, bool value
, Error
**errp
)
1586 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(obj
);
1588 s
->have_aclint
= value
;
1591 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
1594 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1596 if (device_is_dynamic_sysbus(mc
, dev
)) {
1597 return HOTPLUG_HANDLER(machine
);
1602 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
1603 DeviceState
*dev
, Error
**errp
)
1605 RISCVVirtState
*s
= RISCV_VIRT_MACHINE(hotplug_dev
);
1607 if (s
->platform_bus_dev
) {
1608 MachineClass
*mc
= MACHINE_GET_CLASS(s
);
1610 if (device_is_dynamic_sysbus(mc
, dev
)) {
1611 platform_bus_link_device(PLATFORM_BUS_DEVICE(s
->platform_bus_dev
),
1612 SYS_BUS_DEVICE(dev
));
1617 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1620 MachineClass
*mc
= MACHINE_CLASS(oc
);
1621 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
1623 mc
->desc
= "RISC-V VirtIO board";
1624 mc
->init
= virt_machine_init
;
1625 mc
->max_cpus
= VIRT_CPUS_MAX
;
1626 mc
->default_cpu_type
= TYPE_RISCV_CPU_BASE
;
1627 mc
->pci_allow_0_address
= true;
1628 mc
->possible_cpu_arch_ids
= riscv_numa_possible_cpu_arch_ids
;
1629 mc
->cpu_index_to_instance_props
= riscv_numa_cpu_index_to_props
;
1630 mc
->get_default_cpu_node_id
= riscv_numa_get_default_cpu_node_id
;
1631 mc
->numa_mem_supported
= true;
1632 mc
->default_ram_id
= "riscv_virt_board.ram";
1633 assert(!mc
->get_hotplug_handler
);
1634 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
1636 hc
->plug
= virt_machine_device_plug_cb
;
1638 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
1640 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
1643 object_class_property_add_bool(oc
, "aclint", virt_get_aclint
,
1645 object_class_property_set_description(oc
, "aclint",
1646 "Set on/off to enable/disable "
1647 "emulating ACLINT devices");
1649 object_class_property_add_str(oc
, "aia", virt_get_aia
,
1651 object_class_property_set_description(oc
, "aia",
1652 "Set type of AIA interrupt "
1653 "conttoller. Valid values are "
1654 "none, aplic, and aplic-imsic.");
1656 object_class_property_add_str(oc
, "aia-guests",
1657 virt_get_aia_guests
,
1658 virt_set_aia_guests
);
1659 sprintf(str
, "Set number of guest MMIO pages for AIA IMSIC. Valid value "
1660 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS
);
1661 object_class_property_set_description(oc
, "aia-guests", str
);
1664 static const TypeInfo virt_machine_typeinfo
= {
1665 .name
= MACHINE_TYPE_NAME("virt"),
1666 .parent
= TYPE_MACHINE
,
1667 .class_init
= virt_machine_class_init
,
1668 .instance_init
= virt_machine_instance_init
,
1669 .instance_size
= sizeof(RISCVVirtState
),
1670 .interfaces
= (InterfaceInfo
[]) {
1671 { TYPE_HOTPLUG_HANDLER
},
1676 static void virt_machine_init_register_types(void)
1678 type_register_static(&virt_machine_typeinfo
);
1681 type_init(virt_machine_init_register_types
)