hw/riscv/virt.c

   1 /*
   2  * QEMU RISC-V VirtIO Board
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * RISC-V machine with 16550a UART and VirtIO MMIO
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/units.h"
  23 #include "qemu/log.h"
  24 #include "qemu/error-report.h"
  25 #include "qapi/error.h"
  26 #include "hw/boards.h"
  27 #include "hw/loader.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/qdev-properties.h"
  30 #include "hw/char/serial.h"
  31 #include "target/riscv/cpu.h"
  32 #include "hw/riscv/riscv_hart.h"
  33 #include "hw/riscv/sifive_plic.h"
  34 #include "hw/riscv/sifive_clint.h"
  35 #include "hw/riscv/sifive_test.h"
  36 #include "hw/riscv/virt.h"
  37 #include "hw/riscv/boot.h"
  38 #include "chardev/char.h"
  39 #include "sysemu/arch_init.h"
  40 #include "sysemu/device_tree.h"
  41 #include "sysemu/sysemu.h"
  42 #include "exec/address-spaces.h"
  43 #include "hw/pci/pci.h"
  44 #include "hw/pci-host/gpex.h"
  45
  46 #include <libfdt.h>
  47
  48 #if defined(TARGET_RISCV32)
  49 # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin"
  50 #else
  51 # define BIOS_FILENAME "opensbi-riscv64-virt-fw_jump.bin"
  52 #endif
  53
  54 static const struct MemmapEntry {
  55     hwaddr base;
  56     hwaddr size;
  57 } virt_memmap[] = {
  58     [VIRT_DEBUG] =       {        0x0,         0x100 },
  59     [VIRT_MROM] =        {     0x1000,       0x11000 },
  60     [VIRT_TEST] =        {   0x100000,        0x1000 },
  61     [VIRT_CLINT] =       {  0x2000000,       0x10000 },
  62     [VIRT_PLIC] =        {  0xc000000,     0x4000000 },
  63     [VIRT_UART0] =       { 0x10000000,         0x100 },
  64     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
  65     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
  66     [VIRT_DRAM] =        { 0x80000000,           0x0 },
  67     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
  68     [VIRT_PCIE_PIO] =    { 0x03000000,    0x00010000 },
  69     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
  70 };
  71
  72 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
  73
  74 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
  75                                        const char *name,
  76                                        const char *alias_prop_name)
  77 {
  78     /*
  79      * Create a single flash device.  We use the same parameters as
  80      * the flash devices on the ARM virt board.
  81      */
  82     DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
  83
  84     qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
  85     qdev_prop_set_uint8(dev, "width", 4);
  86     qdev_prop_set_uint8(dev, "device-width", 2);
  87     qdev_prop_set_bit(dev, "big-endian", false);
  88     qdev_prop_set_uint16(dev, "id0", 0x89);
  89     qdev_prop_set_uint16(dev, "id1", 0x18);
  90     qdev_prop_set_uint16(dev, "id2", 0x00);
  91     qdev_prop_set_uint16(dev, "id3", 0x00);
  92     qdev_prop_set_string(dev, "name", name);
  93
  94     object_property_add_child(OBJECT(s), name, OBJECT(dev),
  95                               &error_abort);
  96     object_property_add_alias(OBJECT(s), alias_prop_name,
  97                               OBJECT(dev), "drive", &error_abort);
  98
  99     return PFLASH_CFI01(dev);
 100 }
 101
 102 static void virt_flash_create(RISCVVirtState *s)
 103 {
 104     s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
 105     s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
 106 }
 107
 108 static void virt_flash_map1(PFlashCFI01 *flash,
 109                             hwaddr base, hwaddr size,
 110                             MemoryRegion *sysmem)
 111 {
 112     DeviceState *dev = DEVICE(flash);
 113
 114     assert(size % VIRT_FLASH_SECTOR_SIZE == 0);
 115     assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
 116     qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
 117     qdev_init_nofail(dev);
 118
 119     memory_region_add_subregion(sysmem, base,
 120                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
 121                                                        0));
 122 }
 123
 124 static void virt_flash_map(RISCVVirtState *s,
 125                            MemoryRegion *sysmem)
 126 {
 127     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
 128     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
 129
 130     virt_flash_map1(s->flash[0], flashbase, flashsize,
 131                     sysmem);
 132     virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
 133                     sysmem);
 134 }
 135
 136 static void create_pcie_irq_map(void *fdt, char *nodename,
 137                                 uint32_t plic_phandle)
 138 {
 139     int pin, dev;
 140     uint32_t
 141         full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
 142     uint32_t *irq_map = full_irq_map;
 143
 144     /* This code creates a standard swizzle of interrupts such that
 145      * each device's first interrupt is based on it's PCI_SLOT number.
 146      * (See pci_swizzle_map_irq_fn())
 147      *
 148      * We only need one entry per interrupt in the table (not one per
 149      * possible slot) seeing the interrupt-map-mask will allow the table
 150      * to wrap to any number of devices.
 151      */
 152     for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
 153         int devfn = dev * 0x8;
 154
 155         for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
 156             int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
 157             int i = 0;
 158
 159             irq_map[i] = cpu_to_be32(devfn << 8);
 160
 161             i += FDT_PCI_ADDR_CELLS;
 162             irq_map[i] = cpu_to_be32(pin + 1);
 163
 164             i += FDT_PCI_INT_CELLS;
 165             irq_map[i++] = cpu_to_be32(plic_phandle);
 166
 167             i += FDT_PLIC_ADDR_CELLS;
 168             irq_map[i] = cpu_to_be32(irq_nr);
 169
 170             irq_map += FDT_INT_MAP_WIDTH;
 171         }
 172     }
 173
 174     qemu_fdt_setprop(fdt, nodename, "interrupt-map",
 175                      full_irq_map, sizeof(full_irq_map));
 176
 177     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
 178                            0x1800, 0, 0, 0x7);
 179 }
 180
 181 static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
 182     uint64_t mem_size, const char *cmdline)
 183 {
 184     void *fdt;
 185     int cpu;
 186     uint32_t *cells;
 187     char *nodename;
 188     uint32_t plic_phandle, phandle = 1;
 189     int i;
 190     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
 191     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
 192
 193     fdt = s->fdt = create_device_tree(&s->fdt_size);
 194     if (!fdt) {
 195         error_report("create_device_tree() failed");
 196         exit(1);
 197     }
 198
 199     qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
 200     qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
 201     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 202     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 203
 204     qemu_fdt_add_subnode(fdt, "/soc");
 205     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 206     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
 207     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 208     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 209
 210     nodename = g_strdup_printf("/memory@%lx",
 211         (long)memmap[VIRT_DRAM].base);
 212     qemu_fdt_add_subnode(fdt, nodename);
 213     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 214         memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
 215         mem_size >> 32, mem_size);
 216     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 217     g_free(nodename);
 218
 219     qemu_fdt_add_subnode(fdt, "/cpus");
 220     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 221                           SIFIVE_CLINT_TIMEBASE_FREQ);
 222     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 223     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 224
 225     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 226         int cpu_phandle = phandle++;
 227         int intc_phandle;
 228         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 229         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 230         char *isa = riscv_isa_string(&s->soc.harts[cpu]);
 231         qemu_fdt_add_subnode(fdt, nodename);
 232         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 233         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 234         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 235         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 236         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 237         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 238         qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
 239         intc_phandle = phandle++;
 240         qemu_fdt_add_subnode(fdt, intc);
 241         qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
 242         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 243         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 244         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 245         g_free(isa);
 246         g_free(intc);
 247         g_free(nodename);
 248     }
 249
 250     /* Add cpu-topology node */
 251     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
 252     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
 253     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 254         char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
 255                                               cpu);
 256         char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 257         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
 258         qemu_fdt_add_subnode(fdt, core_nodename);
 259         qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
 260         g_free(core_nodename);
 261         g_free(cpu_nodename);
 262     }
 263
 264     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 265     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 266         nodename =
 267             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 268         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 269         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 270         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 271         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 272         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 273         g_free(nodename);
 274     }
 275     nodename = g_strdup_printf("/soc/clint@%lx",
 276         (long)memmap[VIRT_CLINT].base);
 277     qemu_fdt_add_subnode(fdt, nodename);
 278     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 279     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 280         0x0, memmap[VIRT_CLINT].base,
 281         0x0, memmap[VIRT_CLINT].size);
 282     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 283         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 284     g_free(cells);
 285     g_free(nodename);
 286
 287     plic_phandle = phandle++;
 288     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 289     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 290         nodename =
 291             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 292         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 293         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 294         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 295         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 296         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 297         g_free(nodename);
 298     }
 299     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 300         (long)memmap[VIRT_PLIC].base);
 301     qemu_fdt_add_subnode(fdt, nodename);
 302     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
 303                           FDT_PLIC_ADDR_CELLS);
 304     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
 305                           FDT_PLIC_INT_CELLS);
 306     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
 307     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 308     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 309         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 310     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 311         0x0, memmap[VIRT_PLIC].base,
 312         0x0, memmap[VIRT_PLIC].size);
 313     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
 314     qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 315     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 316     g_free(cells);
 317     g_free(nodename);
 318
 319     for (i = 0; i < VIRTIO_COUNT; i++) {
 320         nodename = g_strdup_printf("/virtio_mmio@%lx",
 321             (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
 322         qemu_fdt_add_subnode(fdt, nodename);
 323         qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
 324         qemu_fdt_setprop_cells(fdt, nodename, "reg",
 325             0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 326             0x0, memmap[VIRT_VIRTIO].size);
 327         qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 328         qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
 329         g_free(nodename);
 330     }
 331
 332     nodename = g_strdup_printf("/soc/pci@%lx",
 333         (long) memmap[VIRT_PCIE_ECAM].base);
 334     qemu_fdt_add_subnode(fdt, nodename);
 335     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
 336                           FDT_PCI_ADDR_CELLS);
 337     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
 338                           FDT_PCI_INT_CELLS);
 339     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2);
 340     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 341                             "pci-host-ecam-generic");
 342     qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
 343     qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
 344     qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
 345                            memmap[VIRT_PCIE_ECAM].size /
 346                                PCIE_MMCFG_SIZE_MIN - 1);
 347     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
 348     qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
 349                            0, memmap[VIRT_PCIE_ECAM].size);
 350     qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
 351         1, FDT_PCI_RANGE_IOPORT, 2, 0,
 352         2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
 353         1, FDT_PCI_RANGE_MMIO,
 354         2, memmap[VIRT_PCIE_MMIO].base,
 355         2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
 356     create_pcie_irq_map(fdt, nodename, plic_phandle);
 357     g_free(nodename);
 358
 359     nodename = g_strdup_printf("/test@%lx",
 360         (long)memmap[VIRT_TEST].base);
 361     qemu_fdt_add_subnode(fdt, nodename);
 362     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0");
 363     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 364         0x0, memmap[VIRT_TEST].base,
 365         0x0, memmap[VIRT_TEST].size);
 366     g_free(nodename);
 367
 368     nodename = g_strdup_printf("/uart@%lx",
 369         (long)memmap[VIRT_UART0].base);
 370     qemu_fdt_add_subnode(fdt, nodename);
 371     qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
 372     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 373         0x0, memmap[VIRT_UART0].base,
 374         0x0, memmap[VIRT_UART0].size);
 375     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
 376     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 377     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ);
 378
 379     qemu_fdt_add_subnode(fdt, "/chosen");
 380     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 381     if (cmdline) {
 382         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 383     }
 384     g_free(nodename);
 385
 386     nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
 387     qemu_fdt_add_subnode(s->fdt, nodename);
 388     qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash");
 389     qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
 390                                  2, flashbase, 2, flashsize,
 391                                  2, flashbase + flashsize, 2, flashsize);
 392     qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4);
 393     g_free(nodename);
 394 }
 395
 396
 397 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
 398                                           hwaddr ecam_base, hwaddr ecam_size,
 399                                           hwaddr mmio_base, hwaddr mmio_size,
 400                                           hwaddr pio_base,
 401                                           DeviceState *plic, bool link_up)
 402 {
 403     DeviceState *dev;
 404     MemoryRegion *ecam_alias, *ecam_reg;
 405     MemoryRegion *mmio_alias, *mmio_reg;
 406     qemu_irq irq;
 407     int i;
 408
 409     dev = qdev_create(NULL, TYPE_GPEX_HOST);
 410
 411     qdev_init_nofail(dev);
 412
 413     ecam_alias = g_new0(MemoryRegion, 1);
 414     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 415     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
 416                              ecam_reg, 0, ecam_size);
 417     memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
 418
 419     mmio_alias = g_new0(MemoryRegion, 1);
 420     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
 421     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
 422                              mmio_reg, mmio_base, mmio_size);
 423     memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
 424
 425     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
 426
 427     for (i = 0; i < GPEX_NUM_IRQS; i++) {
 428         irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
 429
 430         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
 431         gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
 432     }
 433
 434     return dev;
 435 }
 436
 437 static void riscv_virt_board_init(MachineState *machine)
 438 {
 439     const struct MemmapEntry *memmap = virt_memmap;
 440     RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
 441     MemoryRegion *system_memory = get_system_memory();
 442     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 443     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 444     char *plic_hart_config;
 445     size_t plic_hart_config_len;
 446     target_ulong start_addr = memmap[VIRT_DRAM].base;
 447     int i;
 448     unsigned int smp_cpus = machine->smp.cpus;
 449
 450     /* Initialize SOC */
 451     object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
 452                             TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
 453     object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
 454                             &error_abort);
 455     object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
 456                             &error_abort);
 457     object_property_set_bool(OBJECT(&s->soc), true, "realized",
 458                             &error_abort);
 459
 460     /* register system main memory (actual RAM) */
 461     memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
 462                            machine->ram_size, &error_fatal);
 463     memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
 464         main_mem);
 465
 466     /* create device tree */
 467     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 468
 469     /* boot rom */
 470     memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
 471                            memmap[VIRT_MROM].size, &error_fatal);
 472     memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
 473                                 mask_rom);
 474
 475     riscv_find_and_load_firmware(machine, BIOS_FILENAME,
 476                                  memmap[VIRT_DRAM].base);
 477
 478     if (machine->kernel_filename) {
 479         uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
 480
 481         if (machine->initrd_filename) {
 482             hwaddr start;
 483             hwaddr end = riscv_load_initrd(machine->initrd_filename,
 484                                            machine->ram_size, kernel_entry,
 485                                            &start);
 486             qemu_fdt_setprop_cell(s->fdt, "/chosen",
 487                                   "linux,initrd-start", start);
 488             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 489                                   end);
 490         }
 491     }
 492
 493     if (drive_get(IF_PFLASH, 0, 0)) {
 494         /*
 495          * Pflash was supplied, let's overwrite the address we jump to after
 496          * reset to the base of the flash.
 497          */
 498         start_addr = virt_memmap[VIRT_FLASH].base;
 499     }
 500
 501     /* reset vector */
 502     uint32_t reset_vec[8] = {
 503         0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
 504         0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
 505         0xf1402573,                  /*     csrr   a0, mhartid  */
 506 #if defined(TARGET_RISCV32)
 507         0x0182a283,                  /*     lw     t0, 24(t0) */
 508 #elif defined(TARGET_RISCV64)
 509         0x0182b283,                  /*     ld     t0, 24(t0) */
 510 #endif
 511         0x00028067,                  /*     jr     t0 */
 512         0x00000000,
 513         start_addr,                  /* start: .dword */
 514         0x00000000,
 515                                      /* dtb: */
 516     };
 517
 518     /* copy in the reset vector in little_endian byte order */
 519     for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 520         reset_vec[i] = cpu_to_le32(reset_vec[i]);
 521     }
 522     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 523                           memmap[VIRT_MROM].base, &address_space_memory);
 524
 525     /* copy in the device tree */
 526     if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
 527             memmap[VIRT_MROM].size - sizeof(reset_vec)) {
 528         error_report("not enough space to store device-tree");
 529         exit(1);
 530     }
 531     qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
 532     rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
 533                           memmap[VIRT_MROM].base + sizeof(reset_vec),
 534                           &address_space_memory);
 535
 536     /* create PLIC hart topology configuration string */
 537     plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
 538     plic_hart_config = g_malloc0(plic_hart_config_len);
 539     for (i = 0; i < smp_cpus; i++) {
 540         if (i != 0) {
 541             strncat(plic_hart_config, ",", plic_hart_config_len);
 542         }
 543         strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
 544         plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
 545     }
 546
 547     /* MMIO */
 548     s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
 549         plic_hart_config,
 550         VIRT_PLIC_NUM_SOURCES,
 551         VIRT_PLIC_NUM_PRIORITIES,
 552         VIRT_PLIC_PRIORITY_BASE,
 553         VIRT_PLIC_PENDING_BASE,
 554         VIRT_PLIC_ENABLE_BASE,
 555         VIRT_PLIC_ENABLE_STRIDE,
 556         VIRT_PLIC_CONTEXT_BASE,
 557         VIRT_PLIC_CONTEXT_STRIDE,
 558         memmap[VIRT_PLIC].size);
 559     sifive_clint_create(memmap[VIRT_CLINT].base,
 560         memmap[VIRT_CLINT].size, smp_cpus,
 561         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 562     sifive_test_create(memmap[VIRT_TEST].base);
 563
 564     for (i = 0; i < VIRTIO_COUNT; i++) {
 565         sysbus_create_simple("virtio-mmio",
 566             memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 567             qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
 568     }
 569
 570     gpex_pcie_init(system_memory,
 571                          memmap[VIRT_PCIE_ECAM].base,
 572                          memmap[VIRT_PCIE_ECAM].size,
 573                          memmap[VIRT_PCIE_MMIO].base,
 574                          memmap[VIRT_PCIE_MMIO].size,
 575                          memmap[VIRT_PCIE_PIO].base,
 576                          DEVICE(s->plic), true);
 577
 578     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
 579         0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
 580         serial_hd(0), DEVICE_LITTLE_ENDIAN);
 581
 582     virt_flash_create(s);
 583
 584     for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
 585         /* Map legacy -drive if=pflash to machine properties */
 586         pflash_cfi01_legacy_drive(s->flash[i],
 587                                   drive_get(IF_PFLASH, 0, i));
 588     }
 589     virt_flash_map(s, system_memory);
 590
 591     g_free(plic_hart_config);
 592 }
 593
 594 static void riscv_virt_machine_instance_init(Object *obj)
 595 {
 596 }
 597
 598 static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
 599 {
 600     MachineClass *mc = MACHINE_CLASS(oc);
 601
 602     mc->desc = "RISC-V VirtIO board";
 603     mc->init = riscv_virt_board_init;
 604     mc->max_cpus = 8;
 605     mc->default_cpu_type = VIRT_CPU;
 606 }
 607
 608 static const TypeInfo riscv_virt_machine_typeinfo = {
 609     .name       = MACHINE_TYPE_NAME("virt"),
 610     .parent     = TYPE_MACHINE,
 611     .class_init = riscv_virt_machine_class_init,
 612     .instance_init = riscv_virt_machine_instance_init,
 613     .instance_size = sizeof(RISCVVirtState),
 614 };
 615
 616 static void riscv_virt_machine_init_register_types(void)
 617 {
 618     type_register_static(&riscv_virt_machine_typeinfo);
 619 }
 620
 621 type_init(riscv_virt_machine_init_register_types)