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hw/riscv: virt: fix syscon subnode paths
[mirror_qemu.git] / hw / riscv / virt.c
1 /*
2 * QEMU RISC-V VirtIO Board
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * RISC-V machine with 16550a UART and VirtIO MMIO
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
25 #include "qapi/error.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/sysbus.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial.h"
31 #include "target/riscv/cpu.h"
32 #include "hw/core/sysbus-fdt.h"
33 #include "hw/riscv/riscv_hart.h"
34 #include "hw/riscv/virt.h"
35 #include "hw/riscv/boot.h"
36 #include "hw/riscv/numa.h"
37 #include "hw/intc/riscv_aclint.h"
38 #include "hw/intc/riscv_aplic.h"
39 #include "hw/intc/riscv_imsic.h"
40 #include "hw/intc/sifive_plic.h"
41 #include "hw/misc/sifive_test.h"
42 #include "hw/platform-bus.h"
43 #include "chardev/char.h"
44 #include "sysemu/device_tree.h"
45 #include "sysemu/sysemu.h"
46 #include "sysemu/kvm.h"
47 #include "sysemu/tpm.h"
48 #include "hw/pci/pci.h"
49 #include "hw/pci-host/gpex.h"
50 #include "hw/display/ramfb.h"
51
52 /*
53 * The virt machine physical address space used by some of the devices
54 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
55 * number of CPUs, and number of IMSIC guest files.
56 *
57 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
58 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
59 * of virt machine physical address space.
60 */
61
62 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
63 #if VIRT_IMSIC_GROUP_MAX_SIZE < \
64 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
65 #error "Can't accomodate single IMSIC group in address space"
66 #endif
67
68 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \
69 VIRT_IMSIC_GROUP_MAX_SIZE)
70 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE
71 #error "Can't accomodate all IMSIC groups in address space"
72 #endif
73
74 static const MemMapEntry virt_memmap[] = {
75 [VIRT_DEBUG] = { 0x0, 0x100 },
76 [VIRT_MROM] = { 0x1000, 0xf000 },
77 [VIRT_TEST] = { 0x100000, 0x1000 },
78 [VIRT_RTC] = { 0x101000, 0x1000 },
79 [VIRT_CLINT] = { 0x2000000, 0x10000 },
80 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
81 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
82 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 },
83 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
84 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
85 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
86 [VIRT_UART0] = { 0x10000000, 0x100 },
87 [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
88 [VIRT_FW_CFG] = { 0x10100000, 0x18 },
89 [VIRT_FLASH] = { 0x20000000, 0x4000000 },
90 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
91 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE },
92 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
93 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
94 [VIRT_DRAM] = { 0x80000000, 0x0 },
95 };
96
97 /* PCIe high mmio is fixed for RV32 */
98 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
99 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
100
101 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
102 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
103
104 static MemMapEntry virt_high_pcie_memmap;
105
106 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
107
108 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
109 const char *name,
110 const char *alias_prop_name)
111 {
112 /*
113 * Create a single flash device. We use the same parameters as
114 * the flash devices on the ARM virt board.
115 */
116 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
117
118 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
119 qdev_prop_set_uint8(dev, "width", 4);
120 qdev_prop_set_uint8(dev, "device-width", 2);
121 qdev_prop_set_bit(dev, "big-endian", false);
122 qdev_prop_set_uint16(dev, "id0", 0x89);
123 qdev_prop_set_uint16(dev, "id1", 0x18);
124 qdev_prop_set_uint16(dev, "id2", 0x00);
125 qdev_prop_set_uint16(dev, "id3", 0x00);
126 qdev_prop_set_string(dev, "name", name);
127
128 object_property_add_child(OBJECT(s), name, OBJECT(dev));
129 object_property_add_alias(OBJECT(s), alias_prop_name,
130 OBJECT(dev), "drive");
131
132 return PFLASH_CFI01(dev);
133 }
134
135 static void virt_flash_create(RISCVVirtState *s)
136 {
137 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
138 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
139 }
140
141 static void virt_flash_map1(PFlashCFI01 *flash,
142 hwaddr base, hwaddr size,
143 MemoryRegion *sysmem)
144 {
145 DeviceState *dev = DEVICE(flash);
146
147 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
148 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
149 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
150 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
151
152 memory_region_add_subregion(sysmem, base,
153 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
154 0));
155 }
156
157 static void virt_flash_map(RISCVVirtState *s,
158 MemoryRegion *sysmem)
159 {
160 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
161 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
162
163 virt_flash_map1(s->flash[0], flashbase, flashsize,
164 sysmem);
165 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
166 sysmem);
167 }
168
169 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
170 uint32_t irqchip_phandle)
171 {
172 int pin, dev;
173 uint32_t irq_map_stride = 0;
174 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS *
175 FDT_MAX_INT_MAP_WIDTH] = {};
176 uint32_t *irq_map = full_irq_map;
177
178 /* This code creates a standard swizzle of interrupts such that
179 * each device's first interrupt is based on it's PCI_SLOT number.
180 * (See pci_swizzle_map_irq_fn())
181 *
182 * We only need one entry per interrupt in the table (not one per
183 * possible slot) seeing the interrupt-map-mask will allow the table
184 * to wrap to any number of devices.
185 */
186 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
187 int devfn = dev * 0x8;
188
189 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
190 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
191 int i = 0;
192
193 /* Fill PCI address cells */
194 irq_map[i] = cpu_to_be32(devfn << 8);
195 i += FDT_PCI_ADDR_CELLS;
196
197 /* Fill PCI Interrupt cells */
198 irq_map[i] = cpu_to_be32(pin + 1);
199 i += FDT_PCI_INT_CELLS;
200
201 /* Fill interrupt controller phandle and cells */
202 irq_map[i++] = cpu_to_be32(irqchip_phandle);
203 irq_map[i++] = cpu_to_be32(irq_nr);
204 if (s->aia_type != VIRT_AIA_TYPE_NONE) {
205 irq_map[i++] = cpu_to_be32(0x4);
206 }
207
208 if (!irq_map_stride) {
209 irq_map_stride = i;
210 }
211 irq_map += irq_map_stride;
212 }
213 }
214
215 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
216 GPEX_NUM_IRQS * GPEX_NUM_IRQS *
217 irq_map_stride * sizeof(uint32_t));
218
219 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
220 0x1800, 0, 0, 0x7);
221 }
222
223 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
224 char *clust_name, uint32_t *phandle,
225 bool is_32_bit, uint32_t *intc_phandles)
226 {
227 int cpu;
228 uint32_t cpu_phandle;
229 MachineState *mc = MACHINE(s);
230 char *name, *cpu_name, *core_name, *intc_name;
231
232 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
233 cpu_phandle = (*phandle)++;
234
235 cpu_name = g_strdup_printf("/cpus/cpu@%d",
236 s->soc[socket].hartid_base + cpu);
237 qemu_fdt_add_subnode(mc->fdt, cpu_name);
238 if (riscv_feature(&s->soc[socket].harts[cpu].env,
239 RISCV_FEATURE_MMU)) {
240 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
241 (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
242 } else {
243 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
244 "riscv,none");
245 }
246 name = riscv_isa_string(&s->soc[socket].harts[cpu]);
247 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
248 g_free(name);
249 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv");
250 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay");
251 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
252 s->soc[socket].hartid_base + cpu);
253 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
254 riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket);
255 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
256
257 intc_phandles[cpu] = (*phandle)++;
258
259 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
260 qemu_fdt_add_subnode(mc->fdt, intc_name);
261 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
262 intc_phandles[cpu]);
263 if (riscv_feature(&s->soc[socket].harts[cpu].env,
264 RISCV_FEATURE_AIA)) {
265 static const char * const compat[2] = {
266 "riscv,cpu-intc-aia", "riscv,cpu-intc"
267 };
268 qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible",
269 (char **)&compat, ARRAY_SIZE(compat));
270 } else {
271 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
272 "riscv,cpu-intc");
273 }
274 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
275 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
276
277 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
278 qemu_fdt_add_subnode(mc->fdt, core_name);
279 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle);
280
281 g_free(core_name);
282 g_free(intc_name);
283 g_free(cpu_name);
284 }
285 }
286
287 static void create_fdt_socket_memory(RISCVVirtState *s,
288 const MemMapEntry *memmap, int socket)
289 {
290 char *mem_name;
291 uint64_t addr, size;
292 MachineState *mc = MACHINE(s);
293
294 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
295 size = riscv_socket_mem_size(mc, socket);
296 mem_name = g_strdup_printf("/memory@%lx", (long)addr);
297 qemu_fdt_add_subnode(mc->fdt, mem_name);
298 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
299 addr >> 32, addr, size >> 32, size);
300 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
301 riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket);
302 g_free(mem_name);
303 }
304
305 static void create_fdt_socket_clint(RISCVVirtState *s,
306 const MemMapEntry *memmap, int socket,
307 uint32_t *intc_phandles)
308 {
309 int cpu;
310 char *clint_name;
311 uint32_t *clint_cells;
312 unsigned long clint_addr;
313 MachineState *mc = MACHINE(s);
314 static const char * const clint_compat[2] = {
315 "sifive,clint0", "riscv,clint0"
316 };
317
318 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
319
320 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
321 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
322 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
323 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
324 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
325 }
326
327 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
328 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
329 qemu_fdt_add_subnode(mc->fdt, clint_name);
330 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible",
331 (char **)&clint_compat,
332 ARRAY_SIZE(clint_compat));
333 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg",
334 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
335 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
336 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
337 riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket);
338 g_free(clint_name);
339
340 g_free(clint_cells);
341 }
342
343 static void create_fdt_socket_aclint(RISCVVirtState *s,
344 const MemMapEntry *memmap, int socket,
345 uint32_t *intc_phandles)
346 {
347 int cpu;
348 char *name;
349 unsigned long addr, size;
350 uint32_t aclint_cells_size;
351 uint32_t *aclint_mswi_cells;
352 uint32_t *aclint_sswi_cells;
353 uint32_t *aclint_mtimer_cells;
354 MachineState *mc = MACHINE(s);
355
356 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
357 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
358 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
359
360 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
361 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
362 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT);
363 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
364 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER);
365 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
366 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT);
367 }
368 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
369
370 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
371 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
372 name = g_strdup_printf("/soc/mswi@%lx", addr);
373 qemu_fdt_add_subnode(mc->fdt, name);
374 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
375 "riscv,aclint-mswi");
376 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
377 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
378 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
379 aclint_mswi_cells, aclint_cells_size);
380 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
381 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
382 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
383 g_free(name);
384 }
385
386 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
387 addr = memmap[VIRT_CLINT].base +
388 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket);
389 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE;
390 } else {
391 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
392 (memmap[VIRT_CLINT].size * socket);
393 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
394 }
395 name = g_strdup_printf("/soc/mtimer@%lx", addr);
396 qemu_fdt_add_subnode(mc->fdt, name);
397 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
398 "riscv,aclint-mtimer");
399 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
400 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
401 0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
402 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
403 0x0, RISCV_ACLINT_DEFAULT_MTIME);
404 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
405 aclint_mtimer_cells, aclint_cells_size);
406 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
407 g_free(name);
408
409 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
410 addr = memmap[VIRT_ACLINT_SSWI].base +
411 (memmap[VIRT_ACLINT_SSWI].size * socket);
412 name = g_strdup_printf("/soc/sswi@%lx", addr);
413 qemu_fdt_add_subnode(mc->fdt, name);
414 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
415 "riscv,aclint-sswi");
416 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
417 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
418 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
419 aclint_sswi_cells, aclint_cells_size);
420 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
421 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
422 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
423 g_free(name);
424 }
425
426 g_free(aclint_mswi_cells);
427 g_free(aclint_mtimer_cells);
428 g_free(aclint_sswi_cells);
429 }
430
431 static void create_fdt_socket_plic(RISCVVirtState *s,
432 const MemMapEntry *memmap, int socket,
433 uint32_t *phandle, uint32_t *intc_phandles,
434 uint32_t *plic_phandles)
435 {
436 int cpu;
437 char *plic_name;
438 uint32_t *plic_cells;
439 unsigned long plic_addr;
440 MachineState *mc = MACHINE(s);
441 static const char * const plic_compat[2] = {
442 "sifive,plic-1.0.0", "riscv,plic0"
443 };
444
445 if (kvm_enabled()) {
446 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
447 } else {
448 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
449 }
450
451 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
452 if (kvm_enabled()) {
453 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
454 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
455 } else {
456 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
457 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
458 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
459 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
460 }
461 }
462
463 plic_phandles[socket] = (*phandle)++;
464 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
465 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
466 qemu_fdt_add_subnode(mc->fdt, plic_name);
467 qemu_fdt_setprop_cell(mc->fdt, plic_name,
468 "#interrupt-cells", FDT_PLIC_INT_CELLS);
469 qemu_fdt_setprop_cell(mc->fdt, plic_name,
470 "#address-cells", FDT_PLIC_ADDR_CELLS);
471 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
472 (char **)&plic_compat,
473 ARRAY_SIZE(plic_compat));
474 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0);
475 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended",
476 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
477 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
478 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
479 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
480 riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
481 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
482 plic_phandles[socket]);
483
484 if (!socket) {
485 platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
486 memmap[VIRT_PLATFORM_BUS].base,
487 memmap[VIRT_PLATFORM_BUS].size,
488 VIRT_PLATFORM_BUS_IRQ);
489 }
490
491 g_free(plic_name);
492
493 g_free(plic_cells);
494 }
495
496 static uint32_t imsic_num_bits(uint32_t count)
497 {
498 uint32_t ret = 0;
499
500 while (BIT(ret) < count) {
501 ret++;
502 }
503
504 return ret;
505 }
506
507 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
508 uint32_t *phandle, uint32_t *intc_phandles,
509 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
510 {
511 int cpu, socket;
512 char *imsic_name;
513 MachineState *mc = MACHINE(s);
514 uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
515 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
516
517 *msi_m_phandle = (*phandle)++;
518 *msi_s_phandle = (*phandle)++;
519 imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2);
520 imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4);
521
522 /* M-level IMSIC node */
523 for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
524 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
525 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
526 }
527 imsic_max_hart_per_socket = 0;
528 for (socket = 0; socket < riscv_socket_count(mc); socket++) {
529 imsic_addr = memmap[VIRT_IMSIC_M].base +
530 socket * VIRT_IMSIC_GROUP_MAX_SIZE;
531 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
532 imsic_regs[socket * 4 + 0] = 0;
533 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
534 imsic_regs[socket * 4 + 2] = 0;
535 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
536 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
537 imsic_max_hart_per_socket = s->soc[socket].num_harts;
538 }
539 }
540 imsic_name = g_strdup_printf("/soc/imsics@%lx",
541 (unsigned long)memmap[VIRT_IMSIC_M].base);
542 qemu_fdt_add_subnode(mc->fdt, imsic_name);
543 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
544 "riscv,imsics");
545 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
546 FDT_IMSIC_INT_CELLS);
547 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
548 NULL, 0);
549 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
550 NULL, 0);
551 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
552 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
553 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
554 riscv_socket_count(mc) * sizeof(uint32_t) * 4);
555 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
556 VIRT_IRQCHIP_NUM_MSIS);
557 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
558 VIRT_IRQCHIP_IPI_MSI);
559 if (riscv_socket_count(mc) > 1) {
560 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
561 imsic_num_bits(imsic_max_hart_per_socket));
562 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
563 imsic_num_bits(riscv_socket_count(mc)));
564 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
565 IMSIC_MMIO_GROUP_MIN_SHIFT);
566 }
567 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
568
569 g_free(imsic_name);
570
571 /* S-level IMSIC node */
572 for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
573 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
574 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
575 }
576 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
577 imsic_max_hart_per_socket = 0;
578 for (socket = 0; socket < riscv_socket_count(mc); socket++) {
579 imsic_addr = memmap[VIRT_IMSIC_S].base +
580 socket * VIRT_IMSIC_GROUP_MAX_SIZE;
581 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
582 s->soc[socket].num_harts;
583 imsic_regs[socket * 4 + 0] = 0;
584 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
585 imsic_regs[socket * 4 + 2] = 0;
586 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
587 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
588 imsic_max_hart_per_socket = s->soc[socket].num_harts;
589 }
590 }
591 imsic_name = g_strdup_printf("/soc/imsics@%lx",
592 (unsigned long)memmap[VIRT_IMSIC_S].base);
593 qemu_fdt_add_subnode(mc->fdt, imsic_name);
594 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
595 "riscv,imsics");
596 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
597 FDT_IMSIC_INT_CELLS);
598 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
599 NULL, 0);
600 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
601 NULL, 0);
602 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
603 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
604 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
605 riscv_socket_count(mc) * sizeof(uint32_t) * 4);
606 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
607 VIRT_IRQCHIP_NUM_MSIS);
608 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
609 VIRT_IRQCHIP_IPI_MSI);
610 if (imsic_guest_bits) {
611 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
612 imsic_guest_bits);
613 }
614 if (riscv_socket_count(mc) > 1) {
615 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
616 imsic_num_bits(imsic_max_hart_per_socket));
617 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
618 imsic_num_bits(riscv_socket_count(mc)));
619 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
620 IMSIC_MMIO_GROUP_MIN_SHIFT);
621 }
622 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle);
623 g_free(imsic_name);
624
625 g_free(imsic_regs);
626 g_free(imsic_cells);
627 }
628
629 static void create_fdt_socket_aplic(RISCVVirtState *s,
630 const MemMapEntry *memmap, int socket,
631 uint32_t msi_m_phandle,
632 uint32_t msi_s_phandle,
633 uint32_t *phandle,
634 uint32_t *intc_phandles,
635 uint32_t *aplic_phandles)
636 {
637 int cpu;
638 char *aplic_name;
639 uint32_t *aplic_cells;
640 unsigned long aplic_addr;
641 MachineState *mc = MACHINE(s);
642 uint32_t aplic_m_phandle, aplic_s_phandle;
643
644 aplic_m_phandle = (*phandle)++;
645 aplic_s_phandle = (*phandle)++;
646 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
647
648 /* M-level APLIC node */
649 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
650 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
651 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
652 }
653 aplic_addr = memmap[VIRT_APLIC_M].base +
654 (memmap[VIRT_APLIC_M].size * socket);
655 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
656 qemu_fdt_add_subnode(mc->fdt, aplic_name);
657 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
658 qemu_fdt_setprop_cell(mc->fdt, aplic_name,
659 "#interrupt-cells", FDT_APLIC_INT_CELLS);
660 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
661 if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
662 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
663 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
664 } else {
665 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
666 msi_m_phandle);
667 }
668 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
669 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
670 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
671 VIRT_IRQCHIP_NUM_SOURCES);
672 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children",
673 aplic_s_phandle);
674 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate",
675 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
676 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
677 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle);
678 g_free(aplic_name);
679
680 /* S-level APLIC node */
681 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
682 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
683 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
684 }
685 aplic_addr = memmap[VIRT_APLIC_S].base +
686 (memmap[VIRT_APLIC_S].size * socket);
687 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
688 qemu_fdt_add_subnode(mc->fdt, aplic_name);
689 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
690 qemu_fdt_setprop_cell(mc->fdt, aplic_name,
691 "#interrupt-cells", FDT_APLIC_INT_CELLS);
692 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
693 if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
694 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
695 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
696 } else {
697 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
698 msi_s_phandle);
699 }
700 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
701 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
702 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
703 VIRT_IRQCHIP_NUM_SOURCES);
704 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
705 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
706
707 if (!socket) {
708 platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
709 memmap[VIRT_PLATFORM_BUS].base,
710 memmap[VIRT_PLATFORM_BUS].size,
711 VIRT_PLATFORM_BUS_IRQ);
712 }
713
714 g_free(aplic_name);
715
716 g_free(aplic_cells);
717 aplic_phandles[socket] = aplic_s_phandle;
718 }
719
720 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
721 bool is_32_bit, uint32_t *phandle,
722 uint32_t *irq_mmio_phandle,
723 uint32_t *irq_pcie_phandle,
724 uint32_t *irq_virtio_phandle,
725 uint32_t *msi_pcie_phandle)
726 {
727 char *clust_name;
728 int socket, phandle_pos;
729 MachineState *mc = MACHINE(s);
730 uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
731 uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
732
733 qemu_fdt_add_subnode(mc->fdt, "/cpus");
734 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
735 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
736 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0);
737 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
738 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
739
740 intc_phandles = g_new0(uint32_t, mc->smp.cpus);
741
742 phandle_pos = mc->smp.cpus;
743 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
744 phandle_pos -= s->soc[socket].num_harts;
745
746 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
747 qemu_fdt_add_subnode(mc->fdt, clust_name);
748
749 create_fdt_socket_cpus(s, socket, clust_name, phandle,
750 is_32_bit, &intc_phandles[phandle_pos]);
751
752 create_fdt_socket_memory(s, memmap, socket);
753
754 g_free(clust_name);
755
756 if (!kvm_enabled()) {
757 if (s->have_aclint) {
758 create_fdt_socket_aclint(s, memmap, socket,
759 &intc_phandles[phandle_pos]);
760 } else {
761 create_fdt_socket_clint(s, memmap, socket,
762 &intc_phandles[phandle_pos]);
763 }
764 }
765 }
766
767 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
768 create_fdt_imsic(s, memmap, phandle, intc_phandles,
769 &msi_m_phandle, &msi_s_phandle);
770 *msi_pcie_phandle = msi_s_phandle;
771 }
772
773 phandle_pos = mc->smp.cpus;
774 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
775 phandle_pos -= s->soc[socket].num_harts;
776
777 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
778 create_fdt_socket_plic(s, memmap, socket, phandle,
779 &intc_phandles[phandle_pos], xplic_phandles);
780 } else {
781 create_fdt_socket_aplic(s, memmap, socket,
782 msi_m_phandle, msi_s_phandle, phandle,
783 &intc_phandles[phandle_pos], xplic_phandles);
784 }
785 }
786
787 g_free(intc_phandles);
788
789 for (socket = 0; socket < riscv_socket_count(mc); socket++) {
790 if (socket == 0) {
791 *irq_mmio_phandle = xplic_phandles[socket];
792 *irq_virtio_phandle = xplic_phandles[socket];
793 *irq_pcie_phandle = xplic_phandles[socket];
794 }
795 if (socket == 1) {
796 *irq_virtio_phandle = xplic_phandles[socket];
797 *irq_pcie_phandle = xplic_phandles[socket];
798 }
799 if (socket == 2) {
800 *irq_pcie_phandle = xplic_phandles[socket];
801 }
802 }
803
804 riscv_socket_fdt_write_distance_matrix(mc, mc->fdt);
805 }
806
807 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
808 uint32_t irq_virtio_phandle)
809 {
810 int i;
811 char *name;
812 MachineState *mc = MACHINE(s);
813
814 for (i = 0; i < VIRTIO_COUNT; i++) {
815 name = g_strdup_printf("/soc/virtio_mmio@%lx",
816 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
817 qemu_fdt_add_subnode(mc->fdt, name);
818 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio");
819 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
820 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
821 0x0, memmap[VIRT_VIRTIO].size);
822 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
823 irq_virtio_phandle);
824 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
825 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts",
826 VIRTIO_IRQ + i);
827 } else {
828 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts",
829 VIRTIO_IRQ + i, 0x4);
830 }
831 g_free(name);
832 }
833 }
834
835 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
836 uint32_t irq_pcie_phandle,
837 uint32_t msi_pcie_phandle)
838 {
839 char *name;
840 MachineState *mc = MACHINE(s);
841
842 name = g_strdup_printf("/soc/pci@%lx",
843 (long) memmap[VIRT_PCIE_ECAM].base);
844 qemu_fdt_add_subnode(mc->fdt, name);
845 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells",
846 FDT_PCI_ADDR_CELLS);
847 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells",
848 FDT_PCI_INT_CELLS);
849 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2);
850 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
851 "pci-host-ecam-generic");
852 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci");
853 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0);
854 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0,
855 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
856 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0);
857 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
858 qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle);
859 }
860 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0,
861 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
862 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges",
863 1, FDT_PCI_RANGE_IOPORT, 2, 0,
864 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
865 1, FDT_PCI_RANGE_MMIO,
866 2, memmap[VIRT_PCIE_MMIO].base,
867 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
868 1, FDT_PCI_RANGE_MMIO_64BIT,
869 2, virt_high_pcie_memmap.base,
870 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
871
872 create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle);
873 g_free(name);
874 }
875
876 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap,
877 uint32_t *phandle)
878 {
879 char *name;
880 uint32_t test_phandle;
881 MachineState *mc = MACHINE(s);
882
883 test_phandle = (*phandle)++;
884 name = g_strdup_printf("/soc/test@%lx",
885 (long)memmap[VIRT_TEST].base);
886 qemu_fdt_add_subnode(mc->fdt, name);
887 {
888 static const char * const compat[3] = {
889 "sifive,test1", "sifive,test0", "syscon"
890 };
891 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible",
892 (char **)&compat, ARRAY_SIZE(compat));
893 }
894 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
895 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size);
896 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle);
897 test_phandle = qemu_fdt_get_phandle(mc->fdt, name);
898 g_free(name);
899
900 name = g_strdup_printf("/reboot");
901 qemu_fdt_add_subnode(mc->fdt, name);
902 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot");
903 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
904 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
905 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET);
906 g_free(name);
907
908 name = g_strdup_printf("/poweroff");
909 qemu_fdt_add_subnode(mc->fdt, name);
910 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff");
911 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
912 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
913 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS);
914 g_free(name);
915 }
916
917 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
918 uint32_t irq_mmio_phandle)
919 {
920 char *name;
921 MachineState *mc = MACHINE(s);
922
923 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base);
924 qemu_fdt_add_subnode(mc->fdt, name);
925 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a");
926 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
927 0x0, memmap[VIRT_UART0].base,
928 0x0, memmap[VIRT_UART0].size);
929 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
930 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle);
931 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
932 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
933 } else {
934 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4);
935 }
936
937 qemu_fdt_add_subnode(mc->fdt, "/chosen");
938 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
939 g_free(name);
940 }
941
942 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
943 uint32_t irq_mmio_phandle)
944 {
945 char *name;
946 MachineState *mc = MACHINE(s);
947
948 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
949 qemu_fdt_add_subnode(mc->fdt, name);
950 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
951 "google,goldfish-rtc");
952 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
953 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
954 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
955 irq_mmio_phandle);
956 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
957 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
958 } else {
959 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4);
960 }
961 g_free(name);
962 }
963
964 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
965 {
966 char *name;
967 MachineState *mc = MACHINE(s);
968 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
969 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
970
971 name = g_strdup_printf("/flash@%" PRIx64, flashbase);
972 qemu_fdt_add_subnode(mc->fdt, name);
973 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
974 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
975 2, flashbase, 2, flashsize,
976 2, flashbase + flashsize, 2, flashsize);
977 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
978 g_free(name);
979 }
980
981 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
982 {
983 char *nodename;
984 MachineState *mc = MACHINE(s);
985 hwaddr base = memmap[VIRT_FW_CFG].base;
986 hwaddr size = memmap[VIRT_FW_CFG].size;
987
988 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
989 qemu_fdt_add_subnode(mc->fdt, nodename);
990 qemu_fdt_setprop_string(mc->fdt, nodename,
991 "compatible", "qemu,fw-cfg-mmio");
992 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
993 2, base, 2, size);
994 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
995 g_free(nodename);
996 }
997
998 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
999 uint64_t mem_size, const char *cmdline, bool is_32_bit)
1000 {
1001 MachineState *mc = MACHINE(s);
1002 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
1003 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
1004 uint8_t rng_seed[32];
1005
1006 if (mc->dtb) {
1007 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
1008 if (!mc->fdt) {
1009 error_report("load_device_tree() failed");
1010 exit(1);
1011 }
1012 goto update_bootargs;
1013 } else {
1014 mc->fdt = create_device_tree(&s->fdt_size);
1015 if (!mc->fdt) {
1016 error_report("create_device_tree() failed");
1017 exit(1);
1018 }
1019 }
1020
1021 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu");
1022 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio");
1023 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2);
1024 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2);
1025
1026 qemu_fdt_add_subnode(mc->fdt, "/soc");
1027 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0);
1028 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus");
1029 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
1030 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
1031
1032 create_fdt_sockets(s, memmap, is_32_bit, &phandle,
1033 &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle,
1034 &msi_pcie_phandle);
1035
1036 create_fdt_virtio(s, memmap, irq_virtio_phandle);
1037
1038 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle);
1039
1040 create_fdt_reset(s, memmap, &phandle);
1041
1042 create_fdt_uart(s, memmap, irq_mmio_phandle);
1043
1044 create_fdt_rtc(s, memmap, irq_mmio_phandle);
1045
1046 create_fdt_flash(s, memmap);
1047 create_fdt_fw_cfg(s, memmap);
1048
1049 update_bootargs:
1050 if (cmdline && *cmdline) {
1051 qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
1052 }
1053
1054 /* Pass seed to RNG */
1055 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
1056 qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
1057 }
1058
1059 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
1060 hwaddr ecam_base, hwaddr ecam_size,
1061 hwaddr mmio_base, hwaddr mmio_size,
1062 hwaddr high_mmio_base,
1063 hwaddr high_mmio_size,
1064 hwaddr pio_base,
1065 DeviceState *irqchip)
1066 {
1067 DeviceState *dev;
1068 MemoryRegion *ecam_alias, *ecam_reg;
1069 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
1070 qemu_irq irq;
1071 int i;
1072
1073 dev = qdev_new(TYPE_GPEX_HOST);
1074
1075 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1076
1077 ecam_alias = g_new0(MemoryRegion, 1);
1078 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1079 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1080 ecam_reg, 0, ecam_size);
1081 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
1082
1083 mmio_alias = g_new0(MemoryRegion, 1);
1084 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1085 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1086 mmio_reg, mmio_base, mmio_size);
1087 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
1088
1089 /* Map high MMIO space */
1090 high_mmio_alias = g_new0(MemoryRegion, 1);
1091 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1092 mmio_reg, high_mmio_base, high_mmio_size);
1093 memory_region_add_subregion(get_system_memory(), high_mmio_base,
1094 high_mmio_alias);
1095
1096 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
1097
1098 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1099 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i);
1100
1101 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
1102 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
1103 }
1104
1105 return dev;
1106 }
1107
1108 static FWCfgState *create_fw_cfg(const MachineState *mc)
1109 {
1110 hwaddr base = virt_memmap[VIRT_FW_CFG].base;
1111 FWCfgState *fw_cfg;
1112
1113 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
1114 &address_space_memory);
1115 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
1116
1117 return fw_cfg;
1118 }
1119
1120 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
1121 int base_hartid, int hart_count)
1122 {
1123 DeviceState *ret;
1124 char *plic_hart_config;
1125
1126 /* Per-socket PLIC hart topology configuration string */
1127 plic_hart_config = riscv_plic_hart_config_string(hart_count);
1128
1129 /* Per-socket PLIC */
1130 ret = sifive_plic_create(
1131 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size,
1132 plic_hart_config, hart_count, base_hartid,
1133 VIRT_IRQCHIP_NUM_SOURCES,
1134 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1),
1135 VIRT_PLIC_PRIORITY_BASE,
1136 VIRT_PLIC_PENDING_BASE,
1137 VIRT_PLIC_ENABLE_BASE,
1138 VIRT_PLIC_ENABLE_STRIDE,
1139 VIRT_PLIC_CONTEXT_BASE,
1140 VIRT_PLIC_CONTEXT_STRIDE,
1141 memmap[VIRT_PLIC].size);
1142
1143 g_free(plic_hart_config);
1144
1145 return ret;
1146 }
1147
1148 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
1149 const MemMapEntry *memmap, int socket,
1150 int base_hartid, int hart_count)
1151 {
1152 int i;
1153 hwaddr addr;
1154 uint32_t guest_bits;
1155 DeviceState *aplic_m;
1156 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false;
1157
1158 if (msimode) {
1159 /* Per-socket M-level IMSICs */
1160 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1161 for (i = 0; i < hart_count; i++) {
1162 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
1163 base_hartid + i, true, 1,
1164 VIRT_IRQCHIP_NUM_MSIS);
1165 }
1166
1167 /* Per-socket S-level IMSICs */
1168 guest_bits = imsic_num_bits(aia_guests + 1);
1169 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1170 for (i = 0; i < hart_count; i++) {
1171 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),
1172 base_hartid + i, false, 1 + aia_guests,
1173 VIRT_IRQCHIP_NUM_MSIS);
1174 }
1175 }
1176
1177 /* Per-socket M-level APLIC */
1178 aplic_m = riscv_aplic_create(
1179 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size,
1180 memmap[VIRT_APLIC_M].size,
1181 (msimode) ? 0 : base_hartid,
1182 (msimode) ? 0 : hart_count,
1183 VIRT_IRQCHIP_NUM_SOURCES,
1184 VIRT_IRQCHIP_NUM_PRIO_BITS,
1185 msimode, true, NULL);
1186
1187 if (aplic_m) {
1188 /* Per-socket S-level APLIC */
1189 riscv_aplic_create(
1190 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size,
1191 memmap[VIRT_APLIC_S].size,
1192 (msimode) ? 0 : base_hartid,
1193 (msimode) ? 0 : hart_count,
1194 VIRT_IRQCHIP_NUM_SOURCES,
1195 VIRT_IRQCHIP_NUM_PRIO_BITS,
1196 msimode, false, aplic_m);
1197 }
1198
1199 return aplic_m;
1200 }
1201
1202 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)
1203 {
1204 DeviceState *dev;
1205 SysBusDevice *sysbus;
1206 const MemMapEntry *memmap = virt_memmap;
1207 int i;
1208 MemoryRegion *sysmem = get_system_memory();
1209
1210 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1211 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1212 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS);
1213 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size);
1214 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1215 s->platform_bus_dev = dev;
1216
1217 sysbus = SYS_BUS_DEVICE(dev);
1218 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {
1219 int irq = VIRT_PLATFORM_BUS_IRQ + i;
1220 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq));
1221 }
1222
1223 memory_region_add_subregion(sysmem,
1224 memmap[VIRT_PLATFORM_BUS].base,
1225 sysbus_mmio_get_region(sysbus, 0));
1226 }
1227
1228 static void virt_machine_done(Notifier *notifier, void *data)
1229 {
1230 RISCVVirtState *s = container_of(notifier, RISCVVirtState,
1231 machine_done);
1232 const MemMapEntry *memmap = virt_memmap;
1233 MachineState *machine = MACHINE(s);
1234 target_ulong start_addr = memmap[VIRT_DRAM].base;
1235 target_ulong firmware_end_addr, kernel_start_addr;
1236 uint32_t fdt_load_addr;
1237 uint64_t kernel_entry;
1238
1239 /*
1240 * Only direct boot kernel is currently supported for KVM VM,
1241 * so the "-bios" parameter is not supported when KVM is enabled.
1242 */
1243 if (kvm_enabled()) {
1244 if (machine->firmware) {
1245 if (strcmp(machine->firmware, "none")) {
1246 error_report("Machine mode firmware is not supported in "
1247 "combination with KVM.");
1248 exit(1);
1249 }
1250 } else {
1251 machine->firmware = g_strdup("none");
1252 }
1253 }
1254
1255 if (riscv_is_32bit(&s->soc[0])) {
1256 firmware_end_addr = riscv_find_and_load_firmware(machine,
1257 RISCV32_BIOS_BIN, start_addr, NULL);
1258 } else {
1259 firmware_end_addr = riscv_find_and_load_firmware(machine,
1260 RISCV64_BIOS_BIN, start_addr, NULL);
1261 }
1262
1263 if (machine->kernel_filename) {
1264 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
1265 firmware_end_addr);
1266
1267 kernel_entry = riscv_load_kernel(machine->kernel_filename,
1268 kernel_start_addr, NULL);
1269
1270 if (machine->initrd_filename) {
1271 hwaddr start;
1272 hwaddr end = riscv_load_initrd(machine->initrd_filename,
1273 machine->ram_size, kernel_entry,
1274 &start);
1275 qemu_fdt_setprop_cell(machine->fdt, "/chosen",
1276 "linux,initrd-start", start);
1277 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
1278 end);
1279 }
1280 } else {
1281 /*
1282 * If dynamic firmware is used, it doesn't know where is the next mode
1283 * if kernel argument is not set.
1284 */
1285 kernel_entry = 0;
1286 }
1287
1288 if (drive_get(IF_PFLASH, 0, 0)) {
1289 /*
1290 * Pflash was supplied, let's overwrite the address we jump to after
1291 * reset to the base of the flash.
1292 */
1293 start_addr = virt_memmap[VIRT_FLASH].base;
1294 }
1295
1296 /*
1297 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
1298 * tree cannot be altered and we get FDT_ERR_NOSPACE.
1299 */
1300 s->fw_cfg = create_fw_cfg(machine);
1301 rom_set_fw(s->fw_cfg);
1302
1303 /* Compute the fdt load address in dram */
1304 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
1305 machine->ram_size, machine->fdt);
1306 /* load the reset vector */
1307 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
1308 virt_memmap[VIRT_MROM].base,
1309 virt_memmap[VIRT_MROM].size, kernel_entry,
1310 fdt_load_addr);
1311
1312 /*
1313 * Only direct boot kernel is currently supported for KVM VM,
1314 * So here setup kernel start address and fdt address.
1315 * TODO:Support firmware loading and integrate to TCG start
1316 */
1317 if (kvm_enabled()) {
1318 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
1319 }
1320 }
1321
1322 static void virt_machine_init(MachineState *machine)
1323 {
1324 const MemMapEntry *memmap = virt_memmap;
1325 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
1326 MemoryRegion *system_memory = get_system_memory();
1327 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
1328 char *soc_name;
1329 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
1330 int i, base_hartid, hart_count;
1331
1332 /* Check socket count limit */
1333 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
1334 error_report("number of sockets/nodes should be less than %d",
1335 VIRT_SOCKETS_MAX);
1336 exit(1);
1337 }
1338
1339 /* Initialize sockets */
1340 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
1341 for (i = 0; i < riscv_socket_count(machine); i++) {
1342 if (!riscv_socket_check_hartids(machine, i)) {
1343 error_report("discontinuous hartids in socket%d", i);
1344 exit(1);
1345 }
1346
1347 base_hartid = riscv_socket_first_hartid(machine, i);
1348 if (base_hartid < 0) {
1349 error_report("can't find hartid base for socket%d", i);
1350 exit(1);
1351 }
1352
1353 hart_count = riscv_socket_hart_count(machine, i);
1354 if (hart_count < 0) {
1355 error_report("can't find hart count for socket%d", i);
1356 exit(1);
1357 }
1358
1359 soc_name = g_strdup_printf("soc%d", i);
1360 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
1361 TYPE_RISCV_HART_ARRAY);
1362 g_free(soc_name);
1363 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
1364 machine->cpu_type, &error_abort);
1365 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
1366 base_hartid, &error_abort);
1367 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
1368 hart_count, &error_abort);
1369 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
1370
1371 if (!kvm_enabled()) {
1372 if (s->have_aclint) {
1373 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
1374 /* Per-socket ACLINT MTIMER */
1375 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1376 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1377 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1378 base_hartid, hart_count,
1379 RISCV_ACLINT_DEFAULT_MTIMECMP,
1380 RISCV_ACLINT_DEFAULT_MTIME,
1381 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1382 } else {
1383 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
1384 riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
1385 i * memmap[VIRT_CLINT].size,
1386 base_hartid, hart_count, false);
1387 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1388 i * memmap[VIRT_CLINT].size +
1389 RISCV_ACLINT_SWI_SIZE,
1390 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1391 base_hartid, hart_count,
1392 RISCV_ACLINT_DEFAULT_MTIMECMP,
1393 RISCV_ACLINT_DEFAULT_MTIME,
1394 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1395 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
1396 i * memmap[VIRT_ACLINT_SSWI].size,
1397 base_hartid, hart_count, true);
1398 }
1399 } else {
1400 /* Per-socket SiFive CLINT */
1401 riscv_aclint_swi_create(
1402 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
1403 base_hartid, hart_count, false);
1404 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1405 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
1406 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
1407 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
1408 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1409 }
1410 }
1411
1412 /* Per-socket interrupt controller */
1413 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
1414 s->irqchip[i] = virt_create_plic(memmap, i,
1415 base_hartid, hart_count);
1416 } else {
1417 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests,
1418 memmap, i, base_hartid,
1419 hart_count);
1420 }
1421
1422 /* Try to use different IRQCHIP instance based device type */
1423 if (i == 0) {
1424 mmio_irqchip = s->irqchip[i];
1425 virtio_irqchip = s->irqchip[i];
1426 pcie_irqchip = s->irqchip[i];
1427 }
1428 if (i == 1) {
1429 virtio_irqchip = s->irqchip[i];
1430 pcie_irqchip = s->irqchip[i];
1431 }
1432 if (i == 2) {
1433 pcie_irqchip = s->irqchip[i];
1434 }
1435 }
1436
1437 if (riscv_is_32bit(&s->soc[0])) {
1438 #if HOST_LONG_BITS == 64
1439 /* limit RAM size in a 32-bit system */
1440 if (machine->ram_size > 10 * GiB) {
1441 machine->ram_size = 10 * GiB;
1442 error_report("Limiting RAM size to 10 GiB");
1443 }
1444 #endif
1445 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
1446 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
1447 } else {
1448 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
1449 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
1450 virt_high_pcie_memmap.base =
1451 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
1452 }
1453
1454 /* register system main memory (actual RAM) */
1455 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
1456 machine->ram);
1457
1458 /* boot rom */
1459 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
1460 memmap[VIRT_MROM].size, &error_fatal);
1461 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
1462 mask_rom);
1463
1464 /* SiFive Test MMIO device */
1465 sifive_test_create(memmap[VIRT_TEST].base);
1466
1467 /* VirtIO MMIO devices */
1468 for (i = 0; i < VIRTIO_COUNT; i++) {
1469 sysbus_create_simple("virtio-mmio",
1470 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
1471 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i));
1472 }
1473
1474 gpex_pcie_init(system_memory,
1475 memmap[VIRT_PCIE_ECAM].base,
1476 memmap[VIRT_PCIE_ECAM].size,
1477 memmap[VIRT_PCIE_MMIO].base,
1478 memmap[VIRT_PCIE_MMIO].size,
1479 virt_high_pcie_memmap.base,
1480 virt_high_pcie_memmap.size,
1481 memmap[VIRT_PCIE_PIO].base,
1482 DEVICE(pcie_irqchip));
1483
1484 create_platform_bus(s, DEVICE(mmio_irqchip));
1485
1486 serial_mm_init(system_memory, memmap[VIRT_UART0].base,
1487 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
1488 serial_hd(0), DEVICE_LITTLE_ENDIAN);
1489
1490 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
1491 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
1492
1493 virt_flash_create(s);
1494
1495 for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
1496 /* Map legacy -drive if=pflash to machine properties */
1497 pflash_cfi01_legacy_drive(s->flash[i],
1498 drive_get(IF_PFLASH, 0, i));
1499 }
1500 virt_flash_map(s, system_memory);
1501
1502 /* create device tree */
1503 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
1504 riscv_is_32bit(&s->soc[0]));
1505
1506 s->machine_done.notify = virt_machine_done;
1507 qemu_add_machine_init_done_notifier(&s->machine_done);
1508 }
1509
1510 static void virt_machine_instance_init(Object *obj)
1511 {
1512 }
1513
1514 static char *virt_get_aia_guests(Object *obj, Error **errp)
1515 {
1516 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1517 char val[32];
1518
1519 sprintf(val, "%d", s->aia_guests);
1520 return g_strdup(val);
1521 }
1522
1523 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp)
1524 {
1525 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1526
1527 s->aia_guests = atoi(val);
1528 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) {
1529 error_setg(errp, "Invalid number of AIA IMSIC guests");
1530 error_append_hint(errp, "Valid values be between 0 and %d.\n",
1531 VIRT_IRQCHIP_MAX_GUESTS);
1532 }
1533 }
1534
1535 static char *virt_get_aia(Object *obj, Error **errp)
1536 {
1537 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1538 const char *val;
1539
1540 switch (s->aia_type) {
1541 case VIRT_AIA_TYPE_APLIC:
1542 val = "aplic";
1543 break;
1544 case VIRT_AIA_TYPE_APLIC_IMSIC:
1545 val = "aplic-imsic";
1546 break;
1547 default:
1548 val = "none";
1549 break;
1550 };
1551
1552 return g_strdup(val);
1553 }
1554
1555 static void virt_set_aia(Object *obj, const char *val, Error **errp)
1556 {
1557 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1558
1559 if (!strcmp(val, "none")) {
1560 s->aia_type = VIRT_AIA_TYPE_NONE;
1561 } else if (!strcmp(val, "aplic")) {
1562 s->aia_type = VIRT_AIA_TYPE_APLIC;
1563 } else if (!strcmp(val, "aplic-imsic")) {
1564 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC;
1565 } else {
1566 error_setg(errp, "Invalid AIA interrupt controller type");
1567 error_append_hint(errp, "Valid values are none, aplic, and "
1568 "aplic-imsic.\n");
1569 }
1570 }
1571
1572 static bool virt_get_aclint(Object *obj, Error **errp)
1573 {
1574 MachineState *ms = MACHINE(obj);
1575 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
1576
1577 return s->have_aclint;
1578 }
1579
1580 static void virt_set_aclint(Object *obj, bool value, Error **errp)
1581 {
1582 MachineState *ms = MACHINE(obj);
1583 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
1584
1585 s->have_aclint = value;
1586 }
1587
1588 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1589 DeviceState *dev)
1590 {
1591 MachineClass *mc = MACHINE_GET_CLASS(machine);
1592
1593 if (device_is_dynamic_sysbus(mc, dev)) {
1594 return HOTPLUG_HANDLER(machine);
1595 }
1596 return NULL;
1597 }
1598
1599 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1600 DeviceState *dev, Error **errp)
1601 {
1602 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev);
1603
1604 if (s->platform_bus_dev) {
1605 MachineClass *mc = MACHINE_GET_CLASS(s);
1606
1607 if (device_is_dynamic_sysbus(mc, dev)) {
1608 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev),
1609 SYS_BUS_DEVICE(dev));
1610 }
1611 }
1612 }
1613
1614 static void virt_machine_class_init(ObjectClass *oc, void *data)
1615 {
1616 char str[128];
1617 MachineClass *mc = MACHINE_CLASS(oc);
1618 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1619
1620 mc->desc = "RISC-V VirtIO board";
1621 mc->init = virt_machine_init;
1622 mc->max_cpus = VIRT_CPUS_MAX;
1623 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
1624 mc->pci_allow_0_address = true;
1625 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
1626 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
1627 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
1628 mc->numa_mem_supported = true;
1629 mc->default_ram_id = "riscv_virt_board.ram";
1630 assert(!mc->get_hotplug_handler);
1631 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1632
1633 hc->plug = virt_machine_device_plug_cb;
1634
1635 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1636 #ifdef CONFIG_TPM
1637 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
1638 #endif
1639
1640 object_class_property_add_bool(oc, "aclint", virt_get_aclint,
1641 virt_set_aclint);
1642 object_class_property_set_description(oc, "aclint",
1643 "Set on/off to enable/disable "
1644 "emulating ACLINT devices");
1645
1646 object_class_property_add_str(oc, "aia", virt_get_aia,
1647 virt_set_aia);
1648 object_class_property_set_description(oc, "aia",
1649 "Set type of AIA interrupt "
1650 "conttoller. Valid values are "
1651 "none, aplic, and aplic-imsic.");
1652
1653 object_class_property_add_str(oc, "aia-guests",
1654 virt_get_aia_guests,
1655 virt_set_aia_guests);
1656 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value "
1657 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS);
1658 object_class_property_set_description(oc, "aia-guests", str);
1659 }
1660
1661 static const TypeInfo virt_machine_typeinfo = {
1662 .name = MACHINE_TYPE_NAME("virt"),
1663 .parent = TYPE_MACHINE,
1664 .class_init = virt_machine_class_init,
1665 .instance_init = virt_machine_instance_init,
1666 .instance_size = sizeof(RISCVVirtState),
1667 .interfaces = (InterfaceInfo[]) {
1668 { TYPE_HOTPLUG_HANDLER },
1669 { }
1670 },
1671 };
1672
1673 static void virt_machine_init_register_types(void)
1674 {
1675 type_register_static(&virt_machine_typeinfo);
1676 }
1677
1678 type_init(virt_machine_init_register_types)
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